JPH0213360B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-channel analog signal calculation circuit used in a multi-channel analog amount adjustment/setting device such as a stage light control device or an audio mixer.

FIG. 1 shows an example of a signal calculation circuit of a conventional light control device. The preset faders f ₁₁ to _{f 3n} are m channels x 3 stages, and the 2 stages selected by the stage selection section 1 are
A signal crossed by cross faders A and B between the two stages is output. (Although not shown, dimmer units for controlling power to the lighting loads are connected to the outputs u ₁ to _{u n} , respectively.) The switches s ₁₁ to _{s 3n} perform the cross operation and the cross fader for each channel. 1 stage preset fader f ₁₁ regardless of A and B
~F _3n only operation and crossfader A, B
It is called a PFG switch, which can select 2+k operations, including an operation based on the product of the one-stage preset faders f ₁₁ to f _3n and any of the group faders g ₁ to g _k , regardless of the The PFG switches s ₁₁ to s _3n in the stages move in conjunction. X is a buffer that outputs the input voltage as it is with low impedance, and Y is an adder. Here, the number of channels m
Since there are usually tens to hundreds of wires, the number of wires for this device is enormous. Furthermore, three multi-contact PFG switches s ₁₁ to s _3n are required to change the signal to be calculated for each channel, and an adder Y is also required for each channel. Furthermore, group faders g ₁ to g _k are often provided which are subordinate to other cross faders A and B, and in that case, the number of wiring lines and the number of switch contacts will further increase. Furthermore, there are many cases in which the number of stages is four or more, in which case the PFG switches s ₁₁ to s _3n need to have multiple circuits, resulting in the problem of an increase in the number of wiring lines.

Also multiplexer MPX _1-1 , MPX _1-2 ,
MPX _2-1 , MPX _2-2 and sample hold circuit S/
A circuit as shown in Fig. 2 is constructed with H, memory 3, counter 4, buffers X, X, adder ADD, etc.
Calculation of the faders F such as the group fader and cross fader is performed by sending the signals of these faders F to the preset fader _f11 to groups through the multiplexers MPX _2-1 and MPX _2-2 , as in the conventional example shown in FIG. A method has been proposed in the past in which the outputs of these preset faders f ₁₁ ~ are multiplexed by multiplexers MPX _1-1 and MPX _1-2 . It is necessary to send signals to many preset faders _F11 ~, which requires an amplifier with a large output current, as well as multiplexers MPX _2-1 and MPX _2-2 .
Since large currents are multiplexed at low frequencies, multiplexing is only possible at low frequencies, which poses problems in terms of signal transmission speed and accuracy.

The present invention has been provided in view of the above-mentioned points, and provides a multi-channel analog signal that reduces the number of wires in the device and reduces the number of electrical components used, thereby making it possible to achieve miniaturization and cost reduction of the device. Its purpose is to provide an arithmetic circuit.

An embodiment in which the present invention is applied to a dimming signal calculation circuit of a stage dimming device will be described in detail below with reference to the drawings. FIG. 3 is the simplest embodiment of the invention.
The signals from the preset faders f ₁ to f _n are time-divided by a multiplexer MPX and output onto a single line.
This multiplexed signal is multiplied by the signal of fader A by multiplier Z. The output of multiplier Z is input to sample and hold circuit S/H,
The signal is returned to the m-system signal again. multiplexer
MPX and sample hold circuit S/H are controlled in synchronization by the output of counter 4. In other words, the signal of preset fader _f1 is sent to the multiplexer.
When the signal is output from MPX, the sample and hold circuit S/H samples it as a signal to be output to u _1. Similarly, when the signal of f ₂ is output from the multiplexer MPX, the sample and hold circuit S/H
is controlled in such a way that it is sampled as a signal output to _u2 . Therefore, if the output of the multiplexer MPX is directly input to the sample and hold circuit S/H and not passed through the multiplier Z, f ₁ to _{f n}
The signals appear as they are at u ₁ to _{u n} . By inserting the multiplier Z in between, in this case, the signals of f ₁ to f _n are all multiplied by the signal of fader A, and appear on u ₁ to _{u n} , and fader A becomes the master fader. It will function as a da. Here, instead of fader A, 7 of the circuit shown in FIG.
If you use the circuit of the part, the preset fader f ₁ ~
Instead of multiplying all f _n signals by the same signal, you can select different signals and multiply them. In other words, in that case, the fader G ₁ in the circuit of FIG.
~G _k will function as a group fader. Also, at this time, RAM is used as memory 2, and the output signal of counter 4 is connected to its address input in the same way as multiplexer MPX and sample hold circuit 2, and the data outputs of faders G ₁ to G _k are connected to multiplexer MPX ₄ . Therefore, the feeders _G1 to _Gk are subjected to multiplex control. Although the memory 2 is not shown, if the data contents can be rewritten by another ordinary circuit, the preset fader _f1
It is possible to freely set which group faders G ₁ to _{G k} each of ~f _n is subordinated to.
OSC is an oscillation circuit for providing counting input to the counter 4.

FIG. 4 shows another embodiment of the invention. The preset fader has two stages, f ₁₁ - f _1n and f ₂₁ - f _2n , and multiplexer MPX ₁ multiplexes the f ₁₁ - f _1n signals, and multiplexer MPX ₂ multiplexes the signals of f 11 - f 1n.
Multiplex the f ₂₁ to f _2n signals. The output of multiplexer MPX ₁ and the signal of crossfader A are multiplied by multiplier Z ₁ ,
MPX ₂ output and crossfader B signal are multiplier
The outputs of both multipliers Z _{1 and} Z ₂ are added together by an adder ADD. The above calculation results are distributed to dimming signals of each channel by the sample and hold circuit S/H. The multiplexers MPX ₁ and MPX ₂ and the sample and hold circuit S/H operate in synchronization with the signal from the counter 4. In other words, when the number of preset faders f _1i is output from multiplexer MPX ₁ ,
The output of preset fader f _2i is multiplexed.
Output from MPX ₂ , sample and hold circuit S/
H samples the input as the output of u _i . Therefore, a signal u _i =f _1i ×A + f _2i × _B is output, and A and B function as cross faders.

FIG. 5 shows yet another embodiment of the invention. The system has three stages of preset faders _f11 to _f3n , cross faders A and B, and group faders _G1 to _Gk . A switch in the stage selection section 1 selects which stage and between which stages the cross operation is to be performed. 6 is a cross operation or whether group faders G 1 to G _k are applied to the first stage preset faders f ₁₁ to f _3n regardless of the states of the cross faders A, B and the switches in the stage selection section ₁ . This is a switching unit for switching. If this switching unit 6 is in the state as shown in the figure, two multipliers Z ₁ and Z ₂
A multiplexer of stages according to the stage selection, respectively.
Since the outputs of MPX ₁ to MPX ₃ and the outputs of cross faders A and B are input, a cross operation is performed.
If the switch of the switching section 6 is reversely switched, the output of the multiplexer MPX ₁ is multiplied by the output of the multiplexer MPX ₄ of the circuit section 7, resulting in a group operation. In this way, the circuit sections 6 and 7 can select for each channel, depending on the contents of the memory 5, the cross by the faders A and B, or the operation by any of the group faders _G1 to _Gk . This part can be used to form a so-called PFG switch, which has conventionally been complicated, using a simple circuit. Furthermore, in this embodiment, data regarding the state of the PFG switch is stored in the memory 5, so by using semiconductor memory, data can be stored efficiently and costs can be reduced. By switching and using PFG states (can be at different addresses in memory), PFG states can be prepared for multiple scenes, and other effects can be set without erasing the PFG state once set. There is.

The embodiment shown in FIG. 6 is an embodiment in which the inventions of claims 2 and 3 are applied to the invention of claim 1, and is a preset fader. There are two stages of f ₁₁ to f _2n , and cross faders A and B are used to perform cross operation.The function is the same as that of the circuit shown in FIG. 4, but the circuit of this embodiment shown in FIG. In this case, instead of dividing the multiplexers MPX ₁ and MPX ₂ into two systems for each stage as in the embodiment shown in FIG. 4, all of them can be completely integrated into one signal line using one multiplexer MPX, and the multiplier Z can also be reduced to one. ing. Thus, when any one of the first stage preset faders f ₁₁ to _{f 1n} is output to the multiplexer MPX output, the changeover switch s is closed to the fader A side, and the second stage preset fader f ₂₁ to f 1n is output. The changeover switch s is controlled by the counter 4 so that it closes to the fader B side when any one of f _2n is being output. Therefore, for the multiplexer MPX output signal as shown in FIG. 7a, the output waveform of the multiplier Z becomes as shown in FIG. 7b. The signal in b of the same figure is added and sampled by an operation of integrating only the section in which the signal of that channel is multiplexed for each channel by the integrator/hold circuit H, and holding the value. Perform both holds at the same time. Specific examples of the integration and hold circuit H are shown in FIGS. 8 to 10. In the case of the circuit shown in Figure 8, switch
s ₀ and low pass filter LPF are the configuration requirements,
By further adding a voltage follower/doubling amplifier circuit VF, the impedance and level become convenient. If the switch s ₀ ... is closed in such a way that it produces an output u ₁ controlled by the counter 4,
This switch s ₀ closes only in the integral interval shown in Figure 7c, so if the time constant R ₁ C ₁ is set sufficiently large, the switch s ₀ closes repeatedly.
The average value of Af ₁₁ and Bf ₂₁ becomes Af ₁₁ +Bf ₂₁ /2. Therefore, by setting R ₂ =R ₃ and amplifying the signal twice, u ₂ =Af ₁₁ +Bf ₂₁ is obtained. low pass filter
The response speed can be increased by improving the cut-off characteristics of the LPF, and the response speed can be further improved by using an active low-pass filter as shown in FIG. Figure 10 further speeds up the response, and instead of responding by repeatedly opening and closing switch _s1 , it integrates the area in which switch _s1 is closed every cycle, and samples and holds the resulting value. 11 is an integrating circuit section, and 12 is a sample and hold circuit section. _s3 is a switch for sample and hold, and _s2 is a switch for resetting the integral value by closing it until the next cycle. Through such an operation, a cross dimming operation between two stages is performed. Here, if the output of counter 4 is made up of _k bits of _{c 0} , _{c 1} . If c ₀ is used to switch the switch s, and c ₁ to c _k are used to control the integration/hold circuit H, an operation as shown in the timing chart in FIG. 7 can be obtained. Also, use c _k to change the changeover switch s,
A similar operation is possible even if c ₀ to _{c k-1} are used to control the integration/hold circuit H. In this way, by using the integration and hold circuit H according to the embodiment of claim 2, cross operation is possible even if two stages of preset faders are multiplexed together. As will be explained later, there is an advantage that multiplication by pulse width modulation is also possible.

FIG. 11 shows an example in which the embodiments of claims 3 and 4 of the present invention are applied. The multiplexed signal is sent to fader A by a multiplier.
Instead of multiplying the signal by the signal from the fader A, the multiplication is performed by pulse width modulation (PWM) to a pulse width proportional to the signal of the fader A, and then integrating and holding it in an integrating/holding circuit H. Here, the output waveform of the multiplexer MPX is as shown in FIG. 12a. On the other hand, the signal from fader A and the triangular wave synchronized with the count input to counter 4 are compared by comparator Comp to convert it into a pulse width modulation signal, and this signal controls switch s (or analog gate). Then, the pulse train is converted into a pulse train whose pulse width is proportional to the signal of fader A while keeping the amplitudes f ₁ , f ₂ , . . . as shown in FIG. If this signal is integrated and held in synchronization with the multiplexer MPX, the output will be an output corresponding to the area of the pulse shown in b in the figure, that is, the output of the multiplexer MPX multiplied by the signal of fader A,
The operation is the same as that of the circuit of the embodiment shown in FIG. In this case, the integrating/holding circuit H is suitably the circuit shown in FIGS. 8 to 10 without the doubling circuit. Further, a circuit for generating a PWM triangular wave synchronized with a counting rectangular wave to the counter 4 can be realized by a circuit configuration as shown in FIG. 13, for example. That is, an integrating circuit is formed by the operational amplifier _OP1 , the resistor _R1 , and the capacitor _C1 , and a triangular wave output is obtained by integrating the rectangular wave output from the operational amplifier _OP2 . Here, the input of operational amplifier OP ₂ is used to provide the upper and lower limits of the triangular wave and invert the output of operational amplifier OP ₂ when the input attempts to exceed that range. The lower limit is O _v and the upper limit is “H” of inverter I
The output voltage is divided by resistors R ₃ and R ₄ .
The triangular wave obtained at this time does not have to be an isosceles triangle as long as the rise and fall are linear, and it may be a sawtooth wave.
This also applies to the embodiments shown in FIGS. 4 and 16. In addition, the circuit in Figure 11 has a switch s separate from the multiplexer MPX and the integral/hold circuit H, but this switch s can be eliminated and the multiplexer
You can use the multiplexer switch built into the MPX, or you can use the switch at the integral circuit input section built into the integration/hold circuit H.

FIG. 14 shows an example in which the embodiments of claims 2 to 4 of the present invention are applied. The signals from the two-stage preset faders f ₁₁ to f _2n are multiplexed at once by the multiplexer MPX, and the signals from the cross faders A and B are multiplexed together with the integration/hold circuit H.
Alternatively, the PFG selection function is obtained by performing pulse width modulation using the signals of the group faders _g1 to _gk . FIG. 15a shows an output waveform of the multiplexer MPX, and FIG. 15b shows an example of the input waveform to the integrating/holding circuit H after being pulse width modulated by the switch s. In this way, the multiplexer MPX ₂ is controlled by the contents of the memory 5, and selects one of the signals of the faders A, B, g ₁ , ..., g _k or O _v and inputs it to the comparator Comp. . In Fig. 15 time chart, signal u ₁
is the value obtained by crossing the signals of preset faders f ₁₁ and f ₂₁ with the signals of faders A and B. Signal u ₂ is the value obtained by multiplying fader f ₁₂ by group fader g ₁ , and is the signal u ₃ . is preset fader f ₁₃ , f ₂₃
Each crossed value will be output. As described above, according to the embodiment of FIG. 14, multiplication and addition for cross operation, and multiplication for group operation can be realized with a very simple circuit, and in the case of such a PFG switching method, ,
Cross faders A, B and group faders g ₁ , g ₂
There is no difference in the wiring between the two, and the functions are only differentiated depending on the contents of the memory 5, so there is an effect that it is possible to change the function of the fader without changing the wiring.

FIG. 16 shows another embodiment to which the embodiments of claims 2 to 4 of the present invention are applied.
There are three stages of preset faders f ₁₁ to f _3n , which two
The light control device has a stage selection function that selects whether to cross between two stages. Multiplexer for each channel in turn by counter 4
When controlling MPX ₁ and the integrating/holding circuit H, the time for one channel is divided into two equal parts, and the crossing signals of the two stages of preset faders f ₁₁ to f _3n are alternately output from the multiplexer MPX ₁ . However, if the channel is selected to be subordinate to the group faders g ₁ to g _k according to the contents of the memory 5, the one-stage preset is selected for one half of the time divided by the free/cross switching section FC. feeder
Outputs _f11 to _f3n signals. By doing this, all of the preset faders f ₁₁ to f _3n are not multiplexed, but only the necessary signals are multiplexed. Multiplexer MPX ₁ connects signals Ga ₁ to _{Ga 3}
Outputs the signals of the preset faders f ₁₁ to f _3n of the channel specified by the bits other than the least significant bit (ms _B ) of the output of the counter 4 in the stage where the output is "H". In this example, group fader g ₁ ~
g _k functions as a so-called free group fader that is unrelated to the cross operation, but in many cases a group fader that is subordinate to the cross fader, so-called cross group fader, is required, and the circuit that enables the cross group fader is the 17th circuit. It is a diagram. It is sufficient to replace only the circuit around the multiplexer MPX ₂ in FIG. 16 with the circuit shown in FIG. 17. X is Batsuhua. The switch _s2 is a switch for selectively switching between using the group faders _g1 to _gk as free group faders or cross group faders depending on the contents of the memory ₅ . Group feeder g ₁ ~ g _k
When using as a cross group fader, set the group fader to the two equal times as described above.
This is for switching g ₁ to g _k so that they are alternately dependent on each of the two crossfaders A and B. In this way, according to the embodiment shown in FIG. 16, the signals of the preset faders f ₁₁ to _{f 3n} are multiplied in a time-division manner, so the signals to be multiplied also need to be time-divisionally multiplied, which can only be accomplished using a conventionally very complicated method. The function of the cross group fader, which was previously unavailable, can be easily achieved, and the group faders g ₁ to g _k can also be easily switched and used as both free group faders and cross group faders. be.

FIG. 18 shows an embodiment based on the embodiment of claim 5 of the present invention, in which a function as an electronic crossbar device is added to the embodiment of FIG. 3 described above. However, the difference from the circuit of the embodiment shown in FIG. 3 is that the multiplexer MPX and the sample and hold circuit S/H are not operated by the same output from the counter 4, but only the sample and hold circuit S/H is controlled by the output from the counter 4. However, the output of the counter 4 is input as the address of the memory 5, and the output data of the memory 5 is used to control the multiplexer MPX. By doing this, the preset fader f ₁ ~
The operation signal of the m channel corresponding to f _n is the signal u ₁ ~
Can be assigned to the lighting load circuit corresponding to u _o . Further, if the contents of the memory 5 can be rewritten using another known circuit (not shown), the allocation state, that is, the connection state can be changed. Here, the embodiment of claim 5 of the present invention is as in the embodiment shown in FIG. 18 above,
In addition to being applicable to the embodiment shown in FIG. 3 described above, it is also applicable to all embodiments of each embodiment of the present invention. If the memory 5 for storing the PFG state is already provided as in the embodiment of FIG. 16, this memory 5 can also be used as a memory for the electronic crossbar, or As mentioned in the explanation, if a plurality of PFG states and connection states of electronic crossbar devices can be stored, switching of both states can be performed in conjunction with each other, making it convenient to use. In this way, in the case of the dimming signal calculation circuit according to the embodiments of claims 1 to 4 of the present invention, even an electronic crossbar function can be provided with a small addition, and the entire dimming system can be improved. This makes it possible to create something extremely lean, low cost, compact, and with a small number of wires.

FIG. 19 is an embodiment in which the embodiments of claims 2 and 6 of the present invention are combined.
That is, the signals from the preset faders _f1 to _fn are multiplexed and pulse width modulated at the same time, and the integration and hold circuit H performs demultiplexing and demodulation of the pulse width modulated signals. The output waveform of the multiplexer MPX is similar to that of the embodiment of FIG. 11, and is as shown in FIG. 20a. This signal of figure a and counter 4
A comparator connects the count input to the triangular wave synchronized with the
By comparing the outputs with Comp, the outputs are converted into a pulse train whose pulse height is constant and whose width is proportional to the outputs of the preset faders _f1 to _fn , respectively, as shown in FIG. The signals of the preset faders f ₁ to _{f n} are reproduced by integrating and holding the signal by the counter 4 in the integrating/holding circuit H in synchronization with the multiplexer MPX. In this way, according to the embodiment of claim 6 of the present invention, the unified signal becomes a digital signal whose peak value has no meaning, so signal transmission is advantageous.
For example, it will be easier to introduce optical fiber,
Can be resistant to noise. In addition, when performing calculations where the signals are unified, Figures 3, 4, and 5
The arithmetic circuits in the embodiments shown in FIGS.
It can be placed at the or position in the circuit shown in Figure 9.

In the present invention, in all the embodiments described above, counters are used to perform sample hold and integral hold in order, but the order does not matter.
It only needs to operate in conjunction with the multiplexer, and therefore a control signal from a microcomputer or the like may be provided instead of the counter.

Further, although the present invention is effectively applied to a stage light control device as described above, it can also be applied to other multi-channel analog signal processing devices, such as an audio mixer.

Since the present invention is configured as described above, it is possible to greatly reduce the number of wires in the device, and it is only necessary to provide one arithmetic circuit, which conventionally required a large number of circuits. It has the effect of easily achieving miniaturization and cost reduction, and by controlling the arithmetic circuit, it can be easily realized by electronic circuits.
The PFG selection function also has the effect of being easily added.

Moreover, there is no need to send signals to many preset faders via buffers as in the past, and this eliminates the need for an amplifier with a large output current.
Furthermore, since a large current does not flow through the multiplexer, multiplexing can be performed at a high frequency, increasing the signal transmission speed and improving accuracy.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a conventional example, Fig. 2 is a circuit diagram of another conventional example, Fig. 3 is a circuit diagram of an embodiment of the present invention, and Fig. 4 is a circuit diagram of a conventional example.
The figure is a circuit diagram of another embodiment same as above, FIG. 5 is a circuit diagram of still another embodiment same as above, and FIG. 6 is a combination of claims 1, 2, and 3 of the present invention. Figures 7a, b, and c are the same time charts as above; Figures 8 to 10 are circuit diagrams of the integrating and holding circuits used in the Figure 6 circuit;
Figure 1 shows claims 1 and 3 of the present invention.
Circuit diagram of an embodiment corresponding to the combination of item 4, 1st
2a and 2b are the same time charts as above, FIG. 13 is a circuit diagram of a triangular wave generation circuit used in the circuit of FIG. 11, and FIG. 14 is a claim 1 and 2 of the present invention.
15a and 15b are time charts of the same, and FIG. 16 is the claim 1 of the present invention.
17 is a circuit diagram of another embodiment corresponding to the combination of items 2, 3, and 4; FIG. FIG. 18 is a circuit diagram of an embodiment corresponding to the combination of claims 1 and 5 of the present invention, and FIG. 19 is a circuit diagram of an embodiment corresponding to the combination of claims 1 to 6 of the present invention. The circuit diagram of the embodiment, FIGS. 20a and 20b are the same time charts as above,
MPX is a multiplexer, S/H is a sample hold circuit, H is an integration/hold circuit, and f ₁ , f ₁₁ . . . are preset faders.

Claims (1)

[Claims] 1. In a multi-channel signal calculation circuit such as a stage light control device or an audio mixer, which sets the adjustment state of multi-channel analog signals using a plurality of preset faders, the preset fader signals are The present invention includes a means for multiplexing, a means for sample-holding in synchronization with the multiplexing operation, and a means for performing an operation with a signal from another fader in a path from the multiplexing means to the sample-holding means. Features a multi-channel analog signal calculation circuit. 2 means for integrating the signal in the sampling interval;
2. The multi-channel analog signal calculation circuit according to claim 1, wherein the multi-channel analog signal arithmetic circuit comprises sample and hold means including means for holding the integration result. 3 A plurality of preset faders provided corresponding to each controlled analog quantity are further provided as a group for adjustment states of a plurality of scenes, and the signals of all the preset faders are sequentially multiplexed by a multiplexing means. This multiplex signal is combined with another fader signal specified in accordance with the adjustment state of each scene and a signal that has been subjected to arithmetic processing for each controlled analog quantity to perform adjustment control. A multi-channel analog signal calculation circuit according to claim 1. 4. Pulse width modulation means is provided in the path between the multiplexing means and the sample and hold means, which converts the signal into a pulse having a pulse width proportional to the signal of another fader in synchronization with the two means. A multi-channel analog signal calculation circuit according to claim 1, characterized in that: 5 A storage means is provided for storing the correspondence relationship between each preset fader and the operating state of the multiplexing means, and the data in the storage means is read out in synchronization with the sampling operation of the sample and hold means, and this output data is used to control the multiplexing means. A multi-channel analog signal calculation circuit according to claim 1, characterized in that it operates a multi-channel analog signal calculation circuit. 6. A pulse width modulation means is provided in the path between the multiplex means and the sample hold means, which converts the signal into a pulse having a pulse width proportional to the signal of each preset fader in synchronization with both means. A multi-channel analog signal calculation circuit according to claim 1, characterized in that the multi-channel analog signal calculation circuit comprises: 7 comprises a plurality of separate faders and a second multiplexing means for multiplexing the separate faders, accesses a storage element in synchronization with the first multiplexer, and performs different processing according to the read contents of the storage element. 2. The multi-channel analog signal calculation circuit according to claim 1, wherein the second multiplexing means is controlled so as to output the signal of the fader.