JPH02132983A - Magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To reduce an adjusting part compared with an analog circuit, to attain cost reduction and an inexpensive device by wholly executing the digital processing after the AD conversion for a picture signal obtained by an image sensor such as a CCD. CONSTITUTION:The output of an image sensor 1 is amplified by a first preamplifier 2 and an effective signal component only is extracted. At a direct current reproducing circuit 3, the direct current reproduction is executed with the black signal of the sensor 1 as a reference and added to a video integrated circuit 16 and a variable step AD converter 4. The output of the circuit 16 is added to an iris adjusting circuit 17 and the iris adjustment is executed. At the converter 4, an AD conversion is executed in accordance with the input and one side of the output is outputted through a picture memory 22, etc., as a signal for displaying directly. Other side of the output is added through a preemphasis circuit 5 to a counter type FM modulator 6, impressed through a head driver 7, etc., to magnetic head 8 and recorded to a magnetic tape 26.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention converts an image signal into an analog-to-digital (AD) converter, digitally processes the image signal, records the signal on a magnetic tape with a magnetic head, and records the image signal on the magnetic tape with a magnetic head. The present invention relates to a magnetic recording and reproducing device that reproduces recorded image signals using the magnetic head. (Example) Conventional technology In general, for home color VTRs, three systems have been put into practical use: the β system using the β format as a cassette type, the VHS system using the VHS format, and the VHS system using the VHS format. A dedicated cassette can be used, and VTRs of the same format are compatible and can be used for recording and playback.

As an example, signal processing during recording and playback is described in, for example, published by Japan Broadcasting Publishing Association, edited by Japan Broadcasting Corporation'NHK Home Hiteo Gi IR JP. 6 7 and P. 9 3
~96.

(c) Problems to be Solved by the Invention In the conventional example described above, each component of the luminance signal and color signal is amplified by a linear amplifier, and the processing of color signals etc. is hardly digitized. There are many adjustment points in the analog circuit, and there are many manufacturing steps, which increases the cost of the device.

The magnetic recording and reproducing apparatus of the present invention uses a simple type magnetic cassette, which is called a C-cassette, which eliminates the above-mentioned drawbacks, and provides a novel magnetic recording and reproducing apparatus which is constructed as digitally as possible.

(2) Means for Solving the Problems The present invention converts an image signal obtained by a photoelectric conversion element consisting of an image sensor such as a CCD into an AD converter, digitally records it on a magnetic tape, and converts the image signal recorded on the magnetic tape into an image signal. In order to convert the
A variable step AD conversion circuit is used for the AD conversion, and the image signal obtained by the image sensor is converted into a digital signal and then subjected to signal processing.

(Main) Effect The present invention enables all image signals obtained by an image sensor such as a CCD to be digitally processed after AD conversion.
This has the advantage of reducing the number of adjustment parts compared to analog circuits. (f) To explain the present invention according to the drawings, Fig. 1 is a block diagram of a monochrome type magnetic recording/reproducing device, Fig. 2 is a block diagram of a color type magnetic recording/reproducing device, and Fig. 3 is a block diagram of a magnetic recording/reproducing device of a monochrome type, and Fig. 3 is a block diagram of a magnetic recording/reproducing device of a monochrome type. Step AD circuit, Figure 4 is a characteristic diagram of the same device, Figure 5
The figure is a block diagram showing the configuration of the counter-2 FM modulator used in the same device, FIG. 6 is an explanatory waveform diagram of FIG. Figure (a) is an explanatory waveform diagram of Figure 7, Figure 9 is a circuit diagram of the synchronization detection circuit used in the same device, Figure 10 is an explanatory waveform diagram of Figure 9, and Figure 11 is an explanatory waveform diagram of the same device. A block diagram of the dropout compatible memory used, FIG. 12 is an explanatory diagram of FIG. 11,
FIG. 13 is a block diagram of an interpolator used in the same device, and FIG. 14 is an explanatory diagram of FIG. 13.

In FIG. 1, (1) is an image sensor as a photoelectric conversion element, (2) is a first pre-amplifier, (3) is a DC regeneration circuit, (4) is a variable step AD converter, (5) is a pre-emphasis circuit, (6) is a Kaunk type FM modulator, (7) is a head driver, (8) is a magnetic head, (9
) is the first switching circuit, (10> is the second amplifier, (11) is the limiter amplifier, (12) is the force counter 2F
M demodulator, (13) is a controller that outputs various control signals, (14) is a sensor driver, (15) is an iris adjustment circuit, (16) is an image integration circuit, (17) is an iris adjustment terminal, (18) ) is the control input terminal, (19) is the de-emphasis circuit, (20) is the dropout detection circuit, (21> is the second switching circuit, (22) is the image memory, (23) is the DA converter, (24> is the 44 combiner, (25) is an RF modulator, (26) is a magnetic tape, the image signal is obtained from the image sensor (1), and the image sensor output is amplified by the first preamplifier (2) and included therein. Only the effective signal components that are present are extracted.

In the next stage DC regeneration circuit (3), the image sensor (1)
DC reproduction is performed using the OPB (Optical Black) signal as a reference, and the DC reproduced video signal is applied to a video integration circuit (16) and a variable step AD converter (4). In the former case, a value corresponding to the average value, peak value or intermediate value is obtained by setting a desired time constant, and as a result, the video integrated output signal is applied to the sensor driver via the iris adjustment circuit (15) and the charge is The iris adjustment is performed by reverse transfer, etc.

In this case, when using a mechanical iris adjustment method, the output of the iris adjustment circuit drives the driver of the mechanism.

On the other hand, the latter is applied to a variable step AD converter (4). This is a circuit that performs AD conversion by changing the steps according to the input. This function is based on automatic gain control (AGC), and even if the average value of the input signal fluctuates, it is possible to obtain converted data with a substantially constant average value. One of the outputs of the variable step AD converter (4) is directly applied to the image memory <22> through the second switching circuit (21) as a signal for display, and is sent to the image memory (22).
After being stored in the DA converter (23) and mixer (2
4), the composite video signal is output. On the other hand, the data corresponding to the high frequency part of the video is emphasized through the pre-emphasis circuit (5), and the counter type FM
After being applied to the modulator (6), the digital signal is FM modulated, applied to the magnetic head (8) via the head driver (7) and the first switching circuit (9), and recorded on the magnetic tape (26). ．When playing, the magnetic head (26)
The detected FM signal is applied to the second preamplifier (10) through the first switching circuit (9). The second briamb (1o) has a peak in the high range, and the recording/reproducing characteristics are relaxed so that an FM signal having a flatter frequency characteristic is output.

Since the FM signal at the output end of the second amplifier (10) still fluctuates in amplitude, a complete FM wave is obtained by the limiter amplifier (11). Here, the output of the limiter amplifier (11) is the counter type F
The FM signal is input to the M demodulator (12), and digital data is obtained from the FM signal. If a sign of dropout (Do) appears, such as an extremely small carrier in the limiter amplifier (11), the dropout detection circuit (2o) detects it and outputs it from the image memory (22). In other words, dropout compensation (DOC) is performed. The output data of the counter type FM demodulator (12) is processed by the de-emphasis circuit (
19), is stored in the image memory (22) via the second switching circuit (21), read out at a predetermined display rate, converted from DA to analog data by the DA converter (23), and then sent to the mixer. (24), the synchronization signal (S
yc) to generate a composite video signal, and by applying it to each video input terminal of a CRT monitor or television receiver, images can be reproduced. The composite video signal is sent to an RF modulator (2
If the signal is RF converted by 5) and applied to the antenna terminal of the television receiver, the image will be reproduced in the same manner as described above.

Next, to explain Figure 2, in the drawing (27)
is a color image sensor, (28) is a color process amplifier, (29) is a DC regeneration circuit, (30) is a first variable step AD converter, and (31) is a second variable step A.
D converter, (32) is Y (luminance signal component) pre-emphasis, (33) is the first IFM modulator, (34) is the first
Head driver, (35) is the first switching circuit, (
36) is the first magnetic head, ``37'' is the second switching circuit, (38) is the R-Y (B-Y) pre-emphasis circuit, ``39'' is the counter type second FM modulator, and (40) is the second FM modulator. Head driver, (41) is the third switching circuit, (42) is the second magnetic head, (43) is the first amplifier, (44) is the first limiter amplifier, <<45>> is the counter type IFM demodulator, <<46> is the Y de-emphasis circuit, (47) is the dropout detection circuit, (48) is the third switching circuit, (49) is the Y memory, (50)
is an interpolator, (51) is a color processor that processes color signals, (52), (53), and (54) are first and second, respectively.
and a third DA converter, (55) a second preamplifier,
(56) is the second limiter amplifier, (57) is the counter type second FM demodulator, R-Y (B-Y) de-emphasis circuit, (58) is the fifth switching circuit, <<59>> is R-
Memory for Y and B-Y, (60) shows the R-Y (B-Y) de-emphasis circuit. The image signal obtained by the image sensor (27) includes a luminance signal component (Y) and color difference signal components (RY and B-Y), and is amplified to a predetermined amplitude by a color processor (28).

The Y signal is sent to the A/D converter (3
The digital data AD-converted at 0) is applied to the counter-type IFM modulator (33) via the Y-brienfγ cis circuit (32), and the modulated output is sent to the first head driver (33).
4) and the first switching circuit (35) to the first magnetic head (36) and are recorded on the magnetic tape (26). On the other hand, regarding reproduction of the Y signal, the Y component extracted by the first magnetic head (36) is applied to the first preamplifier (43) and the first limiter amplifier (44) via the first switching circuit (35). After being amplified to a predetermined amplitude, a demodulated signal is obtained by a counter-type IFM demodulator (45).The demodulated signal is sent to a Y de-emphasis circuit (46), a fourth switching circuit (37), and a Y memory (49). ) and then performs DA conversion at the IDA converter (52) to obtain a Y signal.

Next, as for the color signal, the output (color difference signals R-Y, B-Y) of the DC reproduction circuit (29) is applied to the second variable step AD converter (30), and the AD-converted digital data is sent to the second switching circuit ( 37) and (RY) (
B-Y) is applied to the counter-type second FM modulator (39) via the pre-emphasis circuit (38), and the modulated output is sent to the second head driver (40) and the third switching circuit (
41) to the second magnetic head (42) and is recorded on the magnetic tape (26). At this time, R-Y and B-
Y is alternately thinned out line by line in the second variable step A/D converter, connected on the time axis, and treated as one channel in subsequent modulation and demodulation.

The digital data recorded on the tape (26) is
The first magnetic head (36) and the second? a-head (42)
Y and R-Y are read out as a luminance signal and a color difference signal, respectively, and are sent to a first pre-amplifier (43), via a first switching circuit (35) and a third switching circuit (41), respectively.
1st limiter amplifier (44) and 2nd limiter amplifier (55)
, a second limiter amplifier (56), a counter type IFM demodulator (45) and a second demodulator (57) to generate a luminance signal component (Y) and a color difference signal component (R-Y and B-Y).
are read out, and the demodulated outputs are sent to de-emphasis circuits (4
6) (60), Y memory (49) or R-Y, B-Y memory (5) through the switching circuits (37) and (58).
9), and each memory output is connected to a DA converter (52).
DA conversion is performed in (53) and (54), and each component Y, RY
and B-Y analog outputs are obtained, and a composite color video signal is output by a color processor (51). At this time, the output of the limiter amplifier (44) is applied to the dropout detection circuit (47), and the Y memory (49) and the R-Y, B-Y memory (59) compensate for the dropout detected. conduct. Also, the interpolator (50) uses the R-Y and B-Y memories (which are thinned out line by line).
59》, and an example of its configuration is the 13th
It is shown in the figure. Next, the structure of each component will be explained according to the drawings from FIG. 3 onwards.

Figure 3 is an example of a variable step type AD converter. First, the analog signal extracted by the image sensor is sent to the terminal (
61), and is sampled and held by the sample-and-hold circuit (62), and its output is applied to one comparison terminal of the comparator (63). At this time, the resistor (65) and capacitor ( 66》 is a time constant consisting of each value Ri, Ci, and its center value is applied to the amplifier (67).
) is connected to the switch circuit 68) and the resistor network (69) (
It is used as a reference voltage for an AD conversion circuit consisting of a resistance value R, ~Ri) and a capacitor (70) (capacitance value Cp).

The resistance (R,
~Ri) are connected to a reference voltage.

Therefore, the output point P of the AD conversion circuit (comparator (63)
The voltage at the other input terminal (the other input terminal) fluctuates depending on the magnitude of the average value of the analog input. In addition, the voltage at point P is the highest value of the digital data, that is, the resistance value (mainly R.) n is set so that when all the resistances are connected to the reference voltage (Vr) by the switch circuit (68), α×1. is set. Here, α is the ratio between the dynamic range and the average value, and is determined depending on the application. The controller (13) performs operations necessary for successive approximation type AD conversion, such as timing of the sample/hold circuit (62), switch drive, and latch.

According to the above configuration, the dynamic range of AD conversion changes in response to the average value of human power, so the digital data output from the terminal (71) is automatically controlled by automatic gain control (AGC).
It works as if it were working. FIG. 4 shows how the dynamic range changes depending on the average value of the input. Fourth
In the figure, MSB indicates the pattern when αx2.5;
The amplification factor of 67) is nRr/Rt"n. In the above configuration, when the die capacitor (72) and the resistor ←→ are added, the peak value of the analog input applied to the terminal (61) is reflected in the AGC. It is allowed. Next, Figure 5 shows the counter type F.
A circuit diagram of an embodiment of the M demodulator is shown, and the input terminal (73)
The digital data applied to (73) is divided into two paths (two paths), and is sent to the first and second digital comparators (73), respectively.
74)<75). Here, when the least digit of the multi-bit data is shifted by 1 bit, the value becomes the original H.
It is well known that the value of

In the digital comparator (74), the LSB of the input data is deleted and the second LSB is sent to the counter (76).
The input data and counter (
76》 contents are compared. In other words, this output is a counter (
76) is half of the input data with an error of one clock. In the digital comparator (74), the input data is compared with the contents of the counter (76) and its output indicates whether the contents of the counter (76) are equal to or exceed the input data. The latch circuit (77) is set by the output of the first digital comparator (74) and reset by the output of the second digital comparator (75).

As a result, the output rises at half of the input data (A/2) and falls at all of it (A), and its period is determined by the clock period and the input data, and this situation is shown in Figure 6.
(a) is the clock signal (CLK), and (b) is the output signal waveform.

Next, Figure 7 shows the main configuration of a counter type FM demodulator,
The FM input is converted by a flip-flop (F/F) (78) so that Q and Q having a frequency of κ and having a phase difference of 180° are outputted. AND gate (79) (8
0), the clock signal (CLK) is output from the output Q.0). Q and counted by a first counter (81) and a second counter (82). That is, the first counter (81) and the second counter (82) alternately control each period of the FM input, and the results are sequentially switched by the switching circuit (83) and output as digital data. This situation is shown in Figure 8, where A
The first counter (81) counts with the output of the ND gate (79), and the second counter (82) counts with the output of the AND gate (80).
The count of the counter (81) is during a period P, the waveform of the period P shows the output from the second counter (82), and the waveform of the period Q shows the output from the first counter (81).

A synchronization signal is generated by the synchronization detection circuit (84) in FIG. 7, and horizontal and vertical synchronization is achieved.

Figure vJ9 shows the configuration of the synchronization detection circuit, and the contents (b) of the up/down counter (85) are compared with the video data (a) by a digital comparator (86).

At this time, if a<b, the high frequency H clock decrements the contents of the up/down counter (89) through the AND gate (87) and OR gates (88) and (89).

Next, when a=b, the AND game 1-(90) cuts off the clock signal (CLK) of the up/down counter (85), so its contents do not change.

On the other hand, if a>b, the low frequency L clock increases or increments the contents of the up/down counter (85) through the AND gate (90), the OR gate (88) and the gate (89).

Therefore, the digital comparator (
86) and the logical sum (OR) of a=b and a<b, it is possible to detect the existence of a data portion that is protruding toward the smaller side in the video data. The situation is shown in Fig. 10, where the contents of the up/down counter (85) are rapidly lowered at the downward protruding part as shown in (a), and stopped at the point where it matches the video data, and the video data is When it becomes larger, it gradually rises to prepare for detection of the next downward protrusion.

Next, the configuration of the dropout (Do) compatible memory is
The first memory (92) and the second memory (92) are shown in the figure.
A 1-line shift register 95) is provided separately from the memory (94) containing 93), and in the part where a dropout occurs, the output is output from the register (95>) and the same part as that of the previous scanning line is provided. Replaced by address counter (96) for writing and reading.
) (97) designate the memory address being written and read, respectively.

Further, the role switching signal is normally switched by an internal vertical synchronization signal of the magnetic recording/reproducing device, and switches the reading (read) and writing (writing) roles of the first memory (92) and the second memory (93). The switching circuit <98> includes data, dropout detection output, and output of the 1-line shift register (95), and the switching circuit <98>
The output of the memory (94) is applied to the first memory (94).
2) and the second memory (93) are respectively provided with an address counter for filling (96) and an address counter for reading (97).
output is added to perform dropout compensation. Here, the write address counter (96) receives the write clock (CLK) and synchronization signal (Syc), and the read address counter (97) receives the read clock (CLK).
LK) and a synchronization signal (Syc) are added, the counter output is added to the memory (94), and the role switching signal causes an output to be obtained from the memory (94).

Next, FIG. 12 shows how the previous data is replaced with the dropout part by the shift register (98), and the dropout part (3.
4), the contents of the shift register (98) are 2rl, 11, Ql, m.
−． ...5, -. ,4,-. ,3. -1 is shifted sequentially.

Figure 13 shows the configuration of the interpolator, which is used to read out the memory, and the data read out after being addressed by the segment and line counters is decoded by the decoder (1aiJ) as the last two digits of the line counter (99). Four line memories (101) (102) (103) (10) whose writing/reading (W/R) is controlled by signals
4) are sequentially stored or read out. The line memory (101) (102) (103) (104)
The outputs of the first to sixth gates (10
5) (106) < 107) < 108) (109) (11
0), the first adder (111) and the second adder circuit (112)
) through which the R-Y and B-Y outputs are obtained, respectively.

At this time, RY remains unchanged for odd-numbered scanning lines, but for even-numbered scanning lines, it becomes the average value before and after it. This is the gate (105>(106)(10
7), a first adder (111), a first divider (113)
)(κ). B-Y also has a gate (1
08) (109) (110) and second adder (112)
It is obtained by the configuration of the second divider duct 114) (κ).

Effects of the Invention According to the magnetic recording/reproducing device of the present invention, moving images can be recorded by digital signal processing as a simple VTR, and the main parts can be integrated into ICs, and various adjustments in conventional analog signal processing can be made. If the present invention is used in a video table recorder with a built-in camera called a camcorder, which does not require high resolution, the cost can be reduced by eliminating the circuitry.
It becomes possible to construct an inexpensive device.

[Brief explanation of drawings]

The drawings all show explanatory diagrams of the magnetic recording and reproducing apparatus of the present invention, and FIG. 1 is a block diagram of a monochrome type of the same device, FIG. 2 is a block diagram of a color type of the same device, and FIG. 3 is a block diagram of the same device. The variable step AD circuit used, Fig. 4 is a characteristic diagram of the same device, Fig. 5 is a configuration diagram of a counter type FM modulator used in the same device, Fig. 6 is an explanatory waveform diagram of Fig. 5, and Fig. 7 is the same. A configuration diagram of a counter-type FM demodulator used in the device, FIG. 8 is an explanatory waveform diagram of FIG. 7, FIG. 9 is a circuit diagram of a synchronization detection circuit used in the device, and FIG. 10 is an explanatory waveform diagram of FIG. 9. Figure, 11th
The figure is a block diagram of a dropout compatible memory used in the same device, FIG. 12 is an explanatory diagram of FIG. 11, FIG. 13 is a block diagram of an interpolator used in the same device, and FIG. 14 is an explanatory diagram of FIG. 13. shows. (1)(27)...Image sensor, (4)(30
)(31)...Variable step AD converter, (6
)(33)(39)...Counter type FM modulator, (
8)(36)(42)...Magnetic head, (12)(
45) (57) Counter type FM demodulator, (13>
...Controller, (22) (49) (59)・
...Image memo, (23) (52) (53) (54
)...DA converter, (25)...RF modulator, (51)...Color Brosse 7-na.

Claims (2)

[Claims] (1) An image sensor that performs photoelectric conversion, a variable step AD converter that AD converts the output of the image sensor, and a counter-type FM modulator that FM modulates digital data to which the AD converter output is added; The F
A magnetic head to which an M modulator output is applied and records on a magnetic tape or reproduces data recorded on the magnetic tape, and a counter-type FM demodulates the signal recorded on the magnetic tape by the magnetic head. a demodulator and the FM
1. A magnetic recording and reproducing apparatus comprising a controller to which demodulated output of a demodulator and various operation inputs are applied, and is capable of recording and reproducing image signals on the magnetic tape. (2) An image sensor that performs photoelectric conversion, a first color process amplifier that amplifies the output of the image sensor, and a variable step type first color process amplifier that is connected to the output side of the color process amplifier via a DC regeneration circuit. 1st and 2nd AD
converter, and a counter-type first FM connected to the output side of the first AD converter and FM modulating the luminance component.
a modulator, a counter-type second FM modulator connected to the output side of the second AD converter for FM modulating the color difference signal, and recording the Y component and the color difference signal respectively on a magnetic tape or recording the color difference signal on the magnetic tape. first and second magnetic heads for reproducing the Y component and color difference signals recorded in the first and second magnetic heads;
counter-type first and second FM demodulators each connected to the magnetic head, the first and second AD converters, the first and second modulators, the first and second AD converters, the first and second modulators, and the CPU connected to first and second demodulators
A magnetic recording and reproducing apparatus comprising: a magnetic recording and reproducing apparatus capable of recording and reproducing color image signals on the magnetic tape.