JPH02132937A - Receiving device for spread spectrum communication - Google Patents

Abstract

PURPOSE:To generate a clock synchronized with a received signal, and simultaneously, to decide the difference of synchronism between the received signal and a pseudo noise code without necessitating any complicated constitution by providing a clock generating means and a convolver means, etc. CONSTITUTION:A clock regeneration circuit 2 supplies the clock of prescribed frequency, i.e., the free-running frequency of a voltage controlled oscillator VCO to a code generator 7 and a timing extraction circuit 1, etc. The generator 7 generates a reference pseudo noise code 7-b for demodulation in synchronism with the clock, and the output signal of a local oscillator 8 is modulated, and correlation with the received signal 10 is taken by a SAW convolver 9, and convolution output 9-a is outputted. Next, peak output 5-a is outputted to the timing extraction circuit, a synchronism detection circuit 4 and the circuit 2 through an envelope detection circuit 6 and a peak detection circuit 5, and the respective circuits are operated by the leading edge of the output 5-a. Thus, the clock synchronized with the signal 10 can be generated, and the synchronism difference between the signal 10 and the signal 7-b can be decided without necessitating any complicated constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a receiving device for spectrum spread communications that demodulates a spread spectrum signal using a despreading code.

[Prior art]

Conventionally, a synchronization detection section in a spread spectrum communication receiver is implemented using a delay locked loop (hereinafter referred to as DLL) circuit. In the synchronization establishment method using a DLL, the spreading code generated by the spreading code generator is divided into arbitrary sizes (for example, the reference phase and the one with 1/2 phase advanced, 1
/2 phase delayed), and the phase-shifted spreading codes are input to each of the three correlators of the DLL, increasing the correlation detection period by three times.

[Problem that the invention is trying to solve] However,
In the conventional example described above, a circuit for shifting the phase of the spreading code is required, and three correlators are also required.

In addition, since a bandpass filter and an envelope detector that constitute the DLL are required separately, the circuit becomes complicated.
There were problems such as the adjustment becoming complicated.

[Means for solving problems]

The present invention includes a clock generating means for generating a clock, a code generating means for generating a reference code based on the clock, and a frequency dividing means for dividing the frequency of the clock according to the code length of the reference code. convolver means for correlating the received signal with the reference code; peak detection means for detecting the peak of the output of the convolver means; and peak detection means for determining the timing at which the clock generation means generates the clock with the frequency division means and the peak detection means. By providing a control means that controls according to the output of the means, a complicated configuration is not required.
This makes it possible to generate a clock that is synchronized with the received signal.

The present invention also provides a correlation means for correlating a periodically generated pseudo-noise code with a received signal, a peak detection means for detecting a peak of the correlation means, and a start and peak detection means for the pseudo-noise code. By providing a time difference measuring means for measuring the time difference between the outputs of the signals, it is possible to determine the synchronization difference between the received signal and the pseudo noise code.

〔Example〕

FIG. 1 shows a block diagram showing the configuration of an embodiment of the present invention. Reference numeral 1 designates a timing extraction circuit, and 2 designates a clock regeneration circuit, which is comprised of a phase comparator and a VCO (voltage controlled oscillator). 3 is a frequency dividing circuit, 4 is a synchronization detection circuit, 5 is a peak detection circuit, 6 is an envelope detector, and 7 is a code generator that generates a reference spreading code, and one period is 2.
A reference code which is a pseudo noise code of 55 is generated. 8
is a local oscillator, 9 is a surface acoustic wave convolver device for taking correlation (hereinafter referred to as SAW convolver), and IO is a received spread spectrum signal from an antenna that receives wireless signals (hereinafter referred to as received signal). ).

FIG. 2 shows an internal block diagram of the timing extraction circuit 1, which has the following configuration. 1-1 is a delay detection circuit for detecting the delay m between the code start 7-a of the reference code and the peak output 5-a, and 1-2 is a U/D (up, ·' 1-3 converter detects the amount of delay, and 1-4 creates synchronization timing.

FIG. 3 shows an internal block diaphragm of the synchronization detection circuit 4, and 4-1 is an F for timing detection of the peak output 5-a.
/F (flip flop), and 4-2 is an F/F for timing detection of the code start 7-a. 4-3 is an exclusive OR gate, 4-4 is an F/F for checking deviation, and 4-5 is a check circuit for checking deviation. 5 is a time chart showing the operation of each circuit.

The actual operation will be explained below using the time charts shown in FIGS. 5 to 8.

First, the clock recovery circuit 2 receives the free running frequency of vCO, 1 6 . A 32 MHz clock is supplied to the code generator 7, the timing extraction circuit 1, and the synchronization detection circuit 4. In synchronization with this 16.32 MHz clock, the reference code generator 7 generates a reference pseudo-noise code (hereinafter referred to as a despreading code) 7-b for demodulation. This generated despreading code 7-b is supplied to the mixer 11 and the demodulation circuit l2. The 200 MHz carrier signal output from the local oscillator 8 is modulated by this despreading code 7-b and supplied to the despreading code input of the SAW convolver 9.

Further, the received signal 10 is supplied to the received signal input of the SAW convolver 9. The first received signal lO is a preamble (pre-procedure) for initial synchronization.
It becomes. These two input signals are correlated by the SAW convolver 9 and output as a convolution output 9.
-a is output. The convolution output 9-a obtained here is full-wave rectified by the envelope detection circuit 6, and then its envelope is taken by a low-pass filter. This envelope-detected signal 6-a is input to a peak detection circuit 5, and its peak is detected.

In the peak output 5-a at this time, the rising edge is the peak position, so in order to minimize the influence of noise etc., the peak output 5-a has many High (high) sections. (largely) is taken as a pulse. The pulsed peak output 5-a is
It is input to the timing extraction circuit 1, the clock regeneration circuit 2, and the synchronization detection circuit 4, and each circuit receives this peak output 5-a.
It is activated by the rising edge of . The operations of the timing extraction circuit 11, the clock recovery circuit 2, and the synchronization detection circuit 4, which receive the peak output 5-a, will be explained below.

First, as shown in FIG. 4, the clock regeneration circuit 2 divides the 16.32 MHz clock 2-a transmitted from the VCO 2-1 into l/255 by the frequency dividing circuit 3.
4KHz clock and peak output 5-a
A converter 2-2 compares the phases, converts the error into a voltage, and supplies it to the VCO 2-1 to reproduce a clock synchronized with the received signal. When the phases of the two signals match, the clock recovery circuit 2 transfers the timing extraction circuit 1 to the timing extraction circuit 1.
A lock signal 2-a is outputted to the lock signal 2-a. This signal causes
The timing extraction circuit 1 becomes enabled and starts measuring the deviation width between the despreading code 7-b and the received signal 10.

In other words, the clock recovery circuit 2 uses the received PN code and the VCO
The clock signal 2-1 is synchronized with the clock signal 2-1, and a clock signal 2-b synchronized with the received PN code is output.

The timing extraction circuit l receives a clock 2-b of l6, 32 MHz regenerated by the clock regeneration circuit 2 as shown in the internal block diagram of FIG.
is synchronized with. First, when the enable state is achieved by the lock signal 2-a, the code start signal is sent to the delay detection circuit 1-1.
Wait for signal 7-a to be input (during this time, peak output 5
Even if -a is input, it is masked). Then, when the code start signal 7-a is input (Fig. 5, Fig. 7,
In (a) of FIG. 8, the delay detection circuit 1-1 selects up-counting of the U/D counter l-2, and causes the U/D counter l-2 to count up.

Then, up-counting is continued until the next peak output 5-a is input, and the amount of delay is measured. Next, when the peak output 5-a is input ((b) in Figs. 5, 7, and 8),
)), the U/D counter 1-2 is switched to down count and the delay correction time is measured.

The output of this U/D counter is sent to the next stage comparator 1-
When the delay amount input to 3 and output at the time of counting match with the subtracted value ((C) in Figs. 5, 7, and 8), a timing output signal is output to the synchronous timing generation circuit 1-4. (The converter 1-3 is the U/D counter 1-3.
2 is disabled when counting up, and this comparison is only performed when counting down). The synchronous timing generation circuit 1-4 receiving the timing output signal generates 16. The timing pulse 1-a is outputted to the spreading code generator 7 in synchronization with the 32 MHz clock, and the synchronization detection signal 1 is sent to the synchronization detection circuit 4.
-b is output to disable the timing extraction circuit 1 itself. The spreading code generator 7 receiving the timing pulse 1-a outputs the despreading code 7-b from the beginning as shown in FIG.
d).

Further, the synchronization detection circuit 4 is enabled by receiving the synchronization detection code 1-b, and receives the received signal 10 and the despreading code 7.
-b synchronization detection and monitoring. In the synchronization detection circuit 4,
Firstly, if the peak output 5-a of the received signal 10 is
Alternatively, when the signal is input to 4-2, the output of the F/F changes. Then, the output of exclusive OR of 4-3 becomes Lo
w Changes from (low) to High (high) and enables the shift checking F/F 4-4. At this time, 1 6 . is supplied from the clock recovery circuit 2. 3 2 MH
When the rising edge of the clock 2-b of z is input, H i g h is input to the check circuit 4-5.

The check circuit 4-5 receiving the signal checks each F/F 4-1.
・Output a CLR (clear) signal to 4-2.

Then, as above, again, the F/F4-4 for misalignment check.
until High is input.

If High is input again here, it is recognized that synchronization has been lost, and an out-of-synchronization signal 4-a is output to the timing extraction circuit 1, thereby ending the synchronization detection operation.

Also, either timing detection F/F 4-1 or 4-2 is input, deviation check F/F 4-4 is enabled, and the other one is input before the rising edge of the 16.32 MHZ clock is input. When the signal is input, the output of the check F/F 4-4 does not change. This means that the timing difference between the peak output 5-a and the code start 7-a is within one clock of the 16.32 MHz clock 2-b.

The timing extraction circuit 1 that receives the out-of-synchronization signal 4-a starts the same operation as described above after a certain period of time.
Extract the timing again.

The operation of the synchronization detection circuit 4 will be explained using the time chart of FIG.

In FIGS. 6(a) and 6(b), the received signal 10 and the despreading code 7-b are synchronized. That is, received signal 1
The deviation between the peak output 5-a of 0 and the code start 7-a of the despreading code 7-b is within one clock of the clock 2-b. Therefore, exclusive OR gate 4
Since the period in which -d is High is within one clock of clock 2-b, F/F 4-4 for discrepancy check
The deviation signal 4-e, which is the output of , remains low and does not change.

However, when the clock 2-b enters between the code start 7-a (FIG. 6(C)) and the peak output (FIG. 6(d)), the deviation check F/F 4-4 detects the deviation signal 4-4. Output e. That is, the shift checking F/F 4-4 outputs a shift signal 4-e if the exclusive OR gate 4-d is High when the clock 2-b is input. Check circuit 4-5 has error signal 4-e High
When it becomes gh, the CLR signal is output and the flip-flop F/Fs 4-1 and 4-2 are cleared (FIG. 6(e)).

Continuing here, when the deviation signal 4-e becomes High, that is, after the code start 7-a is input (FIG. 6(f)) and before the peak output 5-a is input, the clock 2- When b is input (FIG. 6(g)), the check circuits 4-5 output an out-of-synchronization signal 4-a.

When the timing extraction circuit 1 receives the out-of-synchronization signal 4-a, it performs the synchronization detection operation again.

Next, the operation of the circuit of this embodiment whose configuration is shown in FIG. 1 will be explained using the time chart of FIG. 7.

In the initial state, the clock regeneration circuit 2 converts the clock 2-b into 1/2 to the peak output signal of the convolution output.
Combine the signals divided by 55. Clock 2-b is 1/
The reason why the frequency is divided by 255 is that the code length of the spreading code is 256 bits, so the convolution output 9-
This is because a has a peak every 256 bits.

Then, after the code start signal generated by the code generator 7 of the reference code is manually inputted, the timing extraction circuit 1 extracts the peak output 5 of the peak detection circuit 5 of the convolution output.
Count clocks 2-b until -a is input.

After the peak output 5-a is input, when the clock 2-b is counted by the same number as the count value, the timing extraction circuit 1 outputs the timing pulse 1-a to the reference code generator 7. When the code generator 7 receives the timing pulse 1-a, it outputs the reference code from the beginning (FIG. 4(d)).

That is, when the code generator 7 starts outputting the reference code (FIG. 8(a)), the code generator 7 outputs the code start signal 7-a.
is output to the timing extraction circuit 1. Then, the peak detection circuit 5 generates a peak output signal 5 of the convolution output.
-a is generated when the received signal and the reference signal match, as shown in FIG. 8(b). As is clear from FIG. 8, when the same time as the time difference between the input of the code start signal 7-a and the input of the peak output signal 5-a has elapsed since the input of the peak output signal 5-a, the spreading code of the received signal is coincides with the convolution integral region of the convolver 9. Therefore, at this time, the timing extraction circuit 1 outputs a code start signal 7-a so that the code generator 7 starts generating the reference code 7-b (FIG. 4(C)).

After the received signal 10 and the reference code 7-b are synchronized in this manner, the synchronization detection circuit 4 detects out-of-synchronization. Note that the code start signal 7-a is also supplied to the code generator 12 for demodulating the information signal from the received signal. The code generator l2 generates a despreading code common to the spreading code in the received signal, and starts outputting the despreading code when receiving the code start signal 7-a.

The synchronization detection circuit 4 converts the time difference between the peak output signal 5-a of the convolution output output from the peak detection circuit 5 and the code start signal 7-a of the code generator 7 into a clock 2-b.
Measure by comparing with. When the synchronization detection circuit 4 determines that a deviation has occurred between the peak output 5-a and the code start signal 7-a, it outputs the out-of-synchronization signal 4-a to the timing extraction circuit l. A despreading code 7-b synchronized with the received signal is output.

Here, the synchronization detection circuit 4 can determine that synchronization has been lost if a deviation occurs even once between the peak output 5-a and the code start signal 7-a, but if the deviation occurs twice in a row, , it can also be determined that synchronization has been lost. In this way, the influence of noise can be reduced.

[Other Examples]

Other embodiments of the present invention are shown in FIGS. 9 to 11.

Here, since the configuration is almost the same as that of the previous embodiment, the same symbols as in the previous embodiment are attached to the same parts. 13 is a timing extraction circuit, and 11 is a clock regeneration circuit, which is composed of a phase converter and a VCO (voltage controlled oscillator). 3 is a frequency dividing circuit, 4 is a synchronization detection circuit, 5 is a peak detection circuit, 6 is an envelope detector, and 7 is a spreading code generator, which generates a reference PN code with one period of 255. 8 is a local oscillator, 9 is a SAW convolver for taking correlation, 10 is a received signal, 12 is 3
2. This is a frequency dividing circuit that creates a reference clock for generating a despreading code 7-b from a 64 MHz clock by the spreading code generator 7.

FIG. 10 is an internal block diagram of the timing extraction circuit 13, which has the following configuration.

13-1 is a delay detection circuit for detecting the delay 1 between the despreading code 7-b and the peak output 5-a, and 13-2 is a U/D (up/down) counter for measuring the amount of delay. , 13-3 The amount of delay is detected by the comparator, and 1
3-4 creates synchronization timing.

FIG. 11 is an internal programming diagram of the synchronization detection circuit 4, where 4-1 is an F/F (flip-flop) for timing detection of the peak output 5-a, and 4-2 is a code start 7-F. This is an F/F for timing detection of a. 4-
3 is an exclusive OR gate, 4-4 is an F/F for checking deviations, and 4-5 is a check circuit for checking deviations. The actual operation will be explained below.

First, the clock recovery circuit 11 generates the free running frequency of vCO, 3 2 . A 64 MHz clock is supplied to the frequency dividing circuit 12, the timing extraction circuit 13, and the synchronization detection circuit 4. 32.64MH output by frequency divider circuit 12
In synchronization with the clock of z, the spreading code generator 7 generates a reference PN code (hereinafter referred to as a despreading code) 7-b for demodulation. This generated despreading code 7-b is supplied to mixer l1 and demodulation circuit l2. The 200 MHz carrier signal output from the local oscillator 8 is modulated by this despreading code 7-b and
It is supplied to the despreading code input of the AW convolver 9.

Further, the received signal 10 is supplied to the received signal input of the SAW convolver 9. The first received signal 10 is a preamble (pre-procedure) for initial synchronization.
It becomes. These two input signals are correlated by the SAW convolver 9 and output as a convolution output 9.
-a is output. The convolution output 9-a obtained here is full-wave rectified by the envelope detection circuit 6, and then its envelope is removed by a low-pass filter. This envelope-detected signal 6-a is input to a peak detection circuit 5, and its peak is detected.

In the peak output 5-a at this time, the rising edge is the peak position, so in order to minimize the influence of noise etc., the peak output 5-a has many High (high) sections (duty It is a thick pulse. The pulsed peak output 5-a is
It is input to the timing extraction circuit 13, the clock regeneration circuit 11, and the synchronization detection circuit 4, and each circuit receives this peak output 5.
It operates on the rising edge of -a. The operations of the timing extraction circuit 13, clock recovery circuit 1l, and synchronization detection circuit 4 that receive the peak output 5-a will be described below.

First, as shown in FIG. 12, the clock regeneration circuit 11 generates 3 2 . 6
The frequency dividing circuit 12 divides the 4 MHz clock 11-a into 1/2, and the frequency dividing circuit 3 divides the clock into 1/2.
The phase of the 64KHz clock divided by 255 and the peak output 5-a is compared using a phase comparator, and the error is converted into voltage and supplied to VCO II-1, which reproduces the clock in synchronization with the received signal. conduct. When the phases of the two signals match, the clock recovery circuit 1l outputs a lock signal 11-a to the timing extraction circuit 13. This signal causes the timing extraction circuit 13 to be enabled, and starts measuring the deviation width between the despreading code 7-b and the received signal IO.

The timing extraction circuit 13 consists of the internal blocks shown in FIG.
3 2 . recovered by the clock recovery circuit 11 as shown in the diagram. It is synchronized to a 64 MHz clock. First, when the enable state is reached, the delay detection circuit 13-1 waits for the code start signal 7-a to be input (even if the peak output 5-a is input during this period, it is masked). Then, when the code start signal 7-a is input, the delay detection circuit l3-1 selects up-counting of the U/D counter 13-2, and the U/D counter 1
Count up 3-2. Then, up-counting is continued until the next peak output 5-a is input, and the amount of delay is measured. Next, when the peak output 5-a is input, U
/D counter l3-2 is switched to down count and the delay correction time is measured.

The output of this U/D counter is the converter l3 of the next stage.
-3, and when the delay amount output at the time of counting matches the subtracted value, it outputs a timing output signal to the synchronous timing generation circuit l3-4 (the converter 13-3 outputs a timing output signal to the U/D counter 13-2 when the U/D counter 13-2 counts up. (This comparison is only performed during down-counting.)

This synchronous timing generation circuit which received the timing output signal is 32. The timing pulse 13-a is sent to the spreading code generator 7 in synchronization with the 64 MHz clock.
At the same time, a synchronization detection signal 13 is output to the synchronization detection circuit 4.
-b is output to disable the timing extraction circuit 13 itself. The spreading code generator 7 that receives the timing pulse 13-a outputs the despreading code 7-b from the beginning.

Further, the synchronization detection circuit 4 is enabled by receiving the synchronization detection signal 13-b, and detects and monitors synchronization between the received signal IO and the despreading code 7-b. In the synchronization detection circuit 4, first, when either the received signal IO or the despreading code 7-b is input to the F/F 4-1, if << is input to 4-2, the F/F
output changes. Then 4-3 exclusive O
The output of R changes from Low to High, enabling the deviation checking F/F 4-4.

At this time, 3 2 is supplied from the clock regeneration circuit 11.
．． When the 64 MHz clock rises, a high signal is input to the check circuit 4-5.

The check circuit 4-5 that received the signal checks each F-F4-1.
-4-2 1: Output CLR signal to. Then, in the same manner as above, the high
Wait until h is input.

If High is input again here, it is recognized that synchronization has been lost, and an out-of-synchronization signal 4-a is output to the timing extraction circuit 13, thereby ending the synchronization detection operation. Further, either timing detection F/F 4-1 or 4-2 is input, deviation check F/F 4-4 is enabled, and 3 2 . If one of the signals is input before the rising edge of the 64 MHz clock is input, the output of the check F/F will not change. This means that the timing difference between the peak output 5-a and the code start 7-a is 3 2 . This means that it is within one clock of the 64 MHz clock.

Timing extraction circuit 13 receiving out-of-synchronization signal 4-a
After a certain period of time, the process starts the same operation as described above and extracts the timing again.

In this way, in this embodiment, the clock 11-b is 3
2. Since a 64 MHz clock is used, more accurate synchronization can be achieved.

In addition, the free running frequency of VCOII-1 is 1 6 . which is the frequency of the spreading code. Using a free-running frequency that is an integer multiple of 32 MHz, the clock generated by vCO is divided into 16 MHz by frequency divider l2. By converting to 32 MHz, it is possible to achieve even more accurate synchronization.

It is also possible to use a microprocessor (one-chip microprocessor, etc.) for the timing extraction circuit of the above embodiment.

In this way, in this embodiment, synchronization can be detected and maintained without using a DLL. Therefore, analog circuits such as bandpass filters and phase shift circuits for configuring the DLL can be made smaller. Therefore, component costs can be eliminated, downsizing can be achieved, and the circuit can be easily adjusted.

〔Effect of the invention〕

As described above, according to the present invention, synchronization with a received signal can be achieved at high speed.

Further, it is possible to accurately detect a deviation in synchronization with a received signal.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a block diagram of a timing extraction circuit of the embodiment, Fig. 3 is a block diagram of a synchronization detection circuit of the embodiment, and Fig. 4 is a block diagram of the embodiment. FIG. 5 is a time chart diagram of the timing extraction circuit of the embodiment. FIG. 6 is a time chart diagram of the synchronization detection circuit of the embodiment. FIG. 7 shows the operation of the embodiment. FIG. 8 is a time chart diagram showing the correspondence between reference symbols and received signals of the embodiment; FIG. 9 is a block diagram showing the configuration of another embodiment; FIG.
11 is a block diagram of a timing extraction circuit of another embodiment, FIG. 11 is a block diagram of a synchronization detection circuit of another embodiment, and FIG. 12 is a block diagram of a block reproduction circuit of another embodiment. 1 is a timing extraction circuit, 2 is a clock recovery circuit, 4 is a synchronization detection circuit, 7 is a code generator, and 9 is a convolver. ? Convolutional compensation area - ± Figure 2nd group

Claims (3)

[Claims] (1) Clock generation means for generating a clock, code generation means for generating a reference code based on the clock, frequency division means for dividing the frequency of the clock according to the code length of the reference code, and reception. convolver means for correlating a signal with the reference code; peak detection means for detecting a peak of the output of the convolver means; and frequency dividing means and peak detection means for determining the timing at which the clock generation means generates the clock. 1. A receiving device for spread spectrum communication, comprising a control means for controlling according to the output of the spread spectrum communication. (2) correlation means for correlating the periodically generated pseudo-noise code with the received signal; peak detection means for detecting the peak of the correlation means; and a correlation between the start of the pseudo-noise code and the output of the peak detection means A receiving device for spread spectrum communication, comprising a time difference measuring means for measuring a time difference. (3) The receiver for spread spectrum communication according to claim 2, further comprising detection means for detecting that the pseudo noise code and the received signal are out of synchronization based on the time difference measuring means. A receiving device for spread spectrum communication characterized by the following.