JPH02130797A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent wrong readout from the title memory device and to improve the reliability of the device by adopting a electric charge reading-out system as the data reading-out system of the device. CONSTITUTION:In the readout mode, a bit line BL is first precharged to a power supply voltage Vcc by changing a pre-charge signal PB to an L level from an H level. When the pre-charging is made, a selected MOS transistor (Tr) S1 is maintained in a turned off state since the gate SG1 of the Tr S1 is L in level. When, for example, the data of a memory cell M3 are read out, Trs S1 and S2 are turned on and a selected word line WL3 is set to an H level, while other word lines WL1, WL2, and WL4 are set to H levels. In this case, the bit line BL is maintained in a floating state. A nonselected memory cell upon which an H level is impressed is turned on irrespective of the content of the data of the memory cell and turned on or off in accordance with the information of the memory cell M3. When a sense amplifier SA is activated at prescribed timing, the potential at the bit line BL drops and, when the potential becomes lower than reference potential VREF, the data output Dout becomes H in level and, when the potential at the bit line BL is maintained at the power supply voltage Vcc, the output Dout becomes L in level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a nonvolatile semiconductor memory device having a floating gate and a control gate.

(Prior art) In the field of E2 FROM, MO3FE with floating gate
Devices using T-structure memory cells are widely known.

This E2 FROM memory array is constructed by arranging memory cells at each intersection of row lines and column lines that intersect with each other. In the actual pattern, the drains of the two memory cells are made common and the column lines are brought into contact with the drains to minimize the area occupied by the cells. However, even in this case, a contact portion with the column line is required for each common drain of two memory cells, and this contact portion occupies a large portion of the cell occupation area.

On the other hand, recently we have connected memory cells in series to
We are proposing E2 FROM, which is configured as an AND cell and makes it possible to significantly reduce the number of contact parts. This NA
In the ND cell, each memory cell stores one bit of "1" or "0" depending on the threshold value. For example, "1" is a state in which electrons from the floating gate are emitted to change the threshold voltage in the negative direction (for example, threshold voltage -2V), and "0"
" is a state in which electrons are injected into the floating gate to change the threshold value in the positive direction (eg, threshold value +3V).

During a read cycle in a NAND cell type E2 FROM, the selected word line is set to "L" level (for example, OV),
The remaining unselected word lines are given an "H" level (for example, power supply voltage Vcc) to be rendered conductive, and a determination is made based on whether or not current flows through the NAND cell.

However, in a NAND cell, due to its configuration, when reading one memory cell, a current is inevitably passed through the remaining unselected memory cells, all of which are connected in series. For example, in an 8NAND cell, 7 are unselected,
This is connected in series to one selected memory cell. Then, if the information of the seven non-selected memory cells is all “0” and if all the information is “1”, N
A large difference occurs in the current flowing through the AND cell.

This is the most extreme example, but even if it is not such a case, for example, if the threshold voltages of "1" and "0" of unselected memory cells vary, a difference will occur in the read current. Become.

In order to detect information in such a current readout type memory cell, a dummy cell that can obtain a reference current of approximately 1/2 of the cell current is usually prepared, and the magnitude relationship between this reference current and the readout current is determined using a differential amplifier. A method of detection is used. However, as mentioned above, the read current varies greatly < N
In the AND cell method, there are problems in that erroneous readings occur frequently and it becomes difficult to set the value of the reference current itself.

(Problem to be solved by the invention) As described above, E2 FRO using conventional NAND cells
M has a problem in that erroneous reading occurs due to its unique configuration and reliability is insufficient.

An object of the present invention is to provide a NAND cell type E2 FROM that solves these problems.

[Structure of the Invention] (Means for Solving the Problems) The E2 PROM according to the present invention is a NAN in which a plurality of memory cells each having a floating gate and a control gate are connected in series.
This constitutes D cells, which are arranged in a matrix to constitute a memory array. Memory cells write and erase data by tunneling electrons between the floating gate and the substrate.

In the E2 FROM having such an operating principle, the present invention employs a charge read type as a data read method instead of the conventional current read type.

That is, the bit line is provided with a means for precharging it to a predetermined potential, and a sense amplifier is provided that detects a change in the potential when a memory cell is selected with the precharged bit line disconnected from the power supply. establish.

(Function) According to the present invention, when the selected memory cell is turned off during reading, the potential of the precharged bit line does not change, and when the selected memory cell is turned on, the precharged bit line potential does not change. Since the electric charge on the bit line discharged through the NAND cell including the selected memory cell and the potential decreases, information "1#" and "0" can be determined based on the change in potential.

When a large number of unselected memory cells are connected in series, the cell current flowing therein may vary greatly depending on their information content, as described above. However, since the present invention is of a charge read type, the bit line potential difference between "0" and "1" becomes large after a certain period of time, so that information discrimination can be performed reliably.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the main part configuration of one embodiment, and FIG. 2 is an operation timing diagram thereof.
The overall structure of FROM will be explained.

FIG. 3 shows a memory array of an E2FROM according to one embodiment. In this embodiment, four memory cells M1 to M4 are connected in series to form a NAND cell.
D cells are arranged in a matrix. The drain of the NAND cell is connected to the bit line BL via the first selection MOS transistor S1, and the source is grounded via the second selection MOS transistor S2. A control gate of each memory cell is connected to a word line WL arranged to intersect with the bit line BL.

FIG. 4 is a plan view showing one NAND cell in this E2 FROM, and FIGS. 5(a) and 5(b) are its A-
It is an A'BB' sectional view.

In this embodiment, four memory cells are formed in one region of a silicon substrate 1 surrounded by an element isolation insulating film 2. In each memory cell, a floating gate 4 is formed on a substrate 1 by a first layer polycrystalline silicon film via a first gate insulating film 3 made of a thermal oxide film, and a second gate insulating film made of a thermal oxide film is formed on the floating gate 4.
A control gate 6 made of a second layer polycrystalline silicon film is formed with a gate insulating film 5 interposed therebetween. The control gates 6 of each memory cell are arranged continuously in one direction to form a word line WL. Four memory cells are connected in series, with the n+ type layer 9 serving as the source and drain of each memory cell being shared by adjacent cells.

The drain at one end of the NAND cell is connected to the bit line 8 via the first selection MOS transistor S1 formed by the gate electrode 6, and the source at the other end is connected to the gate electrode 6.
A second selection MOS transistor S2 constituted by
to a ground wire (not shown).

In such a configuration, the floating gate 4 in each memory cell
The coupling capacitance C1 between the floating gate 4 and the control gate 6 tube is set smaller than the coupling capacitance C2 between the floating gate 4 and the control gate 6 tube.

To explain this by citing specific cell parameters,
For example, the pattern dimensions are 1 μm in width and 1 μm in channel width for floating gate 4 and control gate 6 according to the 1 μm rule.
The floating gate 4 is placed on both sides of the field region by 1 μm.
It is being extended. The first gate insulating film 3 is, for example, a 200-layer thermal oxide film, and the second gate insulating film 5 is a 350-layer thermal oxide film. If the dielectric constant of the thermal oxide film is ε, then C1-ε10.02 and C2-3810,035. That is, C1 minus C2.

FIG. 6 is a waveform diagram for explaining write and erase operations in the NAND cell of this embodiment. Focusing on the NAND cell consisting of memory cells M1 to M4 in FIG. 3, first, the memory cell M constituting the NAND cell
Delete 1 to M4 all at once. Therefore, in this embodiment, the gate electrodes SG of the selection MOS transistors s, s2
,, Set SG2 to "H" level. Specifically, S.G.l.
The boosted potential Vpp is 20 V, S G2
2 gives the power supply Vc c Vc c "5V. Further, the words 19jWL-WL4 are given the boosted potential Vpp-20V as @H" level. That is, all memory cells M1 to M
The "H" level is applied to the control gate No. 4. This results in
An electric field is applied between the control gate of the memory cell and the substrate, and electrons are injected into the floating gate from the inversion layer formed on the substrate surface through the tunnel effect.

As a result, the threshold values of the memory cells M1 to M4 move in the positive direction and become in the "0" state. In this way, the word line WL, ~
All NAND cells along WL4 are erased at once.

Next, data writing to the NAND cell is performed as follows. Data writing is performed in order from the memory cell M4 farthest from the bit line BL. This is because, as will be clear from the following explanation, the memory cells on the bit line side from the selected memory cell enter the erase mode during the write operation. First, writing to the memory cell M4 is performed by writing to the gate S61 of the selection MOS transistor S1 and the word line wt, as shown in FIG.
,, ~WL31: Boosted potential V pp+ V th (
V th is the threshold value when erasing the memory cell) or more.
Apply an H'' level, for example, 23V.Apply an “L” level (OV) to the gate SG2 of the selection MOS transistor S2.The word line connected to the control gate of the selected memory cell M4 is set to an “L” level (for example, OV). At this time, when the "H" level is applied to the bit line BL, this becomes the selection M.
The signal is transmitted to the drain of memory cell M4 through the OS transistor S1 and the channels of memory cells M1 to M3, and a high electric field is applied between the control gate and the substrate in memory cell M4. As a result, the electrons in the floating gate are emitted to the substrate due to the tunnel effect, and the threshold value moves in two directions, for example, to a state "1#" with a threshold voltage of -2V.At this time, in the memory cells M1 to M3, the control gate No electric field is applied between the data and the substrate, and the erased state is maintained.

In the case of writing "0", the "L" level is applied to the bit line BL. At this time, the memory cells M] to M3 located on the bit line BL side from the memory cell M4 enter the erase mode, but this is not a problem because no data has been written yet.

Next, as shown in FIG. 6, writing to the memory cell M3 is started. That is, the gates SG1 and SG2 of the selection MOS transistors
Word 1. W L 3 while keeping the “H# level” of
At this time, the bit line BL is set to “H” level.
'' level is applied, 1'' is written in the memory cell M3. Similarly, writing is sequentially performed in the memory cells M1 and M1.

Next, the main structure and readout operation related to the charge readout type, which is a feature of the present invention, will be explained.

Figure 1 shows the main configuration. A precharge MOS transistor Qp is provided on the bit line BL.

In this embodiment, this precharge MOS transistor is a p-channel, and the precharge signal PB is “L#”.
By setting the bit line BL to the power supply potential VC level
It is designed to charge to C. The bit line BL is also provided with a sense amplifier SA for detecting minute changes in potential. The sense amplifier SA here includes an n-channel MOS transistor QllQ2 that operates differentially and a p-channel MOS transistor Q3 . It is constituted by a current mirror type differential amplifier consisting of Q4. Two differentially operated MOS) transistors Q1. The reference potential vREF is input to one gate of Q2, and the other gate is connected to the bit line BL. An activation p-channel MO8h transistor Q5 is provided on the power supply side.

The read operation will be explained using FIG. 2. When entering the read mode, first, the bit line BL is precharged to VCC by changing the precharge signal PB- from the 'H' level (VoC-5V) to the 'L' level (-0V). At this time, the selected MO9) transistor S1 has its gate S
Gl is at "L" level and is kept off. For example, when reading data from memory cell M3,
After this, select MO3) Turn on transistor S1+82,
The selected word line WL3 is set to "L" level (for example, OV), and the other word lines WL1 . W
An "H" level (eg, Vcc) is applied to L2 and WL4. At this time, the bit line BL is kept in a floating state separated from all power sources. If the threshold value of a memory cell in an erased state is, for example, +2V, an unselected memory cell to which an "H" level of 5V is applied is turned on regardless of its data content. The selected memory cell M3 is turned on or off depending on the information. Therefore, depending on the information of the selected memory cell M3, either the charge on the bit line BL precharged through this NAND cell is discharged and its potential decreases, or the potential on the bit line BL is maintained as it is. The following state is obtained. Therefore, when the sense amplifier SA is activated at a predetermined timing, the bit line B
As the potential of L decreases, the reference potential VREF (for example, 3
When the bit line BL is kept at VCC, the data output D out becomes an "L" level.

In this way, according to this embodiment, even if there is a large variation in the impedance of the entire NAND cell due to the information of unselected memory cells during reading, unlike the case of current reading, the data can be reliably read after a certain period of time. “0”
, "1" can be determined. Therefore, a highly reliable E2 FROM with no read malfunctions can be obtained.

The present invention is not limited to the above embodiments.

For example, in the embodiment, a case has been described in which a NAND cell is configured with four memory cells, but the number of memory cells is arbitrary. For example, a NAND cell can be configured with eight memory cells, and the present invention provides particularly great effects when a large number of memory cells are used in one NAND cell. Further, the precharge potential of the bit line is not limited to the power supply potential VCC, and for example, (1/2) Vcc or the like may be used. Furthermore, it is possible to use other circuits such as a normal inverter as a sense amplifier.

〔Effect of the invention〕

As described above, according to the present invention, by using a charge read-out type, erroneous reading due to causes specific to NAND cell type E2FROM can be prevented, and highly reliable E2FROM can be realized.
ROM can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the main part configuration of an E2 PROM according to an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the read operation, and FIG. 3 is a diagram showing the memory array configuration of the E2 FROM. , FIG. 4 is a plan view of one NAND cell, and FIGS. 5(a) and 5(b) are A-A' and B- of FIG.
B' cross-sectional view and FIG. 6 are operational waveform diagrams for explaining data erasing and writing operations. M) -M4...Memory cell, S,, S2...
Selection MOS transistor, Qp...M for precharging
OSl-transistor, BL...bit line, SA...
sense amplifier. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 3 r-B Figure Figure Figure

Claims (3)

[Claims] (1) A floating gate and a control gate are stacked on a semiconductor substrate, and multiple rewritable memory cells are connected in series to perform writing and erasing by exchanging electric charge with a tunnel current between the floating gate and the substrate. In a nonvolatile semiconductor memory device configured with NAND cells arranged in a matrix, one end of each NAND cell connected to a bit line, and the gate of each memory cell connected to a word line, the bit line is 1. A nonvolatile semiconductor memory device comprising: means for precharging to a predetermined potential; and a sense amplifier connected to a bit line and detecting a change in potential of the bit line that is precharged and disconnected from a power supply. (2) The nonvolatile semiconductor memory device according to claim 1, wherein the sense amplifier is a current mirror type differential amplifier. (3) The nonvolatile semiconductor memory device according to claim 1, wherein the sense amplifier is an inverter.