JP3660503B2 - Nonvolatile semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device using EEPROM cells capable of batch erasing stored data.
[0002]
[Prior art]
14 to 17 show an example of a conventional nonvolatile semiconductor memory device, which shows a NOR flash memory. 14 shows the structure of a single memory cell, FIG. 15 is a sectional view taken along the line 15-15 in FIG. 14, and FIG. 16 is a sectional view taken along the line 16-16 in FIG. 14 to 16, an N-type well region 102 is formed in a P-type semiconductor substrate 101, and a P-type well region 103 is formed in the well region 102. A plurality of element isolation regions 104 are formed in the surface region of the well region 103, and a gate oxide film 105 is formed between the element isolation regions 104. A floating gate (FG) 106 is formed on the gate oxide film 105, and a control gate (CG) 108 is formed on the floating gate 106 with an insulating film 107 interposed therebetween. Diffusion layers 109 and 110 constituting drains and sources are formed in the well regions located on both sides of these gates. An insulating film 111 is formed on the control gate 108, and a bit line (BL) 112 connected to the drain 109 is formed on the insulating film 111.
[0003]
FIG. 17 shows a NOR type memory cell array block in which the memory cells having the above configuration are arranged in a matrix. This memory cell array block has memory cells MC00 to MCnm, and control gates of a plurality of memory cells arranged in the same row are connected to word lines WLn, WLn-1,. Bit lines BL0, BL1... BL7, BL8... BLm are connected to the drains of the plurality of memory cells arranged in the column. The source of each memory cell is connected to a common source line SL. In this memory cell array block, writing, reading and erasing operations when the bit width is 8 are as follows.
[0004]
When memory cells MC00 to MC07 are selected at the time of data writing, Vpp (voltage of about 10V) is applied to word line WL0 shared by these memory cells, and the other word lines are set to 0V. The voltage of the bit line depends on the write data. Vdp (a voltage of about 5 V) is applied to the bit line for writing data “0”, and 0 V is applied to the bit line for writing “1” data. The common source line SL is set to 0V. In a memory cell having a gate of Vpp and a drain of Vdp, some electrons moving from the source to the drain have high energy, and this reaches the floating gate by an electric field in the gate direction. In this way, the “1” state memory cell with a relatively small number of electrons in the floating gate is changed to a “0” state memory cell with a relatively large number of electrons. In a memory cell having a voltage relationship between the gate and the drain, the drain current does not flow and the data in the memory cell does not change.
[0005]
When memory cells MC00 to MC07 are selected at the time of data reading, power supply voltage Vcc (a voltage of about 5 V) is applied to word line WL0 shared by these memory cells. Other word lines are set to 0V. A voltage Vd (a voltage of about 1 V) is applied to the selected bit line, and 0 V is applied to the unselected bit lines. The common source line SL is set to 0V. The threshold voltage of the memory cell in the “1” state is lower than the power supply voltage Vcc, and the threshold voltage of the memory cell in the “0” state is higher than the power supply voltage Vcc. Therefore, a current flows in the memory cell in the “1” state, and no current flows in the memory cell in the “0” state. By sensing this current, data “0” or “1” can be read.
[0006]
Data is erased collectively in memory cell array block units. At this time, if all the word lines are set to 0 V and the P-type well and the N-type well are set to the erase voltage Vee (voltage of about 20 V), a high electric field is applied to the gate oxide film, and electrons in the floating gate are Move to P-type well by tunneling. Thus, the data of all the memory cells in the selected memory cell array block becomes “1”. At this time, since the P-type well of the non-selected memory cell array block is set to 0V and the potentials of the word lines are all set to 0V, the data in the array block is not erased.
[0007]
As a method of erasing data, there is a method of applying a bias voltage to the source in addition to a method of applying a bias voltage to the well. At this time, when the well or the memory cell is formed on the P-type substrate, the substrate is grounded. When a voltage is applied in this way, a tunnel current flows in the overlap portion between the source diffusion layer and the gate, and data is erased.
[0008]
As described above, a high voltage is required for writing and erasing data, and it is difficult to reduce the size of a transistor that handles this high voltage. The memory cell cannot be thinned because the thickness of the tunnel oxide film is defined by the conditions for ensuring reliability. It is also difficult to lower the write voltage in order to ensure reliability. Under these circumstances, even if the bit cost can be reduced by reducing the size of the memory cell, it is difficult to reduce the area occupied by the row decoder including a transistor to which a high voltage is applied or the column gate in the chip. Therefore, the area ratio with respect to these memory cell array blocks is increased, and the cost reduction effect is reduced.
[0009]
[Problems to be solved by the invention]
FIG. 18 shows a block configuration of a conventional nonvolatile semiconductor memory device. Four memory core units 202, 203, 204, and 205 are arranged on the chip 201. An address buffer 206 that receives an address signal in the vicinity of the memory core unit, a control unit 207 that performs overall control of the nonvolatile semiconductor memory device, a write circuit 208 that receives write data and writes this data to the selected memory, and selection A sense amplifier 209 for sensing data read from the read memory cell is arranged. Each memory core unit has the same configuration. That is, a memory cell array block (MCAB) 210 in which memory cells (not shown) are arranged in a matrix, a row predecoder (RPDC) 211 that selects a row in the memory cell array block according to an address signal, and a row main decoder ( RMDC) 212, a pre-column gate (PCG) 213 for selecting a column in the memory cell array block according to an address signal, and a main column gate (MCG) 214.
[0010]
As described above, each memory core section includes the memory cell array block 210, the row predecoder 211, the row main decoder 212, the precolumn gate 213, and the main column gate 214. In addition, the row main decoder 212 includes a transistor having a large size to which a high voltage is applied. Therefore, as described above, even if the size of the memory cell array block 210 is reduced, the area occupied by the row predecoder 211, the row main decoder 212, the precolumn gate 213, and the main column gate 214 cannot be reduced. There is a problem that the effect of reducing the size of the memory cell with respect to the bit cost is reduced.
[0011]
The present invention has been made to solve the above-described problems, and an object of the present invention is to reduce the ratio of the area of the row decoder and column gate to the memory cell array block and to reduce the memory cell size. Therefore, an object of the present invention is to provide a nonvolatile semiconductor memory device that can reduce the bit cost.
[0012]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a plurality of nonvolatile semiconductor memory cells, a plurality of local word lines connected to the plurality of memory cells, and a plurality of local bit lines connected to the plurality of memory cells. And a source line connected to the plurality of memory cells. Rume Mori cell array block; Previous Select a local word line First 1 row decoder; Previous Select a local bit line First 1 column gate and A plurality of memory core units having a row and a column, By global word line Arranged in each row Connected to a plurality of said first row decoders plural With a second row decoder and a global bit line Arranged in each row Connected to a plurality of the first column gates plural A second column gate; plural A write circuit connected to a second column gate for supplying write data to the second column decoder; plural A nonvolatile semiconductor memory device comprising: a sense amplifier connected to a second column gate and detecting data read from the memory cell via the first and second column gates.
[0013]
The local bit line is composed of a first layer metal wiring, the global bit line is composed of a second layer metal wiring, and the global word line is composed of a third layer metal wiring.
[0014]
Said plural A selection signal is supplied to the first and second column gates through the first-layer or third-layer metal wiring.
The local bit line is composed of a first layer metal wiring, the global word line is composed of a second layer metal wiring, and the global bit line is composed of a third layer metal wiring.
[0015]
The memory Core part A source line decoder is provided for each, and supplies an erase potential to the source line of the selected memory cell array block in accordance with a block address signal at the time of erasure.
[0016]
The memory Core part A well decoder is provided for each and supplies an erase potential to a well of a selected memory cell array block in accordance with a block address signal at the time of erasure.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a first embodiment of a nonvolatile semiconductor memory device according to the present invention, and shows a block configuration of a NOR type flash memory, for example. In the memory block 10, four memory core units 11, 12, 13, and 14 are arranged. An address buffer 15 that receives an address signal in the vicinity of these memory core units 11, 12, 13, and 14, a control unit 16 that performs overall control of the nonvolatile semiconductor memory device, receives write data, and stores the data A write circuit 17 for writing data and a sense amplifier 18 for sensing data read from a selected memory cell are arranged. The memory core units 11, 12, 13, and 14 have the same configuration. That is, each memory core section is composed of a memory cell array block (MCAB) 19, a local row decoder (LRDC) 20, and a local column gate (LCG) 21.
[0018]
The memory cell array block (MCAB) 19 has a plurality of memory cells MC (not shown) arranged in a matrix, local word lines WL and local bit lines BL connected to the memory cells MC. The specific configuration of the memory cell array block 19 is the same as the configuration shown in FIG. The local row decoder 20 selects the local word line WL according to the address signal supplied from the address buffer 15, and the local column gate 21 selects the local bit line BL. The local row decoder 20 disposed in each of the memory core units 11 and 12 is connected to a global row decoder (GRDC) 22a through a global word line GWL. The global row decoder (GRDC) 22 a selects the local row decoder 20 of the memory core unit 11 or the local row decoder 20 of the memory core unit 12 according to the address signal supplied from the address buffer 15. Similarly, the local row decoder 20 disposed in each of the memory core units 13 and 14 is connected to a global row decoder (GRDC) 22b through a global word line GWL. The global row decoder 22b selects the global word line GWL according to the address signal supplied from the address buffer 15.
[0019]
On the other hand, the local column gates 21 arranged in the memory core units 11 and 13 are connected to the global column gate 23a through the global bit line GBL. The global column gate 23a selects the global bit line GBL. Similarly, the local column gates 21 disposed in the memory core units 12 and 14 are connected to the global column gate 23b through the global bit line GBL. The global column gate 23b selects the global bit line GBL.
[0020]
Further, the local column gates 21 arranged in the memory core units 11 and 12 are respectively connected to a local column gate driving unit (LCGD) 24a via a wiring L1. The local column gate driving unit 24 a drives the local column gate 21 arranged in the memory core units 11 and 12 according to the address signal supplied from the address buffer 15. The local column gates 21 arranged in the memory core units 13 and 14 are connected to a local column gate driving unit (LCGD) 24b through a wiring L2. The local column gate driving unit 24 b drives the local column gate 21 arranged in the memory core units 13 and 14 according to the address signal supplied from the address buffer 15. Further, the global column gates 23a and 23b are connected to the global column gate driving unit 24c through the wiring L3. The global column gate driver 24c selects and drives one of the global column gates 23a and 23b according to the address signal supplied from the address buffer 15. The local column gate driving units 24 a and 24 b and the global column gate driving unit 24 c are connected to a column decoder (CDC) 25. The column decoder 25 drives one of the local column gate driving units 24 a and 24 b and the global column gate driving unit 24 c in accordance with the address signal supplied from the address buffer 15.
[0021]
The global column gates 23a and 23b are connected to the write circuit 17 via the data line DL and also to the sense amplifier 18. At the time of data writing, the global column gates 23a and 23b are selectively driven by the column decoder 25 and the global column gate driving unit 24c, and the data from the writing circuit 17 is transferred to the local column gate driving unit 24a or the local column gate driving unit 24c. This is supplied to the local column gate 21 selected by the column gate driving unit 24b. In addition, when reading data, the global column gates 23 a and 23 b supply the data read from the memory cell of the selected memory cell array block 19 to the local column gate 21 to the sense amplifier 18.
[0022]
FIG. 2 shows a case where the nonvolatile semiconductor memory device shown in FIG. 1 is applied to a general-purpose memory, for example, and the same parts as those in FIG. In the general-purpose memory 30, the address terminal A of the memory block 10 is connected to the address pin ADD, the control signal input / output terminal B is connected to the control signal input / output pin CTL, and the data input / output terminal C is input / output buffer (I / O) It is connected to the input / output pin IO via 31.
[0023]
FIG. 3 shows a case where the nonvolatile semiconductor memory device shown in FIG. 1 is applied to, for example, a microprocessor. The microprocessor 32 has a memory block 10 and a logic gate 33. The address terminal A, the control signal input / output terminal B, and the data input / output terminal C of the memory block 10 are respectively connected to the logic gate 33, and the logic gate 33 is connected to the input pin IN and the output pin OUT. For example, the logic gate 33 reads out data stored in the memory block 10 and performs arithmetic processing, and the calculation result is output to the outside or stored in the memory block 10 again.
[0024]
FIG. 4 shows the configuration of the global row decoder GRDC. This global row decoder includes a NAND circuit 41a to which row address signals RAi and RAj are supplied, a plurality of P channel MOS transistors (hereinafter referred to as PMOS transistors) 41b to 41e, and a plurality of N channel MOS transistors (hereinafter referred to as NMOS transistors). ) 41f to 41i, and an inverter circuit 41j connected between the output terminal of the NAND circuit 41a and the gate of the NMOS transistor 41g. A global word line GWLij is connected to the connection point of the PMOS transistor 41d and the NMOS transistor 41h. Is connected.
[0025]
In the global row decoder GRDC, when the output signal of the NAND circuit 41a becomes a high level in response to the row address signals RAi and RAj, the NMOS transistor 41f, the PMOS transistor 41e, and the NMOS transistor 41h are sequentially turned on to turn on the global word line. GWLij is set to a low level (ground potential). When the output signal of the NAND circuit 41a becomes low level according to the row address signals RAi and RAj, the NMOS transistor 41g and the PMOS transistor 41d are sequentially turned on, and the global word line GWLij is set to high level (voltage VSW). The
[0026]
FIG. 5 shows the configuration of the local row decoder (LRDC). In this local row decoder, a unit connected to the local word line WLijk includes an inverter circuit 51a, a transfer gate 51b, and an NMOS transistor 51c. An input terminal of the inverter circuit 51a is connected to the global word line GWLij, and an input / output terminal of the inverter circuit 51a is connected to both gates of the transfer gate 51b. The input terminal of the transfer gate 51b is supplied with a power supply Fk (for example, 5V when reading data, 10V when writing data), and the output terminal is connected to a local word line WLijk arranged in the memory cell array block MCAB. In the NMOS transistor 51c, a current path is connected between the output terminal of the transfer gate 51b and the ground, and the gate is connected to the output terminal of the inverter circuit 51a.
[0027]
The unit connected to the local word line WLijk ′ has the same configuration as that of the unit connected to the local word line WLijk.
[0028]
In the local row decoder, when the global word line GWLij goes high, the transfer gate 51b is turned on, the NMOS transistor 51c is turned off, and the local word line WLijk is selected. A voltage corresponding to data reading or writing is supplied to the local word line WLijk through the conductive transfer gate 51b.
[0029]
FIG. 6 shows the configuration of the global column gate GCG. The global column gate GCG is composed of a plurality of NMOS transistors 61a to 61d. One ends of the current paths of the NMOS transistors 61a to 61d are connected to the write circuit 17 and the sense amplifier 18 through the data line DL. The other ends of the current paths of the NMOS transistors 61a to 61d are connected to global bit lines GBL0 to GBL3, respectively, and selection signals CA4 to CA7 output from the global column gate driver are supplied to the gates. These NMOS transistors 61a to 61d are turned on in response to selection signals CA4 to CA7, and global bit lines GBL0 to GBL3 are selected.
[0030]
FIG. 7 shows a configuration of the memory cell array block MCAB and the local column gate LCG connected to one of the global bit lines GBL. The local column gate LCG includes a plurality of NMOS transistors 71a to 71d. One ends of the current paths of the NMOS transistors 71a to 71d are connected to the global bit line GBL. The other ends of the current paths of the NMOS transistors 71a to 71d are connected to local bit lines BL0 to BL3, respectively, and selection signals CA0 to CA3 output from the local column gate driver are supplied to the gates. These NMOS transistors 71a to 71d are turned on in response to the selection signals CA0 to CA3, and connect the selected local bit line to the global bit line GBL.
[0031]
In the memory cell array block MCAB, the plurality of memory cells MC connected to the local word line WL0 and the sources of the plurality of memory cells MC connected to the local word line WL1 are commonly connected to the source line SL, and the drains correspond to each other. Connected to the local bit lines BL0 to BL3.
[0032]
FIG. 8 shows a cross section of the memory cell array block MCAB, and the same parts as those in FIG. The local bit line BL is composed of, for example, a first layer metal wiring (M1), the global bit line GBL is composed of, for example, a second layer metal wiring (M2), and the global word line GWL is, for example, a first layer metal wiring (M1). A third-layer metal wiring (M3) is used. These global word lines GWL and global bit lines GBL are arranged above the memory cell array block.
[0033]
FIG. 9 shows a modification of FIG. The local bit line BL is composed of, for example, a first layer metal wiring (M1), the global word line GWL is composed of, for example, a second layer metal wiring (M2), and the global bit line GBL is composed of, for example, a third layer. It is configured by a metal wiring (M3) of the layer. Even in such a configuration, each wiring can be arranged.
[0034]
Further, the wirings L1, L2, and L3 connected to the local column gate driving units 24a and 24b and the global column gate driving unit 24c are more specifically the local bit line BL or the global word than the wiring layer different from the global bit line GBL. The same wiring layer as the line GWL is used. That is, when the global bit line GBL is the second-layer metal wiring (FIG. 8), the wirings L1 to L3 are the first or third-layer (preferably the third-layer) metal wiring. When the global bit line GBL is a third-layer metal wiring (FIG. 9), the wirings L1 to L3 are first or second-layer (preferably second-layer) metal wiring. Note that the first to third metal wirings can be used for the data line DL.
[0035]
According to the first embodiment, each of the memory core units 11 to 14 has only the memory cell array block 19, the local row decoder 20, and the local column gate 21, and the global word line GWL is selected by the global row decoders 22a and 22b. The global bit line GBL is selected by the global column gates 23a and 23b. Therefore, since the global row decoders 22a and 22b and the global column gates 23a and 23b can be shared by a plurality of memory core parts, the area of the memory core part can be reduced as compared with the conventional case, and the entire chip size can be reduced. In this configuration, when the number of memory core units increases with an increase in storage capacity, the above-described effect appears more remarkably.
[0036]
FIG. 10 shows a second embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals and only different parts will be described. In the second embodiment, a source line decoder (SD) is further added to the configuration shown in the first embodiment. That is, a source line decoder (SD) 26 is provided in each of the memory core units 11 to 14. For example, all the source lines SL in each memory cell array block MCAB are commonly connected, and the commonly connected source lines are connected to the corresponding source line decoder (SD) 26. The source line decoder 26 supplies an erase potential to the source line of the memory cell array block selected according to the block address signal for selecting the memory cell array block when erasing data.
[0037]
FIG. 12 shows an example of the source line decoder SD disposed in the i-th memory core unit, for example. The source line decoder SD includes a NAND circuit 81a to which a block address signal BADDi and an erase signal ERAE are supplied, a plurality of PMOS transistors 81b to 81d, a plurality of NMOS transistors 81e to 81g, an output terminal of the NAND circuit 81a, and the NMOS The inverter circuit 81h is connected between the gate of the transistor 81f. The PMOS transistor 81d and the NMOS transistor 81g constitute an inverter circuit 81i, and the source line SLi of the i-th memory cell array block is connected to the output terminal of the inverter circuit 81i. The erase potential Vee is supplied to the sources of the PMOS transistors 81b to 81d, and the sources of the NMOS transistors 81e to 81g are grounded.
[0038]
In the above configuration, at the time of erasing, when the erase signal ERAE becomes high level and the block address signal BADDi becomes high level, the output signal of the NAND circuit 81a becomes low level. For this reason, the NMOS transistor 81f connected to the output terminal of the inverter circuit 81h is turned on, the PMOS transistor 81d is turned on, and the erase potential Vee (for example, 10V) is supplied to the source line SLi. Therefore, the data in the memory cell array block to which the source line SLi is connected is collectively erased.
[0039]
On the other hand, all output signals of the source line decoder SD in which the block address signal BADDi is not selected are at the low level (0 V). Therefore, the memory cell array block connected to the source line decoder SD is not erased. In other operation modes, for example, when data is written or read, 0 V is applied to the source lines of all blocks.
[0040]
According to the second embodiment, by arranging the source line decoder in each memory cell core portion, the source line to be erased can be selected and the erase potential can be supplied without increasing the chip area.
[0041]
FIG. 11 shows a third embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals and only different parts will be described. In the third embodiment, a well decoder (WD) is further added to the configuration shown in the first embodiment. That is, each memory core unit 11 to 14 is provided with a well decoder (WD) 27. Each memory cell array block is formed in a P-type well region. Each memory cell array block is connected to a corresponding well decoder 27. The well decoder 27 supplies an erase potential to a well in which a memory cell array block selected according to a block address signal is formed when data is erased.
[0042]
FIG. 13 shows an example of the well decoder WD arranged in the i-th memory core portion, for example. The well decoder WD includes a NAND circuit 91a to which a block address signal BADDi and an erase signal ERAE are supplied, a plurality of PMOS transistors 91b to 91d, a plurality of NMOS transistors 91e to 91g, an output terminal of the NAND circuit 91a, and the NMOS transistor. The inverter circuit 91h is connected to the gate 91f. The PMOS transistor 91d and the NMOS transistor 91g constitute an inverter circuit 91i, and the well Well of the i-th memory cell array block is connected to the output terminal of the inverter circuit 91i. An erase potential Vee is supplied to the sources of the PMOS transistors 91b to 91d, and the sources of the NMOS transistors 91e to 91g are grounded.
[0043]
In the above configuration, when the erase signal ERAE becomes high level and the block address signal BADDi becomes high level at the time of erasing, the output signal of the NAND circuit 91a becomes low level. For this reason, the NMOS transistor 91f connected to the output terminal of the inverter circuit 91h is turned on, the PMOS transistor 91d is turned on, and the erase potential Vee (for example, 10V) is supplied to the well Welli. Therefore, electrons are extracted from the floating gate of the memory cell provided in the well Welli to the well, and the data is erased collectively.
[0044]
On the other hand, all output signals of the well decoder WD in which the block address signal BADDi is not selected are at a low level (0 V). Therefore, the memory cell array block connected to the well decoder WD is not erased. In other operation modes, for example, when data is written or read, 0 V is applied to the wells of all blocks.
[0045]
According to the third embodiment, by arranging the well decoder in each memory cell core portion, it is possible to select the well to be erased while suppressing the increase in the chip area and supply the erase potential.
The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.
[0046]
【The invention's effect】
As described above, according to the present invention, the ratio of the area of the row decoder and column gate to the memory cell array block can be reduced, the memory cell size can be reduced, and the bit cost can be reduced. Can be provided.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a nonvolatile semiconductor memory device according to the present invention.
FIG. 2 is a schematic configuration diagram showing a case where the nonvolatile semiconductor memory device shown in FIG. 1 is applied to a general-purpose memory.
FIG. 3 is a schematic configuration diagram showing a case where the nonvolatile semiconductor memory device shown in FIG. 1 is applied to a microprocessor.
4 is a circuit diagram showing a configuration of a global row decoder GRDC shown in FIG. 1. FIG.
5 is a circuit diagram showing a configuration of a local row decoder LRDC shown in FIG. 1. FIG.
6 is a circuit diagram showing a configuration of global column gate GCG shown in FIG. 1. FIG.
7 is a circuit diagram showing a configuration of a memory cell array block MCAB and a local column gate LCG shown in FIG. 1;
FIG. 8 is a cross-sectional view showing the memory cell array block MCAB shown in FIG. 1;
9 is a cross-sectional view showing a modification of FIG.
FIG. 10 is a configuration diagram showing a second embodiment of the present invention.
FIG. 11 is a configuration diagram showing a third embodiment of the present invention.
12 is a circuit diagram showing an example of a source line decoder shown in FIG.
13 is a circuit diagram showing an example of the well decoder shown in FIG.
FIG. 14 is a plan view showing a NOR type flash memory, showing an example of a conventional nonvolatile semiconductor memory device;
15 is a cross-sectional view taken along the line 15-15 in FIG.
16 is a cross-sectional view taken along line 16-16 of FIG.
17 is a circuit diagram showing a NOR type memory cell array block using the memory cell shown in FIG. 14;
FIG. 18 is a block diagram showing a conventional nonvolatile semiconductor memory device.
[Explanation of symbols]
10 ... memory block,
11, 12, 13, 14 ... memory core part,
15 ... Address buffer,
16 ... control part,
17: writing circuit,
18 ... sense amplifier,
19: Memory cell array block (MCAB),
20: Local row decoder (LRDC),
21 ... Local column gate (LCG),
22a, 22b ... Global Low Decoder (GRDC),
23a, 23b ... Global column gate,
24a, 24b ... Local column gate drive section (LCGD),
24c ... Global column gate drive part (GCGD),
25 ... Column decoder (CDC),
26: Source line decoder (SD),
27: Well decoder (WD),
BL ... Local bit line
WL ... Local word line,
GWL: Global word line,
GBL ... Global bit line,
M1, M2, M3... First to third layer metal wirings.

Claims (6)

A plurality of nonvolatile semiconductor memory cells, a plurality of local word lines connected to the plurality of memory cells, a plurality of local bit lines connected to the plurality of memory cells, and the plurality of memory cells and Rume memory cell array blocks and a source line,
A first row decoder you select a pre-Symbol local word lines,
A first column gate you select a pre-Symbol local bit lines
A plurality of memory core units having a row and a column,
A plurality of second row decoders connected to the plurality of first row decoders arranged in each row by a global word line;
A plurality of second column gates connected to the plurality of first column gates arranged in each column by a global bit line;
A write circuit connected to the plurality of second column gates for supplying write data to the second column decoder;
And a sense amplifier connected to the plurality of second column gates and detecting data read from the memory cells via the first and second column gates. Storage device.   The local bit line is composed of a first layer metal wiring, the global bit line is composed of a second layer metal wiring, and the global word line is composed of a third layer metal wiring. The nonvolatile semiconductor memory device according to claim 1. The local bit line is composed of a first layer metal wiring, the global word line is composed of a second layer metal wiring, and the global bit line is composed of a third layer metal wiring. The nonvolatile semiconductor memory device according to claim 1. 4. The nonvolatile semiconductor memory device according to claim 2, wherein a selection signal is supplied to the plurality of first and second column gates through a metal wiring of a first layer or a third layer. 5. 2. A source line decoder provided for each of the memory core units and supplying an erase potential to the source line of a selected memory cell array block in accordance with a block address signal at the time of erasure. Nonvolatile semiconductor memory device. 2. The nonvolatile memory according to claim 1, further comprising a well decoder provided for each of the memory core units and supplying an erase potential to a well of a selected memory cell array block in accordance with a block address signal at the time of erasure. Semiconductor memory device.

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