JPS628398A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To execute the high sensitivity and the high speed of sense action by using the amplifier in which the load is an N channel current mirror circuit, as a CMOS type differential amplifier. CONSTITUTION:As a CMOS type differential amplifier 10 to compare a sense line electric potential VS with a reference electric potential Vref from a dummy circuit 9 and amplify the sense, an N channel current mirror type amplifier is used in which the load is an N channel current mirror circuit and which has differential pair transistors P3 and P4 of a P channel and a transistor P5 for a constant electric current source of the P channel. Differential pair transistors P1 and P2 and transistors N4 and N5 for the current mirror are formed to the same size, a Vcc electric power source electric potential is given to the source of a transistor P3 for the constant electric current source, and a Vss electric potential (earth electric potential) is given to the source of the transistors N4 and N5 for the current mirror.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to semiconductor memories, and in particular to a cell data readout system for 0MO8W (complementary insulated type) memory, It is used in writable memory) and SRAM (static random access memory).

[Technical background of the invention]

FIG. 6 schematically shows a cell data read system in a CMOB type EFROM, in which 1 is a nonvolatile memory cell consisting of a 70-bit transistor, and 2 is a memory cell for selecting the memory cell 1. Word line, 3
4 is a bit line connected to one end of the memory cell 1, and 4 is a transformer 7 consisting of an N-channel MOS transistor.
Agut, 5 is a noise circuit that applies a predetermined noise voltage to the r-to electrode of the transformer 7 Agut 4, and 6 is a sense line connected to the bit line 3 via the transfer r-)4. , 7 is a load transistor made of a MOS transistor connected between the sense line 6 and the power supply. Reference numeral 8 denotes a sense amplifier consisting of a CMO8 type O8 amplifier, which compares the potential of the sense line 6 with a reference potential given from a dummy circuit 9 for generating a reference potential, and reads the sense line 6 from the read f-ta'1'' or 0'' is detected. The reference potential generation dummy circuit 9 is
Dummy memory cell 1. Word line 2't Bit line 3'
, transfer 'r') 4's no ear circuit 5'
, the sense line 6', and the load transistor 7'. By making the transistor size of the load transistor 7' larger than that of the load transistor 7, Il# and I'IQ of the read data can be changed. An intermediate potential located between the two potentials of the sense line 6 corresponding to " is output as a reference potential.

Although not shown in FIG. 6, a bit line selection MO8) transistor is inserted in series with the bit line.

Next, the operation of the r-data read system will be explained with reference to the bit line potential versus cell current characteristic shown in FIG. 7 and the sense line potential versus load current characteristic shown in FIG. When memory cell 1 and dummy memory cell 1' are selected, if data has not been written to memory cell 1 in advance, memory cell 1 will not be in the on state, and the memory cell current will flow from load transistor 7. An equal load current flows and the low level potential vsL of the sense line 6 is determined. On the contrary,
When data has been written in the memory cell 1 in advance, the dark voltage Vtn of the memory cell transistor is larger by ΔVtx than in the non-written state. In this case, the memory cell current decreases according to the magnitude of ΔVTH, and VyH+jvTH)Mac (a output, time (D)
When the power supply potential is set to IJ (power supply potential), the memory cell 1 is completely off, and the memory cell current becomes zero. At this time, when the threshold voltage of the transfer gate transistor 4 is expressed as VTHN, the bit line potential VmL has a value lower than the dart bias potential by pYtaN (for example, about 1.5 V if the bias potential is 3 V). Oh,
The load current is zero, and the sense line 6 has a high level potential V.
IIH appears. As described above, since the bias circuit 5 suppresses the potential of the bit line VEIL to approximately 1.5 V or less, an unnecessarily high potential is applied to the memory cell 1 during reading, and the stored contents change (wrong writing may occur). occurrence) is prevented. Furthermore, the bit line potential amplitude is small and the bit line delay is also small.

Incidentally, in determining the sense characteristics of the sense amplifier 8, the characteristics of the load transistor 7 become important. 0M
In the 08 circuit, the load transistor shown in Fig. 9 (
, ) to (C) (,) P-channel enhancement type active load m, (b) P-channel enhancement type r-) (G) Drain) short circuit m-1 (c) N-channel enhancement There are three possible types of G-D shortcuts for Men) W. Among these three types of load transistors, when we consider the margin for the variation of Norocess/4 rams or the delay of the sense line, we found that the P-channel G-D short circuit type shown in (b) above is the best after various studies. As it turns out, this has already been proposed by the applicant of the present application in Japanese Patent Application No. 58-92641. This more P-channel G-D type load is
When used in the circuit shown in the figure, the low level V8 of sense line 6
L is, for example, 2.5V, High 1/Hek VHH is, for example, 4.2V (when Vcc = 5V, dirt threshold voltage of P channel transistor VTup = 70.8V)
The bit line potential VIIL is amplified by the load transistor and becomes the sense line potential v3.

On the other hand, as the CMO8 type O8 amplifier 8, conventionally the first
A P-channel current mirror circuit as shown in Figure 0 was used as a load.

Here, %N1 and N1 are N-channel transistors forming a differential pair, N3 is an N-channel transistor for constant current source, Pl and P2 are P-channel transistors connected in a current mirror, and the sense line potential VB is as described above. For example, if the voltage varies between 2.5 V and 4.2 V, the reference potential Vref is set at an intermediate level (for example, 3.2 V). P channel G- to the sense line load as shown above.
When a D-short circuit type is used and a P-channel current mirror type is used as a differential amplifier, the following problems arise. That is, in the above differential amplifier, changes in the current INI of the N-channel transistor N1 and the current xpt of the P-channel transistor P1 when the sense line potential Vs is at a high level vs. , even when the sense line potential s is at a low level, a current flows through the N-channel transistor N, so the size of the P-channel transistor P1 must be made sufficiently large in order to output a level of 1 as the amplifier output at this time. Must be. This means that N in the differential amplifier
When the degree of freedom in selecting the size ratio between the channel transistor and the P-channel transistor is small, the sense line potential V,
When the low level output of the differential amplifier is at a high level, the potential becomes high. Tsumashi,
Regarding the N-channel transistor Nl, if its dart threshold voltage VTHN is 0.8V, its f-)
The potential (sense H't level Vs) is at high level (4, 2
V) When O, KVo VTn is 3.4 V (=4
．． 2-0.8) Without K, when the above dirt potential is low level (2.5V), VG-VtT1 is 1.7V
(=2.5-0.8) FC, the current difference in the N-channel transistor N1 due to the high level and low level of the sense line potential VB is not sufficient, and its drain potential (differential amplifier output) is low level. The high level potential difference is no longer sufficient. FIG. 12 shows the input (sense line potential) vs. output characteristics of the P-channel current mirror type differential amplifier, and shows how the differential amplifier is less likely to produce a low level as described above. Furthermore, the output of the differential amplifier does not necessarily change sensitively to changes in the sense line potential. As described above, the sense line potential is determined by the current value of the selected cell, and this potential continuously changes depending on the cell current value. Therefore, depending on the cell threshold voltage change ΔvTH determined by the amount of charge written to the memory cell, the sense line potential may become extremely close to the reference potential Vyef. In such a case, if the sensitivity of the P-channel current mirror differential amplifier is poor as described above, the operation delay of this differential amplifier will become large.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances.
The present invention provides a semiconductor memory that can realize high sensitivity and high speed sensing operations using a W differential amplifier.

[Summary of the invention]

That is, the present invention uses P channel G-D as a sense line load.
In semiconductor memory using type transistors, 0M
The O8W differential amplifier is characterized in that the load is an N-channel current mirror circuit.

This causes the sense line to reach a high level.

A sufficient current difference in the P-channel transistor for sensing operation of the differential amplifier with respect to the low level can be obtained).
Accordingly, a sufficient potential difference between the output potentials of the differential amplifier can be obtained, and higher sensitivity and higher speed sensing operations can be realized.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

Figure 1 shows the cell data reading system of CMO8fi KPROM. -Eas circuit 5. The sense line 6, the P-channel G/D short circuit load transistor 7, and the reference potential generation dummy circuit 9 are connected to each other.
This is the same as the conventional example described above with reference to FIG.
0, the load is an N-channel current mirror circuit and P-channel differential pair transistors P3eP4 and P
This differs from the conventional example in that an N-channel current mirror type device having a channel constant current source transistor Ps is used. Here, the differential pair transistor P1*
Transistor N4p for P snow and current mirror
Ng are formed to the same size, and the Vee power supply potential is applied to the source of the constant current source transistor P3,
Current mirror transistor N4. V to the source of N.
llll potential (ground potential) is applied.

N-channel current mirror differential amplifier 10 configured as above
In this case, when the sense line potential Vs is at a high level (for example, 4.2 V), the P-channel transistor P3 is completely turned off, and its drain potential (differential amplifier output) quickly reaches the Vsm potential. Since the power level decreases, sufficient Roku level output can be obtained. Furthermore, when the sense line potential V- is at a low level (for example, 2.5 V), the static characteristics of the P-channel transistor P3 have a large slope in the non-saturation region as shown in FIG.
．． 7 V) is obtained. Here, IN4 is the current of transistor N4. In other words, the f-) potential (sense line potential) of the P-channel transistor P3 is at a high level (
4.2 V), the VG-VTI! is Ov
Yes, the dirt potential is low level (the 2.5 V
), VG-v, H is -1,7V -(Vce
-2,5-Vtitp)" (25-O8), a sufficient current difference in the P-channel transistor Ps due to the high level and low level of the sense line potential can be obtained, and its drain potential (differential amplifier output) is at the low level. , a sufficient high-level potential difference (for example, 4.7 V) can be obtained.Moreover, the output potential of the differential amplifier does not depend on the size ratio of the P-channel transistor and the N-channel transistor.

Here, the input/output characteristics of the above-mentioned N-channel current mirror type differential amplifier are shown by solid lines in FIG. 3, and for comparison, the input/output characteristics when a conventional P-channel current mirror type differential amplifier is used. is shown by a dotted line in FIG. As can be seen from this figure, when an N-channel current mirror type is used, the amplitude of the differential amplifier output is larger than when a P-channel current mirror type is used, and the sense line potential (differential amplifier The sense sensitivity to changes in input (input) is also high.

The relationship between the sense line potential and the current of the P-channel transistor P3 of the N-channel current mirror differential amplifier 10 (pentode region) is shown by a solid line in FIG. The current characteristics of the N-channel transistor (N! in FIG. 10) of the current mirror type differential amplifier are shown by dotted lines in FIG. In this figure, the difference between the current mirror load current and the current of the P-channel transistor P3 corresponds to the current that raises or lowers the output of the differential amplifier, and this current difference is the difference between the current mirror load current and the current of the N-channel transistor P3. It can be seen that the difference is almost twice as large as the difference with the current of N1. This corresponds to the fact that the operational delay in the differential amplifier is nearly half as small in the N-channel current mirror type as in the conventional P-channel current mirror.

That is, as mentioned above, the combination of using a P-channel G-D short wall transistor as the sense line load and using an N-channel current mirror type as the CMO8 type O8 amplifier for the sense amplifier is better, and the process margin is large. , it is possible to realize a high-speed cell data readout system with high sensing sensitivity.

It should be noted that the present invention is not limited to the above embodiment, but can also be applied to a CMO8W SRAM as shown in FIG. Here, MC is a static type memory cell, WL
are word lines, BL and BI.

is a bit line, QIIL and QIIL are bit line selection transistors, and 7 is a bit line load.
It is a CMO8 differential amplifier of D-short circuit microtransistor, 101 dN channel current mirror type.

〔Effect of the invention〕

As described above, according to the semiconductor memory of the present invention, the combination of using a P-channel GD short-circuited transistor as the sense line load and using an N-channel current mirror as the OB-type differential amplifier for the sense amplifier, The process margin is large, the sense sensitivity of the sense amplifier is high, and a high-speed cell data read system can be realized.

[Brief explanation of drawings]

FIG. 1 shows a CMO5i EPROM according to an embodiment of the present invention.
2 is a characteristic diagram showing the relationship between the current of the sense line potential input transistor in the differential amplifier in FIG. 1 and the differential amplifier output, and FIG. FIG. 4 is a characteristic diagram showing the relationship between the sense line potential input and the differential amplifier output in the differential amplifier in FIG. , FIG. 5 is a circuit diagram showing a part of a CMOS static memory according to another embodiment of the present invention, FIG. 6 is a diagram showing a general configuration of a cell data reading system of a CMO8 type EFROM, and FIG. A characteristic diagram showing the relationship between the potential of the bit line and the current of the memory cell in FIG.
Fig. 8 is a characteristic diagram showing the relationship between the sense line potential and load current in Fig. 6, and Fig. 9 (&) to (,) show different examples of the sense line load transistors in Fig. 6. Circuit diagram, FIG. 10 is a circuit diagram showing a conventional example of the differential amplifier in FIG. 6,
FIG. 11 is a characteristic diagram showing the relationship between the transistor current and the differential amplifier output in the differential amplifier in FIG. 10, and FIG. 12 is a characteristic diagram showing the relationship between the sense line potential input and the differential amplifier output in the differential amplifier in FIG. It is a characteristic diagram showing a relationship. 1, MC...Memory cell, J,! ',BL,BLi・
... Bit line, QIL * Qmt, ... Bit line selection transistor, 7... Load transistor, 10.
-N channel current mirror type differential amplifier. Applicant's agent Patent attorney Takehiko Suzue Figure 2
Fig. 3 Fig. 4 Fig. 6 V8L V8L Fig. 8 (a) (b) (c) Fig. 9 Fig. 10 Fig. 11

Claims (1)

[Claims] A memory cell, a bit line connected to this memory cell, and a bit line selection M inserted in series with this bit line.
OS transistor and CMO connected to the above bit line
In a semiconductor memory having a sense amplifier consisting of an S-type differential amplifier and a load circuit for the bit line, a P-channel enhancement type transistor whose gate and drain are connected to each other is used as the load circuit, and an N-channel transistor is used as the sense amplifier. A semiconductor memory characterized by using a current mirror differential amplifier.