JPH02130182U - - Google Patents
Info
- Publication number
- JPH02130182U JPH02130182U JP3835689U JP3835689U JPH02130182U JP H02130182 U JPH02130182 U JP H02130182U JP 3835689 U JP3835689 U JP 3835689U JP 3835689 U JP3835689 U JP 3835689U JP H02130182 U JPH02130182 U JP H02130182U
- Authority
- JP
- Japan
- Prior art keywords
- adder
- subtracter
- impedance circuit
- input impedance
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Networks Using Active Elements (AREA)
- Television Signal Processing For Recording (AREA)
Description
第１図はこの考案による周波数特性補償回路の
一実施例の全体の構成を示すブロツク図、第２図
はこの考案の一実施例の要部の構成を示す結線図
、第３図及び第４図はこの考案の一実施例の全体
及び要部の特性を示す線図、第５図はこの考案の
説明のための線図、第６図は従来の周波数特性補
償回路の構成例を示すブロツク図、第７図は従来
の特性を示す線図である。
１０，１０Ｄ……周波数特性補償回路（コサイ
ンイコライザ）、１２……遅延線、１６，１６Ｄ
……可変減衰器、１７……緩衝増幅器である。
FIG. 1 is a block diagram showing the overall configuration of an embodiment of a frequency characteristic compensation circuit according to this invention, FIG. 2 is a wiring diagram showing the structure of the main part of an embodiment of this invention, and FIGS. The figure is a diagram showing the overall characteristics and main parts of an embodiment of this invention, FIG. 5 is a diagram for explaining this invention, and FIG. 6 is a block diagram showing an example of the configuration of a conventional frequency characteristic compensation circuit. 7 are diagrams showing conventional characteristics. 10, 10D... Frequency characteristic compensation circuit (cosine equalizer), 12... Delay line, 16, 16D
. . . variable attenuator, 17 . . . buffer amplifier.
Claims (1)
高入力インピーダンス回路を介して加算器又は減
算器が接続されると共に、上記遅延線の入力端の
反射信号及び入力信号が可変減衰器を介して上記
加算器又は減算器に供給されて成るコサイン特性
の周波数特性補償回路において、 上記可変減衰器と遅延特性及び周波数特性が等
しい緩衝増幅器を上記高入力インピーダンス回路
と上記加算器又は減算器との間に設けたことを特
徴とする周波数特性補償回路。[Claims for Utility Model Registration] An adder or a subtracter is connected to a delay line with a predetermined delay time to which an input signal is supplied via a high input impedance circuit, and a reflected signal at the input end of the delay line and an input In a frequency characteristic compensation circuit having a cosine characteristic in which a signal is supplied to the adder or subtracter via a variable attenuator, a buffer amplifier having delay characteristics and frequency characteristics equal to those of the variable attenuator is connected to the high input impedance circuit and the above-mentioned high input impedance circuit. A frequency characteristic compensation circuit characterized in that it is provided between an adder or a subtracter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989038356U JPH0727737Y2 (en) | 1989-03-31 | 1989-03-31 | Frequency characteristic compensation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989038356U JPH0727737Y2 (en) | 1989-03-31 | 1989-03-31 | Frequency characteristic compensation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02130182U true JPH02130182U (en) | 1990-10-26 |
| JPH0727737Y2 JPH0727737Y2 (en) | 1995-06-21 |
Family
ID=31546287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989038356U Expired - Lifetime JPH0727737Y2 (en) | 1989-03-31 | 1989-03-31 | Frequency characteristic compensation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0727737Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61146010A (en) * | 1984-12-20 | 1986-07-03 | Nec Corp | Variable delay time equalizer |
-
1989
- 1989-03-31 JP JP1989038356U patent/JPH0727737Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61146010A (en) * | 1984-12-20 | 1986-07-03 | Nec Corp | Variable delay time equalizer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0727737Y2 (en) | 1995-06-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |