JPH024366U - - Google Patents
Info
- Publication number
- JPH024366U JPH024366U JP8091088U JP8091088U JPH024366U JP H024366 U JPH024366 U JP H024366U JP 8091088 U JP8091088 U JP 8091088U JP 8091088 U JP8091088 U JP 8091088U JP H024366 U JPH024366 U JP H024366U
- Authority
- JP
- Japan
- Prior art keywords
- delay
- signal
- circuit
- contour correction
- amount
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Picture Signal Circuits (AREA)
Description
第１図乃至第４図は本考案の輪郭補正回路の夫
々第１乃至第４実施例のブロツク構成図、第５図
及び第７図は従来の輪郭補正回路のブロツク構成
図、第６図、第８図及び第９図は各輪郭補正回路
の動作説明用タイミングチヤートである。
３，４……増幅器（減衰器）、５，７，１３…
…加算器、６……利得制御回路、１１……インバ
ータ、１２……バツフア、１７〜２０……輪郭補
正回路、２１〜２３……遅延回路、２４〜２６…
…遅延時間可変型遅延回路、２７……遅延時間コ
ントロール回路。
1 to 4 are block diagrams of the first to fourth embodiments of the contour correction circuit of the present invention, FIGS. 5 and 7 are block diagrams of the conventional contour correction circuit, and FIG. 8 and 9 are timing charts for explaining the operation of each contour correction circuit. 3, 4...Amplifier (attenuator), 5, 7, 13...
...Adder, 6...Gain control circuit, 11...Inverter, 12...Buffer, 17-20...Contour correction circuit, 21-23...Delay circuit, 24-26...
...Delay time variable type delay circuit, 27...Delay time control circuit.
Claims (1)
回路を直列に接続し、該第１の遅延回路の入力信
号及び第２の遅延回路の出力信号を夫々−1/2倍
に増幅した後、該第１の遅延回路の出力信号と加
算して輪郭補正信号を得る構成とした輪郭補正回
路において、上記第１及び第２の遅延回路を、遅
延量を可変し得る同一特性の遅延回路で構成する
と共に、該遅延量を同量ずつ連動して切り換わる
よう構成したことを特徴とする輪郭補正回路。 (2) 入力端側はインピーダンス整合が取られ、
出力端側は終端を開成して全反射の構成とされた
１つの遅延回路を有し、該遅延回路の出力端から
の信号より、該入力端より取出した信号を減算し
て輪郭補正信号を得る構成とした輪郭補正回路に
おいて、上記遅延回路の遅延量を可変し得るよう
構成すると共に、該遅延量の変化を外部より制御
し得るよう構成したことを特徴とする輪郭補正回
路。[Claims for Utility Model Registration] (1) First and second delay circuits having the same delay amount are connected in series, and the input signal of the first delay circuit and the output signal of the second delay circuit are connected in series. In the contour correction circuit configured to obtain a contour correction signal by amplifying the output signal by -1/2 and then adding it to the output signal of the first delay circuit, the first and second delay circuits are connected to What is claimed is: 1. A contour correction circuit comprising variable delay circuits having the same characteristics, and configured to switch the delay amount by the same amount. (2) Impedance matching is done on the input end side,
The output end side has one delay circuit whose termination is open and has a total reflection configuration, and the signal taken out from the input end is subtracted from the signal from the output end of the delay circuit to generate a contour correction signal. 1. A contour correction circuit having a configuration in which the delay amount of the delay circuit can be varied, and the change in the delay amount can be controlled from the outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8091088U JPH024366U (en) | 1988-06-17 | 1988-06-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8091088U JPH024366U (en) | 1988-06-17 | 1988-06-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH024366U true JPH024366U (en) | 1990-01-11 |
Family
ID=31305723
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8091088U Pending JPH024366U (en) | 1988-06-17 | 1988-06-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH024366U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08298602A (en) * | 1995-04-26 | 1996-11-12 | Nec Corp | Digital contour compensating device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5637568B2 (en) * | 1976-11-01 | 1981-09-01 | ||
| JPS5990472A (en) * | 1982-10-09 | 1984-05-24 | アイテイ−テイ−・インダストリ−ズ・インコ−ポレ−テツド | Intensity signal integrated digital filter |
| JPS6327167A (en) * | 1986-07-21 | 1988-02-04 | Victor Co Of Japan Ltd | Contour compensation circuit |
-
1988
- 1988-06-17 JP JP8091088U patent/JPH024366U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5637568B2 (en) * | 1976-11-01 | 1981-09-01 | ||
| JPS5990472A (en) * | 1982-10-09 | 1984-05-24 | アイテイ−テイ−・インダストリ−ズ・インコ−ポレ−テツド | Intensity signal integrated digital filter |
| JPS6327167A (en) * | 1986-07-21 | 1988-02-04 | Victor Co Of Japan Ltd | Contour compensation circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08298602A (en) * | 1995-04-26 | 1996-11-12 | Nec Corp | Digital contour compensating device |
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