JPH0727737Y2 - Frequency characteristic compensation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a frequency characteristic compensating circuit suitable for FM signals.

[Outline of device]

This invention is a cosine equalizer in which an input signal and an output signal of a variable attenuator supplied by superimposing a reflection signal of a delay line having a predetermined delay time and a main line signal output from a delay line are added or subtracted, By inserting a buffer whose delay characteristic and frequency characteristic are the same as those of the variable attenuator on the main line side, variations in the delay of the equalizer output signal due to changes in the attenuation amount of the variable attenuator are eliminated.

[Conventional technology]

In a general VTR, a luminance signal is recorded on a tape in the form of a low carrier FM signal and reproduced. In the head output obtained in this recording / reproducing process, the amplitude of the lower sideband is larger than that of the upper sideband,
It is asymmetric with respect to the carrier. When such an FM signal passes through a so-called cosine equalizer, which is a cosine-type amplitude frequency characteristic (cosine characteristic) with no phase distortion as shown in FIG. 5, the upper and lower sidebands are symmetrically demodulated. The signal waveform is improved.

The conventional cosine equalizer is basically constructed as shown in FIG.

In FIG. 6, (10) shows the whole of the equalizer, and the FM luminance signal Y _FM applied to the input terminal is delayed by the delay line (12) with the delay time τ via the matching resistor (11).
Is supplied to. The output terminal of the delay line (12) is connected to a high input impedance amplifier (13) such as an emitter follower and is substantially open. Therefore, the supplied FM luminance signal is reflected with the same amplitude and the same phase, and is absorbed by the matching resistor (11) at the input end of the delay line (12).

The signal at the output end of the delay line (12) is supplied to the subtractor (14) through the amplifier (13), and the signal at the input end of the delay line (12) is supplied to the amplifier (15) and the high input impedance It is supplied to a subtractor (14) via a voltage-controlled variable attenuator (16).

The basic operation of the conventional example of FIG. 6 is as follows.

When the input signal Sin is expressed by the following equation (1), the signal Sd delayed by the delay line (12) and the reflected signal Sri reaching the input end of the delay line (12) are given by equation (2) and It is expressed as in equation (3).

Sin = Aexp {jωt} (1) Sd = Aexp {jω (t + τ)} (2) Sri = Aexp {jω (t + 2τ)} (3) The reflected signal Sri and the input signal Sin are superimposed. The signal Ss
It is expressed as the following equation (4) and is supplied to the amplifier (15).

Ss = Sin + Sri = Aexp {jω (t + τ)} × [exp {-jωτ} + exp {jωτ}] = 2Acos ωτ exp {jω (t + τ)} (4) In the variable attenuator (16), this signal Ss is k times (k1 /
2) and the attenuation signal S as expressed by the following equation (5)
You get a.

Sa = 2kAcos ωτ exp {jω (t + τ)} (5) In the subtractor (14), the attenuated signal Sa is subtracted from the delayed signal Sd, and the output signal Sout represented by the following equation (6) is obtained. Is obtained.

Sout = Sd−Sa = A (1-2kcos ωτ) exp {jω (t + τ)} (6) The amplitude frequency characteristic of the output signal Sout is as shown in FIG.
Further, as is clear from the equation (6), the output signal Sout is delayed by τ time with respect to the input signal Sin, but there is no phase distortion at all.

Incidentally, in FIG. 6, when an adder is used in place of the subtractor (14), as can be easily understood from the equation (6),
A cosine characteristic having a phase opposite to that of the characteristic shown in FIG. 5 can be obtained. Such a cosine equalizer is used, for example, for compensating the differential gain (DG) due to the characteristics of the magnetic head.

[Problems to be solved by the device]

By the way, in the analysis of the operation of the above-mentioned cosine equalizer (10), the voltage control type variable attenuator (16) simply controls only the signal amplitude.

However, in reality, since there are delay and frequency characteristics due to the electronic circuit inside the attenuator, in an actual cosine equalizer, for example, as shown in FIG.
There was a problem that the delay time of the output signal of the equalizer fluctuated significantly with the change of the attenuation coefficient of 6), and the phase distortion occurred after demodulating the FM signal.

In view of such a point, an object of the present invention is to provide a frequency characteristic compensating circuit capable of eliminating the adverse effect of the internal delay of the variable attenuator and performing the original characteristic compensation without fluctuation of the delay time.

[Means for Solving the Problems]

This invention comprises a delay line 12 to which an input signal is supplied and delays the input signal by a predetermined delay time τ, and a high input impedance circuit 13 to which an output signal of the delay line 12 is supplied.
And a variable attenuator 16D to which the reflected signal output from the input end of the delay line 12 and the input signal are supplied.
, And an adder or subtractor 14 to which the output of the first signal path is supplied to one input end and the output of the second signal path is supplied to the other input end. In the characteristic frequency characteristic compensating circuit, a buffer amplifier 17 having the same delay characteristic and frequency characteristic as the variable attenuator 16D is provided between the high input impedance circuit 13 and the adder or subtractor 14 in the first signal path. Is a frequency characteristic compensating circuit.

[Action]

According to this invention, fluctuations in the delay of the equalizer output signal due to changes in the amount of attenuation of the variable attenuator are eliminated.

〔Example〕

An embodiment of the frequency characteristic compensating circuit according to the present invention will be described below with reference to FIGS.

The overall construction of an embodiment of the present invention is shown in FIG. 1, and the construction of the essential parts thereof is shown in FIG. In FIG. 1, parts corresponding to those in FIG. 6 described above are designated by the same reference numerals to omit redundant description.

In FIG. 1, (10D) shows the cosine equalizer according to the present invention as a whole, and includes an amplifier (13) and a subtractor (1
A buffer amplifier (buffer) (17) is provided between the subtracter (14) and the amplifier (15), and a voltage-controlled variable attenuator (16D) is provided between the subtractor (14) and the amplifier (15). The remaining structure is the same as that shown in FIG.

This variable attenuator (16D) has delay and frequency characteristics due to an internal electronic circuit as shown in FIG. 2, and its transfer function is expressed by the following equation (7).

F (ω) = k · f (ω) exp {jωτ ₁₆ } (7) Similarly, the buffer (17) also has delay and frequency characteristics due to the internal electronic circuit, and its transfer function is (8) ) Is expressed as

G (ω) = g (ω) exp {jωτ ₁₇ } (8) The delayed signal Sa of the above formula (2) is supplied to the buffer (17), and the superimposed signal Ss of the formula (4) is variable attenuator. The signals Sdd and Sad as represented by the following equations (9) and (10) are obtained from the buffer (17) and the variable attenuator (16D) supplied to (16D).

Sdd = Sd · G (ω) = A · g (ω) exp {jω (t + τ + τ 17)} ‥‥
(9) Sad = Ss · F (ω) = 2kAcos ωτ · f (ω) × exp {jω (t + τ + τ ₁₆ )} (10) In the subtractor (14), the difference between both signals Sdd and Sad is taken. The output signal Sou of the cosine equalizer (10D) shown in FIG.
t is expressed by the following equation (11).

As is apparent from the equation (11), in the case of τ ₁₆ = τ ₁₇ = τΔ (12), exp {jω (τ ₁₆ −τ ₁₇ )} → 1 and further f (ω) = g ( If ω) = h (ω) (13), that is, if the delay and frequency characteristics of the buffer (17) are equal to those of the variable attenuator (16D), the equation (11) is simplified as follows. To be done.

Sout = A (1−2kcos ωτ) h (ω) × exp {jω (t + τ + τΔ)} (14) Comparing this equation (14) with the ideal cosine characteristic of the above equation (6), The cosine equalizer (10D) in Fig. 1 deviates from the ideal characteristic by the delay component τΔ of the variable attenuator (16D), and the variable attenuator (16D) frequency characteristic component k (ω).
Since it has a doubled cosine characteristic, even if the attenuation coefficient k of the variable attenuator (16D) is changed, as shown in FIG. Absent.

As shown in the equations (12) and (13), the delay and frequency characteristics of the variable attenuator (16D) and the buffer (17) are made equal to each other. Therefore, in this embodiment, the variable attenuator (16D) is used. For both the buffer and the buffer (17), for example, a 4-quadrant multiplier as shown in FIG. 2 is used.

In the circuit of FIG. 2, when Rx >> kT / qIx, Ry >> kT / qIy, the following equation must hold between the input voltage Vx and Vy of the terminals Xin and Yin and the output voltage Vz of the terminal Zout. It has been known.

In the case of the variable attenuator (16D), the superimposed signal Ss is supplied to one input terminal Xin, and the variable DC voltage is supplied to the other input terminal Yin as a control signal to control the attenuation degree (k). It

In case of buffer (17), delay signal S
d is supplied, and the fixed DC voltage is supplied to the other input terminal Yin via the resistance voltage divider RD, and the attenuation is fixed to zero, that is, the gain is fixed to 1.

In this way, since the variable attenuator (16D) and the buffer (17) have the same circuit configuration, both delay characteristics and frequency characteristics become equal, as shown in FIG.

In addition, in FIG. 4, Ssout is an emitter follower (15).
Shows the delay characteristic only, and Sad / Sdd shows the total delay characteristic of the emitter follower and the attenuator (16D) or the buffer (17).

In addition, in this embodiment, the variable attenuator (16D) and the buffer (17) are integrated on the same semiconductor substrate to prevent the change of the equalizer characteristic due to the temperature change.

[Effect of device]

As described above in detail, according to the present invention, the output signal of the variable attenuator to which the input signal and the reflection signal of the delay line having the predetermined delay time are superimposed and supplied, and the main line signal output from the delay line are provided. In the frequency characteristic compensating circuit of the cosine characteristic that is added or subtracted, the buffer whose delay characteristic and frequency characteristic are the same as those of the variable attenuator is inserted on the main line side. A frequency characteristic compensating circuit capable of removing fluctuations in signal delay can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall construction of an embodiment of the frequency characteristic compensating circuit according to the present invention, and FIG. 2 is a connection diagram showing the construction of the essential parts of an embodiment of the present invention, FIGS. The figure is a diagram showing the characteristics of the whole and essential parts of one embodiment of the present invention,
FIG. 5 is a diagram for explaining the present invention, FIG. 6 is a block diagram showing a configuration example of a conventional frequency characteristic compensation circuit, and FIG. 7 is a diagram showing conventional characteristics. (10) and (10D) are frequency characteristic compensation circuits (cosine equalizers), (12) is a delay line, (16) and (16D) are variable attenuators, and (17) is a buffer amplifier.

Claims (1)

[Scope of utility model registration request] 1. A first input circuit comprising: a delay line supplied with an input signal to delay the input signal by a predetermined delay time; and a high input impedance circuit supplied with an output signal of the delay line.
Signal path, a second signal path formed of a variable attenuator to which the reflected signal output from the input end of the delay line and the input signal are supplied, and the output of the first signal path has one input end. In the frequency characteristic compensating circuit having a cosine characteristic, the frequency characteristic compensating circuit having an adder or a subtracter having an output of the second signal path supplied to the other input end of the variable attenuator, the delay characteristic and the frequency. A frequency characteristic compensating circuit, characterized in that a buffer amplifier having the same characteristic is provided between the high input impedance circuit and the adder or subtractor in the first signal path.