JPH0212833A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0212833A JPH0212833A JP16321788A JP16321788A JPH0212833A JP H0212833 A JPH0212833 A JP H0212833A JP 16321788 A JP16321788 A JP 16321788A JP 16321788 A JP16321788 A JP 16321788A JP H0212833 A JPH0212833 A JP H0212833A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- semiconductor layer
- film
- polycrystalline semiconductor
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 81
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 40
- 230000004888 barrier function Effects 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 15
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 10
- 239000000956 alloy Substances 0.000 claims abstract description 10
- 238000002844 melting Methods 0.000 claims description 7
- 230000008018 melting Effects 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 abstract description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 239000012535 impurity Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 239000012808 vapor phase Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に半導体基板
上に、多結晶半導体層及び金属膜より成る第１の電極と
、高融点金属と金属膜より成る第２の電極を有する半導
体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular, a first electrode made of a polycrystalline semiconductor layer and a metal film, a high melting point metal, and a metal film, on a semiconductor substrate. The present invention relates to a method of manufacturing a semiconductor device having a second electrode made of a film.
近年における半導体集積回路装置は、高速化。 In recent years, semiconductor integrated circuit devices have become faster.
高性能化を図るために、種々の素子を同一の半導体基板
内に形成している。In order to improve performance, various elements are formed within the same semiconductor substrate.
例えば、ＴＴＬ回路、を用する半導体装置では、ＮＰＮ
）ランジスタ、ＰＮＰトランジスタの他に、回路のスイ
ッチング時間を速くするために、第３図に示すようにバ
イポーラトランジスタに接続されるショットキーバリア
ダイオード（以後ＳＢＤと略す）を一体的に形成してい
る。For example, in a semiconductor device using a TTL circuit, NPN
) In addition to transistors and PNP transistors, in order to speed up the switching time of the circuit, a Schottky barrier diode (hereinafter abbreviated as SBD) connected to a bipolar transistor is integrally formed as shown in Figure 3. .
第４図（ａ）乃至第４図（ｅ）は、この種の半導体装置
を製造工程順に示す断面図である。FIGS. 4(a) to 4(e) are cross-sectional views showing this type of semiconductor device in the order of manufacturing steps.
即ち、第４図（ａ）のように、Ｐ型半導体基板１上の素
子領域に、ｎ型埋込層２を形成し、その周辺にｐ型埋込
層３を形成し、全面にｎ型エピタキシャル層４を形成す
る。そして、選択酸化技術を用いて、ｐ型埋込層３に達
するシリコン酸化膜から成るフィールド絶縁膜５を形成
する。また、素子領域のエピタキシャル層表面上に１０
００〜３０００人程度の酸化シリ形成膜６を第１の絶縁
膜として形成する。That is, as shown in FIG. 4(a), an n-type buried layer 2 is formed in the element region on a P-type semiconductor substrate 1, a p-type buried layer 3 is formed around it, and an n-type layer is formed on the entire surface. An epitaxial layer 4 is formed. Then, a field insulating film 5 made of a silicon oxide film reaching the p-type buried layer 3 is formed using a selective oxidation technique. In addition, 10
A silicon oxide formation film 6 having a thickness of about 0.00 to 3000 is formed as a first insulating film.
次に、第４図（ｂ）のように、前記酸化シリコン膜６を
介してｐ型不純物原子を選択的にイオン注入してベース
層７を形成し、更にベース開孔部を形成する領域に高濃
度のｐ型不純物原子をイオン注入する。そして、前記酸
化シリコン膜６に選択的に開孔してコレクタ及びエミッ
タの開孔部を形成し、エピタキシャル層４の表面を露出
させる。Next, as shown in FIG. 4(b), p-type impurity atoms are selectively ion-implanted through the silicon oxide film 6 to form a base layer 7, and further into the region where the base opening is to be formed. A high concentration of p-type impurity atoms is ion-implanted. Then, holes are selectively opened in the silicon oxide film 6 to form collector and emitter openings, and the surface of the epitaxial layer 4 is exposed.
更に、前記エミッタ及びコレクタ開孔部を含む全面に多
結晶半導体層９を形成し、この多結晶半導体層９からｎ
型不純物を添加してエミッタ１０を形成する。Furthermore, a polycrystalline semiconductor layer 9 is formed on the entire surface including the emitter and collector openings, and from this polycrystalline semiconductor layer 9 n
Emitter 10 is formed by adding type impurities.
次に、第４図（Ｃ）のように、ベース及びＳＢＤ領域と
それらの周囲の多結晶半導体層９を選択的に除去し、続
いて多結晶半導体層９の表面を覆うように１０００〜２
０００人程度の気相成長形成シリコン膜１２を第２の絶
縁膜として形成する。Next, as shown in FIG. 4C, the base and SBD regions and the polycrystalline semiconductor layer 9 around them are selectively removed, and then the
A silicon film 12 of about 1,000 yen is formed by vapor phase growth as a second insulating film.
その後、第４図（ｄ）のように、気相成長酸化シリコン
膜１２及び酸化シリコン膜６を選択的に除去してベース
及びＳＢＤ開孔部を形成する。そして、白金等の高融点
金属を被着した後、熱処理をしてベース及びＳＢＤ開孔
部のエピタキシャル層表面部のみに白金とシリコンのシ
リサイド合金膜１３を形成する。これにより、シリサイ
ド合金膜１３とｎ型エピタキシャル層４の接合部にＳＢ
Ｄが構成され、シリサイド合金膜１３を介してベースＮ
７に接続される。次いで、前記ベース及びＳＢＤ開孔部
にバリア金属膜１４を選択的に形成する。Thereafter, as shown in FIG. 4(d), the vapor phase grown silicon oxide film 12 and the silicon oxide film 6 are selectively removed to form a base and an SBD opening. After depositing a high melting point metal such as platinum, heat treatment is performed to form a silicide alloy film 13 of platinum and silicon only on the base and the surface of the epitaxial layer in the SBD opening. As a result, SB is formed at the junction between the silicide alloy film 13 and the n-type epitaxial layer 4.
D is formed, and the base N is formed through the silicide alloy film 13.
Connected to 7. Next, a barrier metal film 14 is selectively formed on the base and the SBD opening.
その後、第４図（ｅ）のように、気相成長酸化シリコン
膜１２を選択的に除去した上で半導体基板１の全面に低
導電率の金属膜、例えばアルミニウム１５を被着し、こ
の金属膜１５及び前記多結晶半導体Ｎ９を同時に選択エ
ツチングする。これにより、コレクタ及びエミッタ開孔
部には多結晶半導体層９及びアルミニウム１５から成る
第１の電極構造が形成され、ベース及びＳＢＤ開孔部は
バリア金属膜１４とアルミニウム１５から成る第２の電
極構造が形成され、これら２種の電極構造を有する半導
体装置が完成される。Thereafter, as shown in FIG. 4(e), after selectively removing the vapor-phase grown silicon oxide film 12, a metal film of low conductivity, for example, aluminum 15, is deposited on the entire surface of the semiconductor substrate 1. The film 15 and the polycrystalline semiconductor N9 are selectively etched at the same time. As a result, a first electrode structure made of the polycrystalline semiconductor layer 9 and aluminum 15 is formed in the collector and emitter openings, and a second electrode structure made of the barrier metal film 14 and aluminum 15 is formed in the base and SBD openings. A structure is formed, and a semiconductor device having these two types of electrode structures is completed.
［発明が解決しようとする課題］
上述した従来の半導体装置の製造方法では、ベース及び
ＳＢＤ開孔部を形成するに際しては、多結晶半導体層９
を形成した後にベース及びＳＢＤ開孔部となる領域の多
結晶半導体層９を除去する第１の工程と、多結晶半導体
層９を含む全面に第２の絶縁膜１２を形成した後に、こ
の第２の絶縁ｖ、１２と第１の絶縁膜６を除去する第２
の工程とを必要としている。このため、半導体装置の製
造工程数が多（なり、製造が煩雑になるとともに製造コ
ストも高くなるという問題があった。[Problems to be Solved by the Invention] In the conventional semiconductor device manufacturing method described above, when forming the base and the SBD opening, the polycrystalline semiconductor layer 9
After forming the polycrystalline semiconductor layer 9, the polycrystalline semiconductor layer 9 in the region that will become the base and the SBD opening is removed. After forming the second insulating film 12 on the entire surface including the polycrystalline semiconductor layer 9, 2 to remove the insulation v, 12 and the first insulation film 6;
process. For this reason, there are problems in that the number of manufacturing steps for the semiconductor device is large, making the manufacturing complicated and increasing the manufacturing cost.
また、第４図（ｄ）の工程ではベース、ＳＢＤ開孔部及
びその周囲にバリア金属１４を選択的に形成しているが
、このとき多結晶半導体層９上の第２の絶縁膜１２は例
えば弗酸を用いてエツチングを行っている。そして、こ
の場合に第２の絶縁膜を完全に除去するためには、１分
〜２分オーバーエツチングする必要があり、このときに
多結晶半導体Ｎ９で覆われてない領域、つまりベース及
びＳＢＤ開孔部周囲の第２の絶縁膜１２も同時に除去さ
れてしまうことがある。Further, in the step of FIG. 4(d), the barrier metal 14 is selectively formed on the base, the SBD opening and its surroundings, but at this time, the second insulating film 12 on the polycrystalline semiconductor layer 9 is For example, etching is performed using hydrofluoric acid. In this case, in order to completely remove the second insulating film, it is necessary to over-etch for 1 to 2 minutes, and at this time, the areas not covered with the polycrystalline semiconductor N9, that is, the base and SBD openings, are removed. The second insulating film 12 around the hole may also be removed at the same time.
これにより、第５図（ａ）に示すように、へ−ス及びＳ
ＢＤ開孔部の周囲の部分１６で半導体基板１のシリコン
面が露出してしまうことがある。As a result, as shown in FIG. 5(a), the base and S
The silicon surface of the semiconductor substrate 1 may be exposed in the area 16 around the BD opening.
したがって、このような状態で全面にアルミニウム被着
後、選択エツチングしてコレクタ、エミッタ、ベース及
びＳＢＤの電極を形成する工程を行うと、第５図（ｂ）
に示すように、アルミニウム１５が部分１６でシリコン
面に接続され、ベースとコレクタ間が短絡してしまう。Therefore, if aluminum is deposited on the entire surface under such conditions and then selectively etched to form the collector, emitter, base, and SBD electrodes, the result shown in FIG. 5(b) is performed.
As shown in FIG. 2, the aluminum 15 is connected to the silicon surface at a portion 16, resulting in a short circuit between the base and the collector.
このため、半導体装置の歩留り低下を招くとともに、信
頼性が低下されるという問題が生じる。This causes problems in that the yield of semiconductor devices is lowered and reliability is lowered.
本発明は上述した工程の簡略化を図るとともに、アルミ
ニウム電極における短絡を防止することが可能な半導体
装置の製造方法を提供することを目的としている。An object of the present invention is to provide a method for manufacturing a semiconductor device that can simplify the above-mentioned steps and prevent short circuits in aluminum electrodes.
本発明の半導体装置の製造方法は、半導体基板上を覆う
第１の絶縁膜に第１の電極を形成するための第１の開孔
部を形成する工程と、この第１の開孔部を含む半導体基
板上全面に多結晶半導体層と第２の絶縁膜を順次堆積す
る工程と、これら第２の絶縁膜、多結晶半導体層及び前
記第１の絶縁膜を第１の開孔部と異なる領域において順
次選択エツチングして第２の電極を形成するための第２
の開孔部を形成する工程と、前記第２の開孔部内の半導
体基板表面上にシリサイド合金膜を形成する工程と、前
記第２の開孔部を覆うようにバリア金属膜を選択的に形
成する工程と、このバリア金属膜をマスクにして前記多
結晶半導体層上の第２の絶縁膜を除去する工程と、全面
に金属膜を被着し、これを前記第１の開孔部及び第２の
開孔部に残すように前記多結晶半導体層とともに選択的
にエツチングする工程とを含んでいる。The method for manufacturing a semiconductor device of the present invention includes a step of forming a first opening for forming a first electrode in a first insulating film covering a semiconductor substrate, and a step of forming a first opening for forming a first electrode. a step of sequentially depositing a polycrystalline semiconductor layer and a second insulating film over the entire surface of the semiconductor substrate including the second insulating film, the polycrystalline semiconductor layer, and the first insulating film different from the first opening portion; a second electrode for forming a second electrode by sequentially selectively etching the regions;
forming a silicide alloy film on the surface of the semiconductor substrate within the second opening, and selectively forming a barrier metal film to cover the second opening. a step of removing a second insulating film on the polycrystalline semiconductor layer using the barrier metal film as a mask, and depositing a metal film on the entire surface of the polycrystalline semiconductor layer, and depositing the metal film on the first opening and the second insulating film on the polycrystalline semiconductor layer. and selectively etching the polycrystalline semiconductor layer together with the polycrystalline semiconductor layer so as to leave it in the second opening.
［作用］
上述した方法では、第２の開孔部を開孔するに際しては
、第２の絶縁膜、多結晶半導体層及び第１の絶縁膜を同
時に１の工程でエツチングすればよい。また、第２の絶
縁膜のエツチングに際しては、第１の絶縁膜は多結晶半
導体層及びバリア金属で完全に覆われることになり、第
２の絶縁膜のエツチング時間が過多になっても、第１の
絶縁膜がエツチングされることがな（、金属膜を形成し
た際にも短絡が生じることはない。[Operation] In the method described above, when forming the second opening, the second insulating film, the polycrystalline semiconductor layer, and the first insulating film may be etched simultaneously in one step. Furthermore, when etching the second insulating film, the first insulating film is completely covered with the polycrystalline semiconductor layer and the barrier metal, so even if the etching time of the second insulating film is too long, the first insulating film is completely covered with the polycrystalline semiconductor layer and the barrier metal. The first insulating film will not be etched (and no short circuit will occur when a metal film is formed).
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）乃至第１図（Ｃ）は本発明の第１実施例の
主要工程を示す断面図である。なお、第４図（ｂ）に示
す状態までは、これまでと同様の工程で製造を行ってお
り、その説明は省略する。FIG. 1(a) to FIG. 1(C) are sectional views showing the main steps of the first embodiment of the present invention. Incidentally, up to the state shown in FIG. 4(b), manufacturing is performed using the same steps as before, and the explanation thereof will be omitted.
第４図（ｂ）の構造まで工程が進められた後、第１図（
ａ）のように、全面に第２の絶縁膜としての気相成長酸
化シリコン膜１２を形成後、フォトリソグラフィ技術を
用いてベース及びＳＢＤの開孔部のフォトレジストパタ
ーンを形成し、これをマスクとした異方性エツチングに
より、第２の絶縁膜１２．多結晶半導体１９．第１の絶
縁膜６を順次エツチングして半導体基板１のシリコン面
を露出させる。After the process has proceeded to the structure shown in Fig. 4(b), the structure shown in Fig. 1(b) is completed.
As shown in a), after forming a vapor phase grown silicon oxide film 12 as a second insulating film on the entire surface, a photoresist pattern for the base and SBD openings is formed using photolithography technology, and this is masked. By anisotropic etching, the second insulating film 12. Polycrystalline semiconductor 19. The first insulating film 6 is sequentially etched to expose the silicon surface of the semiconductor substrate 1.
次に、前記フォトレジストパターンを除去した後、第１
図（ｂ）のように、全面に白金等の高融点金属を被着後
、熱処理してベース及びＳＢＤの開孔部に露出している
シリコン面及び多結晶半導体層９の側壁面に夫々シリサ
イド膜１３を形成する。なお、第１及び第２の絶縁膜上
の高融点金属は除去する。更に、ベース及びＳＢＤ開孔
部を含むその周囲にバリア金属１４を選択的に形成する
。Next, after removing the photoresist pattern, the first
As shown in Figure (b), after coating a high melting point metal such as platinum on the entire surface, heat treatment is performed to silicide the silicon surface exposed to the base and the opening of the SBD, and the side wall surface of the polycrystalline semiconductor layer 9, respectively. A film 13 is formed. Note that the high melting point metal on the first and second insulating films is removed. Further, a barrier metal 14 is selectively formed around the base and the SBD opening.
しかる上で、第２の絶縁膜１２をエツチング除去する。After that, the second insulating film 12 is removed by etching.
次に、第１図（Ｃ）のように、全面にアルミニウム１５
を被着し、このアルミニウム１５及び多結晶半導体層９
を同時に選択エツチングし、エミッタ、コレクタ、ベー
ス及びＳＢＤの電極を形成する。Next, as shown in Figure 1(C), aluminum 15
This aluminum 15 and polycrystalline semiconductor layer 9
are simultaneously selectively etched to form emitter, collector, base and SBD electrodes.
したがって、この製造方法では、ベース及びＳＢＤ開孔
部を開孔するに際しては、多結晶半導体層９上に第２の
絶縁膜１２を形成した後に、これら第２の絶縁膜１２．
多結晶半導体層９及び第１の絶縁膜６を同一工程で順次
エツチングすればよく、従来の２工程に対して１工程で
済み、半導体装置の製造工程数を低減し、かつ製造コス
トも低減できる。Therefore, in this manufacturing method, when forming the base and SBD openings, after forming the second insulating film 12 on the polycrystalline semiconductor layer 9, the second insulating film 12.
It is sufficient to sequentially etch the polycrystalline semiconductor layer 9 and the first insulating film 6 in the same process, which requires only one process instead of the conventional two processes, reducing the number of manufacturing processes for semiconductor devices and reducing manufacturing costs. .
また、バリア金属１４の形成後に第２の絶縁膜１２をエ
ツチングしているが、このとき第１の絶縁膜６は多結晶
半導体層９及びバリア金属１４で完全に覆われているた
め、第２の絶縁膜１２をエツチングする際のエツチング
時間が過多になっても、第１の絶縁膜６をエツチングす
ることがなく、アルミニウム１５を形成した際の短絡を
防止して半導体装置の歩留り及び信頼性を改善する。Further, the second insulating film 12 is etched after the barrier metal 14 is formed, but at this time, since the first insulating film 6 is completely covered with the polycrystalline semiconductor layer 9 and the barrier metal 14, the second insulating film 12 is etched. Even if the etching time is too long when etching the first insulating film 12, the first insulating film 6 is not etched, and short circuits are prevented when the aluminum 15 is formed, thereby increasing the yield and reliability of the semiconductor device. improve.
第２図（ａ）乃至第２図（Ｃ）は本発明の第２実施例の
主要工程の断面図であり、第１実施例と同様に第４図（
ｂ）以下の工程のみを示している。FIG. 2(a) to FIG. 2(C) are sectional views of the main steps of the second embodiment of the present invention, and like the first embodiment, FIG.
b) Only the following steps are shown.
先ず、第４図（ｂ）の工程の終了後に、第２図（ａ）の
ように、全面に第２の絶縁膜１２を形成し、この上にベ
ース及びＳＢＤ開孔部を形成する為に選択的にフォトレ
ジストパターン１７を形成する。そして、このフォトレ
ジストパターン１７をマスクにした等方性のエツチング
を行い、第２の絶縁膜１２及び多結晶半導体層９をエツ
チングする。このとき、これらはフォ１−レジストパタ
ーン１７の開孔寸法よりも横方向に若干大きくなるよう
にエツチングされる。また、このフォトレジストパター
ン１７を利用して異方性エツチングにより第１の絶縁膜
６をエツチングし、半導体基板１のシリコン面を露出さ
せる。First, after completing the process shown in FIG. 4(b), as shown in FIG. 2(a), a second insulating film 12 is formed on the entire surface, and a base and an SBD opening are formed on this. A photoresist pattern 17 is selectively formed. Then, isotropic etching is performed using this photoresist pattern 17 as a mask, and the second insulating film 12 and polycrystalline semiconductor layer 9 are etched. At this time, these are etched so that they are slightly larger in the lateral direction than the opening size of the photoresist pattern 17. Further, the first insulating film 6 is etched by anisotropic etching using this photoresist pattern 17 to expose the silicon surface of the semiconductor substrate 1.
次に、フォトレジストパターン１７を除去した後、全面
に高融点金属被着後、熱処理してベース及びＳＢＤ開孔
部の露出したシリコン面及び多結晶半導体層の側壁部に
、第２図（ｂ）のようにシリサイド合金膜１３を形成す
る。その後、第１及び第２の絶縁膜上の高融点金属膜は
除去する。Next, after removing the photoresist pattern 17, a high melting point metal is deposited on the entire surface, and heat treatment is applied to the exposed silicon surface of the base and SBD opening and the side wall of the polycrystalline semiconductor layer as shown in FIG. ) A silicide alloy film 13 is formed as shown in FIG. After that, the high melting point metal film on the first and second insulating films is removed.
更に、シリサイド合金膜１３を形成したベース及びＳＢ
Ｄ開孔部を含み、かつ多結晶半導体層９に覆われていな
い領域の第１の絶縁膜６を覆うようにバリア金属膜１４
を選択的に形成する。Furthermore, the base and SB on which the silicide alloy film 13 is formed
A barrier metal film 14 is formed so as to cover the first insulating film 6 in the region including the D opening and not covered by the polycrystalline semiconductor layer 9.
selectively formed.
その後、第２図（Ｃ）のように、第２の絶縁膜１２を除
去し、アルミニウム１５を被着した上でアルミニウム１
５と多結晶半導体層９を同時に選択エツチングして、コ
レクタ、エミッタ、ベース。Thereafter, as shown in FIG. 2(C), the second insulating film 12 is removed, aluminum 15 is deposited, and aluminum 1
5 and the polycrystalline semiconductor layer 9 are selectively etched at the same time to form a collector, emitter, and base.
及びＳＢＤの電極を形成する。and forming the electrodes of the SBD.
この第２の実施例においても、ベース及びＳＢＤ開孔部
の開孔を１工程で形成することができ、工数を低減でき
る。また、第２の絶縁膜１２のエツチングに際しても、
第１の絶縁膜６は、多結晶半導体層６及びバリア金属膜
１４で覆われているので第１の絶縁膜６がエツチングさ
れることはない。Also in this second embodiment, the base and the openings of the SBD openings can be formed in one step, and the number of steps can be reduced. Also, when etching the second insulating film 12,
Since the first insulating film 6 is covered with the polycrystalline semiconductor layer 6 and the barrier metal film 14, the first insulating film 6 is not etched.
［発明の効果］
以上説明したように本発明は、第２の開孔部を開孔する
に際しては、第２の絶縁膜、多結晶半導体層及び第１の
絶縁膜を同時に１の工程でエツチングすることができる
ので、従来の２工程に比較して工程数を低減でき、半導
体装置の製造を容易にしかつ製造コストを低減できる。[Effects of the Invention] As explained above, the present invention etches the second insulating film, the polycrystalline semiconductor layer, and the first insulating film simultaneously in one step when forming the second opening. Therefore, the number of steps can be reduced compared to the conventional two steps, making it easier to manufacture semiconductor devices and reducing manufacturing costs.
また、第２の絶縁膜のエツチングに際しては、第１の絶
縁膜は多結晶半導体層及びバリア金属で完全に覆われる
ので、第２の絶縁膜のエツチング時間が過多になっても
第１の絶縁膜がエツチングされることはなく、金属膜に
よる短絡を防止して半導体装置の歩留り及び信頼性を太
き（向上することができる。Furthermore, when etching the second insulating film, the first insulating film is completely covered with the polycrystalline semiconductor layer and the barrier metal, so even if the etching time of the second insulating film is too long, the first insulating film is completely covered with the polycrystalline semiconductor layer and the barrier metal. The film is not etched, and short circuits caused by the metal film can be prevented, thereby increasing the yield and reliability of semiconductor devices.
第１図（ａ）乃至第１図（ｃ）は本発明の第１実施例の
主要工程を示す断面図、第２図（ａ）乃至第２図（Ｃ）
は本発明の第２実施例の主要工程を示す断面図、第３図
はバイポーラトランジスタとＳＢＤを接続した構成の回
路図、第４図（ａ）乃至第４図（ｅ）は従来の製造方法
の一例を工程順に示す断面図、第５図（ａ）及び第５図
（ｂ）は従来における問題点を説明するための断面図で
ある。
１・・・ｐ型半導体基板、２・・・ｎ型埋込層、３・・
・ｐ型埋込層、４・・・ｎ型エピタキシャル層、５・・
・フィールド絶縁膜、６・・・酸化シリコン膜（第１の
絶縁膜）７・・・ベース層、８・・・高濃度不純物領域
、９・・・多結晶半導体層、１０・・・エミッタ領域、
１１・・・コレクタ領域、１２・・・気相成長酸化シリ
コン膜（第２の絶縁膜）、１３・・・シリサイド合金膜
、１４・・・バリア金属膜、１５・・・アルミニウム、
１６・・・半導体基板の露出シリコン面、１７・・・フ
ォトレジストパターン。
７Ａ′−７層
第２
図
弔
図
第４
図
第４
図FIGS. 1(a) to 1(c) are sectional views showing the main steps of the first embodiment of the present invention, and FIGS. 2(a) to 2(C)
is a sectional view showing the main steps of the second embodiment of the present invention, FIG. 3 is a circuit diagram of a configuration in which a bipolar transistor and an SBD are connected, and FIGS. 4(a) to 4(e) are a conventional manufacturing method. FIGS. 5(a) and 5(b) are sectional views showing an example of the process in the order of steps, and FIGS. 5(a) and 5(b) are sectional views for explaining problems in the conventional method. 1...p-type semiconductor substrate, 2...n-type buried layer, 3...
・P-type buried layer, 4...n-type epitaxial layer, 5...
・Field insulating film, 6... Silicon oxide film (first insulating film) 7... Base layer, 8... High concentration impurity region, 9... Polycrystalline semiconductor layer, 10... Emitter region ,
DESCRIPTION OF SYMBOLS 11... Collector region, 12... Vapor-phase growth silicon oxide film (second insulating film), 13... Silicide alloy film, 14... Barrier metal film, 15... Aluminum,
16...Exposed silicon surface of semiconductor substrate, 17...Photoresist pattern. 7A'-7th layer 2nd figure Funeral map 4 Figure 4
Claims (1)
高融点金属と金属膜より成る第２の電極を有する半導体
装置の製造方法において、半導体基板上を覆う第１の絶
縁膜に第１の電極を形成するための第１の開孔部を形成
する工程と、この第１の開孔部を含む半導体基板上全面
に多結晶半導体層と第２の絶縁膜を順次堆積する工程と
、これら第２の絶縁膜、多結晶半導体層及び前記第１の
絶縁膜を第１の開孔部と異なる領域において順次選択エ
ッチングして第２の電極を形成するための第２の開孔部
を形成する工程と、前記第２の開孔部内の半導体基板表
面上にシリサイド合金膜を形成する工程と、前記第２の
開孔部を覆うようにバリア金属膜を選択的に形成する工
程と、このバリア金属膜をマスクにして前記多結晶半導
体層上の第２の絶縁膜を除去する工程と、全面に金属膜
を被着し、これを前記第１の開孔部及び第２の開孔部に
残すように前記多結晶半導体層とともに選択的にエッチ
ングする工程とを含むことを特徴とする半導体装置の製
造方法。1. A first electrode made of a polycrystalline semiconductor layer and a metal film;
In a method of manufacturing a semiconductor device having a second electrode made of a high melting point metal and a metal film, a first opening for forming the first electrode is formed in a first insulating film covering a semiconductor substrate. a step of sequentially depositing a polycrystalline semiconductor layer and a second insulating film over the entire surface of the semiconductor substrate including the first opening; forming a second opening for forming a second electrode by sequentially selectively etching the insulating film in a region different from the first opening; and a surface of the semiconductor substrate within the second opening. forming a silicide alloy film on the polycrystalline semiconductor layer; selectively forming a barrier metal film to cover the second opening; and using the barrier metal film as a mask to form a silicide alloy film on the polycrystalline semiconductor layer; Step 2 of removing the insulating film, and depositing a metal film on the entire surface, and selectively etching it together with the polycrystalline semiconductor layer so as to leave it in the first opening and the second opening. A method for manufacturing a semiconductor device, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63163217A JP2661153B2 (en) | 1988-06-30 | 1988-06-30 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63163217A JP2661153B2 (en) | 1988-06-30 | 1988-06-30 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0212833A true JPH0212833A (en) | 1990-01-17 |
| JP2661153B2 JP2661153B2 (en) | 1997-10-08 |
Family
ID=15769532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63163217A Expired - Lifetime JP2661153B2 (en) | 1988-06-30 | 1988-06-30 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2661153B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60169169A (en) * | 1984-02-13 | 1985-09-02 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
-
1988
- 1988-06-30 JP JP63163217A patent/JP2661153B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60169169A (en) * | 1984-02-13 | 1985-09-02 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2661153B2 (en) | 1997-10-08 |
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