JPH02127442U - - Google Patents

Info

Publication number
JPH02127442U
JPH02127442U JP1989036975U JP3697589U JPH02127442U JP H02127442 U JPH02127442 U JP H02127442U JP 1989036975 U JP1989036975 U JP 1989036975U JP 3697589 U JP3697589 U JP 3697589U JP H02127442 U JPH02127442 U JP H02127442U
Authority
JP
Japan
Prior art keywords
led
wiring boards
led chip
array head
chip row
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989036975U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989036975U priority Critical patent/JPH02127442U/ja
Publication of JPH02127442U publication Critical patent/JPH02127442U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dot-Matrix Printers And Others (AREA)
  • Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案のＬＥＤアレイヘツドの一実施
例を示す上面図、第２図は第１図の−断面図
、第３図は従来のＬＥＤアレイヘツドの上面図、
第４図はその横断面図、第５図は従来のＬＥＤア
レイヘツドの突き合わせ部を示す拡大図である。 図中、１……セラミツク配線基板体、２，３…
…セラミツク配線基板、４……突き合わせ部、５
，５１……ＬＥＤチツプ、６，６１……駆動用Ｉ
Ｃ、７……金属ワイヤ、８……基板固定板、９…
…ヒートシンク、１７……発光部を示す。 FIG. 1 is a top view showing an embodiment of the LED array head of the present invention, FIG. 2 is a cross-sectional view taken from FIG. 1, and FIG. 3 is a top view of a conventional LED array head.
FIG. 4 is a cross-sectional view thereof, and FIG. 5 is an enlarged view showing the abutting portion of a conventional LED array head. In the figure, 1... Ceramic wiring board body, 2, 3...
... Ceramic wiring board, 4 ... Butt portion, 5
, 51... LED chip, 6, 61... Drive I
C, 7... Metal wire, 8... Board fixing plate, 9...
. . . heat sink, 17 . . . indicates a light emitting section.

Claims (1)

【実用新案登録請求の範囲】 １ 複数の配線基板をその端部を突き合わせて一
枚の基板固定用の平板上に固定し、この複数の配
線基板上にＬＥＤチツプを直線的に配列すると共
にこのＬＥＤチツプ列の側方にＬＥＤチツプ列に
沿つて駆動用ＩＣを配設したことを特徴とするＬ
ＥＤアレイヘツド。 ２ 上記ＬＥＤチツプ列は、上記複数の配線基板
の突合せ部と交差する部分では、その部分のＬＥ
Ｄチツプが突き合わせ部を跨ぐように搭載されて
いることを特徴とする請求項１記載のＬＥＤアレ
イヘツド。 ３ 上記基板固定用の平板は配線基板の熱膨張率
と近い値を持つことを特徴とする請求項１又は２
記載のＬＥＤアレイヘツド。[Claims for Utility Model Registration] 1 A plurality of wiring boards are fixed on a single board fixing flat plate with their ends butted together, and LED chips are linearly arranged on the plurality of wiring boards, and the LED chips are arranged linearly on the plurality of wiring boards. L characterized in that a driving IC is arranged along the LED chip row on the side of the LED chip row.
ED array head. 2 At the portion where the LED chip row intersects with the abutting portion of the plurality of wiring boards, the LED chip row at that portion
2. The LED array head according to claim 1, wherein the D-chip is mounted so as to straddle the abutting portion. 3. Claim 1 or 2, wherein the flat plate for fixing the board has a coefficient of thermal expansion close to that of the wiring board.
The LED array head described.
JP1989036975U 1989-03-30 1989-03-30 Pending JPH02127442U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989036975U JPH02127442U (en) 1989-03-30 1989-03-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989036975U JPH02127442U (en) 1989-03-30 1989-03-30

Publications (1)

Publication Number Publication Date
JPH02127442U true JPH02127442U (en) 1990-10-19

Family

ID=31543677

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989036975U Pending JPH02127442U (en) 1989-03-30 1989-03-30

Country Status (1)

Country Link
JP (1) JPH02127442U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004311791A (en) * 2003-04-08 2004-11-04 Sharp Corp Lighting device, backlight and display

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004311791A (en) * 2003-04-08 2004-11-04 Sharp Corp Lighting device, backlight and display

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