JPH02126721A - Phase detecting circuit - Google Patents

Abstract

PURPOSE:To obtain a phase detecting circuit which is small in the number of logic elements and suitable to a high speed action by adding an input signal and a signal obtained from a voltage control oscillating circuit to an exclusive OR circuit, phase-detecting them and obtaining the control signal of the voltage control generating circuit. CONSTITUTION:When the phase of an output pulse signal VCO(voltage control oscillating circuit) of a VCO3 and an input signal REF are mutually matched, the phase output signal of a duty 50% is generated at an EXOR 1. A control voltage is added from a control voltage generating circuit 4 to the VCO3 so that the VCO3 can be oscillated by the set reference oscillation frequency. The phase of the signal VCO is advanced for the input signal REF and at the time of becoming -45 deg., the phase output signal of a duty 75% is generated at the EXOR1. The control voltage corresponding to this is added from the control voltage generating circuit 4 to the VCO3 and the oscillation frequency of the VCO3 is controlled so as to go to the reference frequency.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a phase detection circuit, and more specifically, a phase detection circuit suitable for IC implementation when generating a reference signal in a PLL system using a logic circuit. Regarding improvements.

[Prior Art] As a conventional PLL type phase detection circuit suitable for IC implementation, a logic circuit using an edge-type flip-flop circuit is used.

FIG. 4 shows an example of this, in which the reference signal REF and the voltage controlled oscillation circuit (
VCO) output signal from set terminal S and reset terminal FR.
and a phase output signal PDOU to its Q output.
I'm getting a T.

In addition, (a) of FIG. 5 is a timing chart of the operation, and its phase duty conversion characteristic is shown in (b) of the same figure.
As shown in , the phase output signal PDOUT increases in response to the phase delay of the VCO with respect to the REF signal, and becomes
The characteristic is that the duty is 100% at 360 degrees and -i'50%.

[Problem to be solved a] Usually, an edge trigger type flip-flow knob circuit is a NAND circuit, as shown in FIG.

It is constructed using many basic logic circuits such as NOR circuits. Therefore, when this is developed into a gate-level hardware configuration, the number of logic elements increases, and since multiple stages of logic elements T are combined, the operation speed becomes slow.

Therefore, when performing phase detection at a high frequency, the detection output will contain many errors, and a high-precision PLL
become unable to function.

The present invention is intended to solve the problems of the prior art, and aims to provide a phase detection circuit that requires a small number of logic elements and is suitable for high-speed operation.

[Means for Solving the Problems] The configuration of the phase detection circuit of the present invention to achieve such an object is to add an input signal and a signal obtained from a voltage controlled oscillation circuit to an exclusive OR circuit, and perform phase detection. The control signal for the voltage control generation circuit is obtained by doing this.

[Function] In this way, by using the exclusive OR circuit as a phase detection circuit, the number of elements that are open to the gate level by I1m can be reduced, and the number of element stages is also reduced, resulting in faster operation. Therefore, even when used in a high frequency phase detection circuit, phase detection with little error can be performed.

[Embodiment] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a PLL circuit using the phase detection circuit of the present invention, FIG. 2 is a timing chart of its phase detection operation, and FIG. 3 is a diagram of its phase table duty characteristic. It is a graph.

In FIG. 1, 5 is a PLL circuit, and 1 is a phase detection circuit constituted by an exclusive OR circuit (EXOR) thereof. The output of EXOR1 is applied to a control voltage generation circuit 4 via a low-pass filter 2, and the control voltage generation circuit 4 generates a control voltage for the VCO3 to control the VCO3. The output of VCO3 is then applied to one input of EXOR1. Further, the REF signal is input to the other input of EXORI. Note that the oscillation frequency of the VCO 3 is controlled by an upward voltage centered on the reference voltage level.

To explain the phase detection operation according to Fig. 2, the VCO
If the relationship between VCO, which is the output pulse signal of No. 3, and REF, which is the pulse signal of input signal REF, is the relationship shown in FIG. occurs, and this state is VCO
A control voltage is applied to the VCO 3 from the control voltage generation circuit 4 so that the phases of and REF match the phase σ, and the VCO 3 oscillates at the set reference oscillation frequency.

As shown in (b) of the same figure, V
When the phase of CO3 advances and vCO reaches 145 degrees, the phase output signal PDOUT with a duty of 75% becomes E.
A control voltage generated at XORs and corresponding thereto is applied from the control voltage generation circuit 4 to the VCO 3, and the oscillation frequency of the VCO 3 is controlled to become the reference frequency.

Further, as shown in (C) of the same figure, when the phase of VCO3 further advances with respect to the input signal REF and vCO reaches 190 degrees, the phase output signal P with a duty of 100%
DOUT is generated at EXORl, which is at logic level H.
The signal becomes an IGH level signal, and the corresponding control voltage is applied from the control voltage generation circuit 4 to the VCO3.
is controlled so that the oscillation frequency of is the reference frequency.

In this way, as shown in (d) to (h) of the same figure,
The phase of VCO3 is 1135 degrees with respect to the input signal REF,
When the temperature reaches -180 degrees, +135 degrees, +90 degrees, and +45 degrees, the duty is 75%, 50%,
45%, logic level and LOW level signal (zero voltage)
, and the 45% phase output signal PDOUT is EXORt
The oscillation frequency of the VCO 3 is controlled so that the oscillation frequency of the VCO 3 becomes the reference frequency by applying the corresponding control voltages to the VCO 3.

The phase table duty characteristic in this case is as shown in the graph shown in Figure 3, when the phase is zero, the duty is 50%.
As the phase lags or advances, it becomes a polygonal curve, with a duty of 100% at a phase of 190 degrees and a duty of 0% at a phase of +90 degrees.

Although the embodiments have been described above mainly in the case of PLL, the present invention is of course applicable not only to the case of PLL but also to phase detection in general when controlling vCO.

[Effects of the Invention] As can be understood from the explanation in 1- below, the present invention achieves the following effects by using an exclusive OR circuit as a phase detection circuit.
The number of elements deployed at the gate level can be reduced, and the number of stages in the element r configuration is also reduced, resulting in faster operation speed and phase detection with fewer errors even when used in high frequency phase detection circuits. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a PLL circuit using the phase detection circuit of the present invention, FIG. 2 is a timing chart of its phase detection operation, and FIG. 3 is a diagram of its phase 0 duty characteristic. 4 is an explanatory diagram of a conventional phase detection circuit, and FIG. 5 is a timing chart illustrating its operation and an explanatory diagram of phase/duty characteristics. DESCRIPTION OF SYMBOLS 1... Exclusive OR circuit (EXOR), 2... Low pass filter, 3... Voltage control oscillation circuit, 4... Control voltage generation circuit. Figure Figure Figure Figure (a) vc. DOUT (C) 9th section (d) ■α[ Figure p Sniff bar Figure I Standing 1

Claims (1)

[Claims] (1) A phase detection circuit characterized in that it obtains an exclusive OR of an input signal and a signal obtained from a voltage control oscillation circuit as a phase detection output, thereby generating a control signal for the voltage control generation circuit.