JPH02126718A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH02126718A JPH02126718A JP28186688A JP28186688A JPH02126718A JP H02126718 A JPH02126718 A JP H02126718A JP 28186688 A JP28186688 A JP 28186688A JP 28186688 A JP28186688 A JP 28186688A JP H02126718 A JPH02126718 A JP H02126718A
- Authority
- JP
- Japan
- Prior art keywords
- microcomputer
- frequency
- multiplier
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 3
- 230000005855 radiation Effects 0.000 abstract description 3
- 230000010355 oscillation Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は基本クロックを発生する発振器とマイクロコン
ピュータを同一半導体基板上に有する半導体集積回路に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit having an oscillator that generates a basic clock and a microcomputer on the same semiconductor substrate.
従来、マイクロコンピュータの動作スピードを上げるに
は、基本クロックの周波数を上げなければならないため
、集積回路外部の発振子の周波数を上げていた。Conventionally, in order to increase the operating speed of a microcomputer, it was necessary to increase the frequency of the basic clock, which led to increasing the frequency of an oscillator external to the integrated circuit.
上述した従来の半導体集積回路では、マイクロコンピュ
ータの動作スピードを上げる場合、集積回路外部の発振
子の周波数を上げていたので集積回路の発振端子より出
るスプリアス放射が、同時にセットされた他の回路、特
に最近マイクロコンピュータと共に用いられるようにな
った高周波回路(テレビ、VTR,ラジオ等)にノイズ
発生の影響を与えるという欠点がある。In the conventional semiconductor integrated circuit described above, when increasing the operating speed of the microcomputer, the frequency of the oscillator external to the integrated circuit was increased, so that spurious radiation emitted from the oscillation terminal of the integrated circuit was transmitted to other circuits set at the same time. In particular, it has the disadvantage of generating noise in high frequency circuits (televisions, VTRs, radios, etc.) that have recently come to be used with microcomputers.
本発明の半導体集積回路は内部に発振器の周波数を逓倍
する手段を有している。The semiconductor integrated circuit of the present invention has internal means for multiplying the frequency of the oscillator.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例を示す回路図で、1は半導体
集積回路、2.3は発振端子、4は逓倍器、5は水晶発
振子、6,7は発振周波数調整用容量、8は位相が18
0度反転する増幅器、9は自己バイアス抵抗である。逓
倍器4は第2図にその詳細を示すように、デイレイ素子
10.NANDゲート11.インバータゲー)12,1
4.NORゲート13.15で構成される。FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which 1 is a semiconductor integrated circuit, 2 and 3 are oscillation terminals, 4 is a multiplier, 5 is a crystal oscillator, 6 and 7 are capacitors for adjusting the oscillation frequency, 8 has a phase of 18
The amplifier inverts 0 degrees, 9 is a self-biasing resistor. As shown in detail in FIG. 2, the multiplier 4 includes delay elements 10. NAND gate 11. Inverter game) 12,1
4. It consists of NOR gates 13 and 15.
第3図に逓倍器4への入力波形16.デイレイ素子10
の出力波形17.インバータゲート12の出力波形18
.NORゲート15の出力波形19、インバータゲート
14の出力波形20を示す。FIG. 3 shows the input waveform 16 to the multiplier 4. Delay element 10
Output waveform 17. Output waveform 18 of inverter gate 12
.. An output waveform 19 of the NOR gate 15 and an output waveform 20 of the inverter gate 14 are shown.
以上よりわかるように逓倍器2へ入力されるクロックパ
ルスは2倍の周波数を有するクロックパルスとして逓倍
器より取り出されマイクロコンピュータの基本クロック
として使用される。As can be seen from the above, the clock pulse input to the multiplier 2 is extracted from the multiplier as a clock pulse having twice the frequency and used as the basic clock of the microcomputer.
以上説明したように本発明は、集積回路外部の発振子の
周波数を上げずに集積回路内部で発振器の周波数を逓倍
することにより基本クロックの周波数を上げるのでマイ
クロコンピュータと共にセットされた他の回路、特にテ
レビ、VTR,ラジオ等の高周波回路に集積回路の発振
端子からのスプリアス放射によるノイズ発生の影響を与
えずにマイクロコンピュータの動作スピードを上げられ
る効果がある。As explained above, the present invention increases the frequency of the basic clock by multiplying the frequency of the oscillator inside the integrated circuit without increasing the frequency of the oscillator outside the integrated circuit. In particular, it is effective in increasing the operating speed of a microcomputer without affecting high frequency circuits such as televisions, VTRs, radios, etc. by noise generation due to spurious radiation from the oscillation terminals of integrated circuits.
第1図は本発明の一実施例を示すブロック図、第2図は
第1図に示す逓倍器の論理図、第3図は第2図の各ゲー
トで出力される波形図である。
■・・・・・・半導体集積回路、2,3・・・・・・発
振端子、4・・・・・・逓倍器、5・・・・・・水晶発
振子、6,7・・・・・・発振周波数調整用容量、8・
・・・・・位相が180度反転する増幅器、9・・・・
・・自己バイアス抵抗、lO・・・・・・デイレイ素子
、11・・・・・・NANDゲート、12゜14・・・
・・・インバータゲー)、13.15・・・・・・NO
Rゲート、16・・・・・・逓倍器4への入力波形、1
7・・・・・・デイレイ素子10の出力波形、18・・
・・・・インバータゲート12の出力波形、19・・・
・・・N。
Rゲート15の出力波形、20・・・・・・インバータ
ゲート14の出力波形。
代理人 弁理士 内 原 晋FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a logic diagram of the multiplier shown in FIG. 1, and FIG. 3 is a waveform diagram output from each gate in FIG. ■... Semiconductor integrated circuit, 2, 3... Oscillation terminal, 4... Multiplier, 5... Crystal oscillator, 6, 7... ...Capacitor for oscillation frequency adjustment, 8.
...Amplifier whose phase is inverted by 180 degrees, 9...
... Self-bias resistance, lO ... Delay element, 11 ... NAND gate, 12゜14 ...
...inverter game), 13.15...NO
R gate, 16...Input waveform to multiplier 4, 1
7... Output waveform of delay element 10, 18...
...Output waveform of inverter gate 12, 19...
...N. Output waveform of R gate 15, 20... Output waveform of inverter gate 14. Agent Patent Attorney Susumu Uchihara
Claims (1)
そのマイクロコンピュータに与える基本クロックの周波
数を逓倍する手段を有することを特徴とする半導体集積
回路A semiconductor integrated circuit comprising a microcomputer on the same semiconductor substrate and further comprising means for multiplying the frequency of a basic clock applied to the microcomputer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28186688A JPH02126718A (en) | 1988-11-07 | 1988-11-07 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28186688A JPH02126718A (en) | 1988-11-07 | 1988-11-07 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02126718A true JPH02126718A (en) | 1990-05-15 |
Family
ID=17645077
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28186688A Pending JPH02126718A (en) | 1988-11-07 | 1988-11-07 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02126718A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5399996A (en) * | 1993-08-16 | 1995-03-21 | At&T Global Information Solutions Company | Circuit and method for minimizing electromagnetic emissions |
-
1988
- 1988-11-07 JP JP28186688A patent/JPH02126718A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5399996A (en) * | 1993-08-16 | 1995-03-21 | At&T Global Information Solutions Company | Circuit and method for minimizing electromagnetic emissions |
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