JPH02126441U - - Google Patents

Info

Publication number
JPH02126441U
JPH02126441U JP3439289U JP3439289U JPH02126441U JP H02126441 U JPH02126441 U JP H02126441U JP 3439289 U JP3439289 U JP 3439289U JP 3439289 U JP3439289 U JP 3439289U JP H02126441 U JPH02126441 U JP H02126441U
Authority
JP
Japan
Prior art keywords
clock
receiving device
tuner
supplied
pll circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3439289U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3439289U priority Critical patent/JPH02126441U/ja
Publication of JPH02126441U publication Critical patent/JPH02126441U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Stereo-Broadcasting Methods (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の受信装置の要部の
ブロツク図である。
FIG. 1 is a block diagram of the main parts of a receiving apparatus according to an embodiment of the present invention.

Claims (1)

【実用新案登録請求の範囲】 (1) PLL回路で決定される周波数で選局を行
うチユーナ部を複数有する複数チヤンネルの受信
装置において、 上記各チユーナ部のPLL回路の基準クロツク
を1個のクロツク源から供給したことを特徴とす
る受信装置。 (2) 上記クロツク源を1個のチーナ部に組み込
み、他のチユーナ部へのクロツク供給をコンデン
サを介して行つたことを特徴とする実用新案登録
請求の範囲第1項記載の受信装置。
[Claims for Utility Model Registration] (1) In a multi-channel receiving device having a plurality of tuner sections that perform tuning at a frequency determined by a PLL circuit, the reference clock of the PLL circuit of each tuner section is set to one clock. A receiving device characterized in that the receiving device is supplied from a source. (2) The receiver according to claim 1, wherein the clock source is incorporated in one tuner section, and the clock is supplied to other tuner sections via a capacitor.
JP3439289U 1989-03-28 1989-03-28 Pending JPH02126441U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3439289U JPH02126441U (en) 1989-03-28 1989-03-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3439289U JPH02126441U (en) 1989-03-28 1989-03-28

Publications (1)

Publication Number Publication Date
JPH02126441U true JPH02126441U (en) 1990-10-18

Family

ID=31538823

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3439289U Pending JPH02126441U (en) 1989-03-28 1989-03-28

Country Status (1)

Country Link
JP (1) JPH02126441U (en)

Similar Documents

Publication Publication Date Title
JPH02126441U (en)
ES8607644A1 (en) Tuning arrangement.
JPS5830359U (en) Receiving machine
JPH0264222U (en)
JPS63174736U (en)
JPH0295944U (en)
JPS6077125U (en) Television receiver channel selection device
JPS58123635U (en) Receiving machine
JPS6157627U (en)
JPS623121U (en)
JPH0359747U (en)
JPS609333U (en) PLL receiver
JPH0356235U (en)
JPH01160738U (en)
JPS647441U (en)
JPS58161347U (en) Receiving machine
JPS60174373U (en) Television signal receiving circuit
JPS6423132U (en)
JPH0439742U (en)
JPH0472728U (en)
JPH02188017A (en) Clock extracting circuit
FR2439507A1 (en) SYNCHRONIZATION ASSEMBLY OF THE OSCILLATOR FREQUENCY AND THE RESONANCE FREQUENCY OF THE INPUT CIRCUIT OF A SUPER-HETERODYNE RECEIVER
JPS63142926U (en)
JPS5888461U (en) Receiving machine
JPH02134745U (en)