JPH02125331A - Dividing and multiplying square root extractor - Google Patents

Abstract

PURPOSE:To increase the approximating calculation speed in the Newton- Raphson's method by eliminating the difference in the number of transfer machine cycles from the output stage to the input stage of a multiplier between execution and non-execution of operation of the output of the multiplier in an adder/subtractor or a shifter. CONSTITUTION:A subtracting and shifting circuit is inserted between the output stage and the input stage of a multiplier 10, and the output of the multiplier 10 is directly inputted to a subtracting and shifting circuit 11, and the output result of this circuit 11 is inputted to the multiplier 10 through a bus 14 or a private local bus. That is, the multiplier 10 calculates a multiplication term in a recurrence formula, and the subtracting and shifting circuit 11 subtracts '2' or '3' from the output of the multiplier 10 and shifts the result as required, and the result is transferred to the multiplier 10 through the bus 14. Consequently, the recurrence formula is calculated. Thus, multiplication and division processings in the approximating calculation of the Newton-Raphson's method are continuously performed to increase the calculation speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic device having a multiplier, and more particularly to a multiplication/division squarer that performs a division or square rooter operation using a multiplier.

[Conventional technology]

Conventionally, multipliers have been used in addition to adders to speed up multiplication in arithmetic devices, while approximation calculations have been used to speed up division and square root operations. , multipliers are generally used for approximate calculations. A method of performing division by approximate calculation using a multiplier is described in, for example, Japanese Patent Laid-Open No. 49-96647.

[Problem to be solved by the invention]

On the other hand, the approximate calculation method called Newton-Raphson method is a method of calculating the function value using the equation of the tangent line of the function, and the value of the function is calculated by calculating the following recurrence formula for the function f (x). This is what we seek.

When dividing A÷B using this method, -=A・f(x)
If =B--=O, the recurrence formula becomes as follows.

Xt+1=Xi @ (2B xt) (2) In this way, if this method is used, division can be realized only by multiplication and subtraction.

In addition, in square root arithmetic, f (x)=A −xz=0
Then, the recurrence formula is Xi"1=Xt.

・(3A-xt”) ...(4) Next door.

Square root calculation can be realized using only multiplication, subtraction, and -times operations.

In a binary calculator, the 1x operation is This can be achieved by simply shifting.

However, in the conventional example, the adder/subtracter that performs subtraction is separate from the multiplier, and it is necessary to transfer the result of one multiplication to the adder/subtracter, perform the operation, and transfer the result of the operation to the multiplier again.

The purpose of the present invention is to reduce the overhead caused by this subtraction,
The objective is to speed up approximate calculation using the Newton-Raphson method.

[Means to solve the problem]

The above purpose is to add a subtractive shift rotation between the output stage and the input stage of the multiplier, input the output of the multiplier directly to the subtractive shift circuit, and send the output result of the subtractive shift circuit via a bus or a dedicated local bus. This is achieved by inputting to a multiplier. Furthermore, by specifying the type of subtraction and simplifying the subtraction circuit, processing speed can be further increased.

[Effect]

The multiplier calculates the multiplication term in the recurrence formula, and the subtraction shift circuit subtracts 2 or 3 from the output of the multiplier, performs shift operations as necessary, and transfers the result to the multiplier via the bus.

This allows the recurrence formula to be calculated.

C Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 to 6.

Figure 1 is a diagram showing the basic configuration of the present multiplier-removal squarer.
X) 12, Multiplier source register Y (MSRY) 13
and a bus (BUS) 14 as basic components.

MULTIO performs multiplication of n bits by n bits and 2
Outputs the result of 0 pits. 5BSFII performs subtraction and shift operations, details of which will be described later.

MSRX12 and MSRY13 are n-bit registers that hold values that are input to MULTIO. BUS
14 performs data transfer between the 5BSF11, MSRX12, and MSRY13.

Although the data width of the BUS 14 is 2n bits in this embodiment, the data width is not essential to the present invention.

FIG. 2 is a diagram showing the details of the overall configuration of the multiplication/division squarer.*The Newton-Raphson method requires an initial value for calculating the recurrence formula, but in this embodiment, the initial value is determined using the constant table (CT) 20. generate a value.

CT2O is the constant table address register (CTAR
) 201, constant storage device I (CTM) 202, constant table output register (CTOR) 203, and BUS
14. CTAR201 is BUS14
The receiver takes the above data as the address of the daple reference.

Constants in CTM202 are read out to CTOT203 using the contents of CTAR201 as an address, and CTOR203
The contents of are output to the BUS 14. The data width of BUS14 is 2n bits, but the upper n bits are
USH141 and lower n bits are assumed to be BUSL142.

In this embodiment, CTAR201 connects to BUSH141 and CTAR201.
OR203 is BUSH141 and BUSL142, M
SRX12 is BUSH141, MSRY13 is BUS
) (141 and BUSL142, 5BSFII is BU
It is assumed that the SH 141 and the BUSL 142 are connected to each other.

A control device (CTRL) 21 controls the operation of the multiplication/division squarer. The CTRL 21 includes a loop counter (LC) 211 and a decrementer (LC) 211 for controlling the number of approximate calculations.
DEC) 212.

A predetermined value is set in LC211, and D E C212
decreases the value of LC211. When the value of LC211 becomes 0, CTRL21 shall perform predetermined control.

Incidentally, it is not essential that the loop counter be included in the control device, and it is sufficient if there is a number control means having the same function as the loop counter in the entire device including the multiplication/division squarer.

In this embodiment, the data to be handled is a floating point number.

In other words, the number is S-M・2E (where S is the sign, M is the mantissa,
City is expressed as index). The sign and exponent are processed outside the multiplication/division squarer, and this multiplication/division squarer handles only the mantissa of floating point numbers. That is, it is assumed that an integer bit is 1 bit. Since the decimal point position is also below the MSB in MSRX12 and MDRY13, the output of MULTIO is M as shown in Figure 3.
There is a decimal point position below the SB-1 bit. That is, MUL
The output of the TLO consists of two integer bits.

Next, the functions of 5BSFII will be explained.

The details of the configuration of 5BSFII are shown in FIG.

5BSFI 1 is subtraction circuit (SUB) 111, shift circuit (SFT) 112, output register (S S OR) 1
13 and a shift-out carry register (SFC) 114. The 5UB 111 performs subtraction on the MULT 1017) output, the 5FT 112 performs a shift operation on the subtraction result, and stores the results in the 5SOR 113 and 5FC 114.

In the case of division and square rooting, SUB 111 subtracts 2 and 3 from the output of MULTlo, respectively. This operation is performed as follows. Subtraction from 2 is an operation of taking two's complement, and MULTIO's The output is a = b 1In-1
b 2n-L mu b xn-s-b s b o (mu is a decimal point), then 2- a == b 2n-1b
xn-zmu bzn-s・=bzbo+2″″(2′″-
”) (bt is the inversion of bI, 2-prl-g is a carry input from LSB). Subtraction from 3 is 3-a=1+
Since (2-a), it is sufficient to add 1 to the result of 2-a. By the way, if we pay attention to the fact that the AX- term in equation (4) is a number close to 1 (that is, the multiplication result never exceeds 2), we get 3- a = b 2n-2b 2n-2 m b 2n-
3'1lll b s b o+ 2-(""2), on the other hand, the carry size of 2-(zn-z) is Ne
%+ton-Since the error is smaller than the error caused by the approximate calculation using the Raphson method, the calculation accuracy is not affected even if the carry of 2'''' (zn-z) is not added.Therefore, 5LIB1
11 processing is MULTlo output result b 2n-1b
2n-2mu b 2n-3...b For lbo, 2
b for subtraction from ! n-1b zn-zmu b
Outputs 1n-3+++ b s b o , and for subtraction from 3, outputs b zn-x b 2n-2 m b zn
-s-b 1b.

will be output. In addition, if subtraction is not performed, M
The output of ULTIO is directly used as the output of SUB 111. Furthermore, if only approximate calculations are performed up to m bits (2n>m), it is meaningless to output any value for the lower 2n+m-2 bits, so the operation by the SUB 111 is performed using the upper 2n-2 bits. It is also possible to go only to m+2 bits.

Since the output of SUB 111 has a decimal point position below the MSB-1 bit, the decimal point position must be adjusted in order to use this value again for calculation. For that reason 5
The FT 112 shifts the output to the SUB 111 by 1 bit to the left, and outputs it to the 5SOR 113. At that time SUB
The MSB 1 bit of the output of 5FC 111 is output to 5FC 114 as a shift-out carry. This aligns the decimal point. Note that in formula (2), 2-B-x
Since the t term is a number close to 1, 5FC114 will never be 1. In the case of a square rooter, the process of multiplying by - in the recurrence formula is to directly convert the output of SUB 111 to 5SO without shifting it.
It is sufficient to output it to R113. In other words, the positions of several points where the apparent stopped vehicle is shifted to the left by one bit, resulting in an operation of multiplying by one. Note that in this example, the decimal point position on the bus is shifted by 1 bit to the left with respect to the multiplier output, so in the case of a square rooter, there is no need to perform a shift operation, but the relationship between the decimal point positions is different from that in this example. In a case different from the example, in the case of a square rooter, it is necessary to perform a 1-bit right shift operation on the decimal point position.

Next, a method of calculating division and square root square using this embodiment will be explained.

First, division will be explained. A flowchart of the division calculation is shown in FIG. Figure 5 shows that in the calculation of A÷B,
One is found by the recurrence formula of equation (2), and then -.A is found. The procedure will be explained below with reference to FIG.

First, the number of repetitions in the recurrence formula is expressed as LC in CTRL21.
Set to 211. The number of repetitions is determined in advance based on the relationship between the accuracy of the initial value and the accuracy of the value to be determined. (501) Next, the initial value for calculating the recurrence formula is read from CT2O.

The value of the divisor B is placed on BUS14.

The data on BUSH141 is stored in CTAR201.
2n-1b 2n-2"' b n+1 b n, then m-1 bit data of b zn-z b 2n-3...b Ln-* is input. This means that the multiplication/division squarer is This is because the integer bit, ie, b2h-i, on the BUS 141 is always 1 since floating point mantissa data is handled.The initial value of the corresponding Ω bit is read from the CTM 202 according to the contents of the CTAR 201.

The output of CTM 202 is set to CTOR 203.

The data width of CTOR203 is 2n bits;
The data width may be less than one bit.

The output data width Q of the CTM 202 is set to be m-1 or more. However, in the case of division, the possible range of the initial value is -x≦1
Since it is 1 to 0.111 (2) in binary representation, the integer bits of the initial value and the first bit below the decimal point are respectively O and 1. CTM
When reducing the data width Q of 202 and storing it in CTOR 203, 0 is added to the integer bits and the first bit below the decimal point.
and l can be bid. Conversely, the accuracy of the initial value can be improved without changing the data width Q. CTOR2
A predetermined constant value is entered into the lower 2n-Q-2 bits of 03. ...(502) The initial value read to CTOR203 is sent to MSRX12 via BUS14.
can be placed in ...(503) Divisor B is placed in MSRY13. (504) MSRX12 and MSRY13 are multiplied. This means that the term B-xt in equation (2) has been calculated.

(505) Next, 52 is subtracted from the multiplication result by 5tJB 111, and the 2-B-X10 term in equation (2) is calculated. ...(506) SFT11
2 pads the subtraction result with 0 and shifts it to the left by 1 bit, 5FC11
Set to 4 and 5 SOR113. This aligns the decimal point. ...(507) 5SOR113
The upper n bits of the contents are sent to MSR via BUSH141.
It will be placed in Y13. (508) MSRX12 and MSRY13 are multiplied. The contents of MSRX12 store the value of xt in equation (2), which means that the right-hand side of equation (2) (2B-xt) has been calculated.・
(509) 5UBIII does not perform any operation on the multiplication result, and 5FT 112 performs a left shift to align the decimal point. (510) The upper n bits of the 5SOR 113 are input to the MSRX 12 via the BUSH 141. This means that the assignment from the right side of the recurrence formula to the left side has been performed. ...(511) The contents of LC211 are subtracted by DEC212, and the value is
can be placed in ...(512) CTRL21 is LC2
If the content of step 11 satisfies the calculation end condition, control is transferred to step (514); otherwise, control is transferred to step (504).
(513) Return the value of dividend A to MSRY13.
Put it in.

(514) MSRX12 and MSRY13 are multiplied. This means that - obtained by approximate calculation is multiplied by A, and the division of - is completed.・・・
・(515) SFT112 shifts the multiplication result to the left and
Enter into FC114 and 5SOR113. As a result, the final result of the division according to this embodiment is stored in 5SORI 13. (516) Next, square root calculation will be explained. A flowchart of the square root calculation is shown in FIG. In FIG. 6, in the calculation of H, 1 is obtained using the recurrence formula of equation (4), Jπ is then multiplied by A to obtain 5. The procedure will be explained below with reference to FIG.

First, the number of repetitions in the recurrence formula is expressed as LC in CTRL21.
Set to 211. The number of repetitions is determined in advance as in the case of division. (601) The initial value for calculating the recurrence formula is read from CT2O. The procedure is the same as for division, but in the case of square root arithmetic, if the exponent value is an odd number, if you divide the mantissa by 2 to make the exponent value even and then calculate, the integer bit of the mantissa will not necessarily be 1. isn't it.

Therefore, the value of the open base number A is placed on BUS14, but the data on BUSH141 is placed on CTAR201. If n-1b an-x・= b n+1 b n, then b 2n-1b 1ln-1...b! i-(
m-1 bits of data, which is (mat), is input. C
According to the contents of TAR 201, the initial value of the corresponding Ω bit is read from CTM 202. The output of the CTM 202 is set in the CTOR 203, but in the case of square root calculation, the possible number of bits of the initial value is not necessarily 1. Therefore, the integer bits cannot be determined in advance as in the case of division. (602) The initial value read to the CTOR 203 is input to the MSRX 12 via the BUS 14. ...(603) MSRY13 is filled with the open fraction A - (604) MSRX12 and MSRY1
A multiplication of 3 is performed. As a result, A−xl in formula (4)
This means that the term has been calculated.

(605) The 5FT 113 shifts the multiplication result by 1 bit to the left in order to align the decimal point position, and inputs the result into the 5FC 114 and 5SOR 113.・(6
06) Upper n bits of SSOR113 are BUSH141
into MS RY 13 via.・(607
) MS RX 12 and MS RY 13 are multiplied. MSRX12 is X in formula (4).

This means that the term A-xlz in equation (4) has been calculated. ...(608) Next 5UB11
3 is subtracted from the multiplication result by 1. This means that the term 3-A-x i2 in equation (4) has been calculated. (609) The SFT 112 inputs the subtraction result into the 5SOR 113 without shifting it. As a result, the subtraction result is relatively shifted to the right by 1 bit, and the term -.(3-A-xt") in equation (4) has been calculated. (610) 5SO
The upper n bits of R113 are sent to the MS via BUSH141.
It will be placed in RY13. ...(611)MS RX
12 is multiplied by MSRY13. The contents of MSRX12 hold the value of xl in formula (4), and formula (4)
This means that the right-hand side X1...(3-A-xi'') has been calculated.

...(612) The 5FT112 performs a left shift to align the decimal point on the multiplication result, ...(613
) The upper n bits of SSOR 113 are put into MSRXI2 via BUSH 141. This means that the assignment from the right side of the recurrence formula to the left side has been performed. ...(6
14) The contents of LC211 are subtracted by DEC212 and the value is placed in LC211. ...(615
(616)
Put the value of the open fraction A into MSRYl3. ...(61
7) Perform multiplication of MSRXI 2 and MSRYl 317). As a result, - obtained by approximate calculation is multiplied by A, and the calculation of 5 is completed. ...(6
18) SFT112 shifts the multiplication result to the left and converts it to 5FC1.
14 and 5SOR113. As a result, the final result of the square root squarer according to this embodiment is included in the 5SOR 113. ...(619) With the above specific explanation,
It can be seen that division and square rooting are executed according to this embodiment.

Next, another embodiment will be described with reference to FIGS. 7 and 8.

FIGS. 7 and 8 show the subtraction and shift circuits of the previous embodiment in which the subtraction circuit and the shift circuit are separated. In FIGS. 7 and 8, the shift circuit 30 has the same structure as the SFT 112.5SOR 113 and 5FC 114 in the previous embodiment. In FIGS. 7 and 8, the subtraction circuit 31 has the same structure as the SUB 111 in the previous embodiment. However, in this case, the data width is n bits. Further, in the subtraction process from 2 in division, since a shift is performed first, all bits from bzn-t to bn are inverted. In FIG. 7, subtraction circuit 31 is located between the output of shift circuit 30 and the input of MSRYl 3. In FIG. 8, the subtraction circuit 31 is MSRY
It is located between the output of l3 and the input of MULTIO.

The division and square root calculations in the embodiments of FIGS. 7 and 8 are performed in the same manner as in the previous embodiments.

Next, an embodiment of a floating point arithmetic device using the present multiplication/division squarer will be described. The basic configuration of this embodiment is shown in FIG.

The floating point arithmetic unit mainly consists of an exponent arithmetic section, a mantissa arithmetic section, a multiplication/division squarer, and a control section. The exponent calculation unit includes an exponent register file (ERF) 40, an exponent calculation unit (EAU)
)41. Exponent input register (EIR) 42, exponent output register (EOR) 43, exponent A bus (EABUS) 44
, an exponential B bus (EBBtJS) 45 is the basic component. The mantissa calculation unit is a mantissa register file (MRF) 5
0° mantissa calculation shifter (MASF) 51, mantissa input register (MIR) 52, mantissa output register (MOR) 53,
Mantissa A bus (MABUS) 54, mantissa B bus (MBBU)
S) 55 is the basic component.

ERF 40 stores index data. The EAU 41 performs calculations on the exponent part in floating point calculations.

EIR42 receives data from BUS14.

EOR43 sends data to BUS14.

EABUS44 and EBBUS45 are ER
F40°EAU41. This is a bus for data transfer between EIR42 and EOR43 (7). The MRF 50 stores mantissa data. The MASF 51 performs mantissa operations and shift operations in floating point number operations.

MIR52 receives and receives data from BUS14.

The MOR 53 sends BUS14L: data.

MABUS54 and MBBUS55 have MRF50°M
ASF51. This is a bus that transfers data between the MIR 52 and MOR 53. In this embodiment, the BUS 14 also has the function of transmitting data between the exponent operation section, the mantissa operation section, and the multiplication/division squarer. In this embodiment, the exponent operation section, the mantissa operation section, and the multiplication/division squarer can each operate independently, so that floating point operations can be executed at high speed.

〔Effect of the invention〕

According to the present invention, since multiplication and subtraction processing in approximate calculation using the Newton-Raphson method can be performed continuously, calculation speed is increased. By limiting the subtraction process, the subtraction operation is simplified, and the time for subtraction can be kept within the processing unit time for multiplication, so compared to when subtraction is performed with a normal adder/subtractor, it is much faster. Calculations are made faster.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, FIG. 3 is a diagram showing the operation of a multiplier, FIG. 4 is a detailed diagram of a subtraction shift circuit, and FIG. The figure is a flowchart of division, Figure 6 is a flowchart of square root calculation, Figures 7 and 8 are
This figure is a basic block diagram of another embodiment of the present invention, and FIG. 9 is a block diagram of an embodiment in which the present invention is applied to a floating point arithmetic unit. 10... Multiplier, 14... Bus, 20... Constant table. 111... Subtraction circuit, 112... Shift circuit. 2nd cause 2nd cause Figure 4 Figure 5 β7AR7 Building ND Figure 6-f;'TART Temple fNρ 7th cause 8th ward 90

Claims (1)

[Scope of Claims] 1. In a multiplication/division squarer having a multiplication device and determining the value of a function such as division or square rooting by approximation calculation that repeats multiplication and addition/subtraction, the output stage and the input stage of the multiplication device are connected. An addition/subtraction device or a shift device is provided in the data transfer path,
whether or not the output of the multiplication device is operated by the addition/subtraction device or the shift device;
A multiplication/division squarer characterized in that there is no change in the number of machine cycles transferred from the output stage to the input stage of the multiplication device. 2. In a multiplication/division squarer which has a multiplication device and calculates the value of a function such as division or square rooting by approximation calculation that repeats multiplication and addition/subtraction, in the data transfer path connecting the output stage and input stage of the multiplication device. A multiplication/division squarer device characterized by being provided with an addition/subtraction device or a shift device dedicated to approximate calculations. 3. A multiplication/division squarer, characterized in that in the first term or the second term, the addition/subtraction device is limited to subtraction from 2 or subtraction from 3. 4. In the third term, a multiplication/division squarer, characterized in that subtraction from 2 is approximated by a 1's complement number. 5. A multiplication/division squarer, characterized in that in the first term or the second term, the amount shifted by the shift device is 1 bit on either the left or the right. 6. In the first or second term, as an approximation formula for square root calculation, subtract the product of the square of the approximate value and the open root number from the constant,
A multiplication/division square rooter characterized by using the product of its value, an approximate value, and a constant.