JPH02125292A - Method for constituting three-dimensional raster image display device - Google Patents

Abstract

PURPOSE:To obtain an image within a practical image range by connecting plural processors in a cubic lattice shape, processing tokens corresponding to pixels on a screen and gathering the tokens and constituting an image. CONSTITUTION:The tokens corresponding to respective pixels are generated and passed to processors at proper positions on the surface of a picture element array PEARY togoether with proper directional vectors. The positions and vectors are calculated view point coordinates and view-line directional vectors and processors which receive the tokens makes a view-line search in its assigned memory space, and pass obtained information to next processors together with added tokens. Which of six processors is a next processor is calculated from the directional vectors that the tokens have. This process is repeated and the tokens appear on the surface of the PEARY eventually and information on the tokens is gathered to constitute the image. Thus, the image is obtained within the practical time range.

Description

[Detailed description of the invention] 31. Objective of the invention 3.1.1. Industrial Application Field This invention relates to computer graphics.
In particular, we will discuss methods for displaying three-dimensional raster images.

3.1.2. BACKGROUND OF THE INVENTION Conventional solid modeling methods represent a target figure as a combination of simple models, and synthesize an image using calculations from there.

Therefore, as the complexity of the figure increases, the amount of calculation also increases. In response, attempts have been made to improve throughput using multiprocessors, but unless the modeling method is changed, processing time will increase in proportion to the complexity of the figure.To deal with this, PEA RY ( Pi
A method for developing a three-dimensional raster image on a 3D raster image has been proposed.
Generalized 0bjectDisplay
"Processor Architecture",
The 11thAnnual International
onal Symposium on Compute
rArchtecture Conference
Proceedings.

MichiBan, 1984゜[2]0hasht, T,, T, Uchiki,
and M, Tokoro, “AThree-Di
Mensional 5haded Display
Method for Voxel-Based Rep
resentationll, EUROGRAPHI
C3'85. 1985゜[3] Uchiki, T,, T, 0hasni,
and M, Tokoro.

”Co11ision Detection in
"MotionSimulation", Comp
Uter and Graphics, Vol 7°No, 374.1983°[41 Tetsuya Uchimoto, Mari Tokoro, “3D graphic display mechanism using 3D memory -3COPE-,” Journal of the Communication Society of Japan, VolJ68-D No, 4.1985
゜3.1.3. However, the problem that the invention seeks to solve is
This method using PEAR requires access to a large amount of memory, so if it were to be implemented on a conventional data bus type computer, it would take an enormous amount of calculation time due to the Neumann bottleneck. This eliminates the bottleneck and allows you to earn 100 yen in a practical amount of time.

3.

2. Structure of the invention 3.

2.

1. Means to solve the problem [Symbol definition a] 3. Size of memory allocated to subPEARY, unit is voxel.

The size of the entire PEARY memory space.

The unit is voxel.

L2 Screen size 0. The unit is pixel.

Time required to access and calculate Cm1voxe1.

Ci Communication time between processors within the chip.

Ct Inter-chip communication time.

N3 Number of chips.

■3 Number of processors in the chip O Q3 Total memory in the chip 08. The unit is voxe
l Note 1: Even when the actual screen size is smaller than L2, you can set the screen size to L2 and evaluate the processing time, because it is the density of 5 tokens that affects the total processing time. It is. Therefore, even if the screen size is reduced, the processing time will not be reduced.

Note 2: IMN=L holds true.

Note 3: Q=IM holds true.

[Basic structure] Memory space of size 3 is connected to 5ubPE of size M3
One processor is assigned to 0-5 ubPEAR, which is decomposed into ARY.

A certain SUB PEA RY can be accessed only by the processor that manages it. Furthermore, the processor is connected to the six processors in front, back, left, right, top and bottom of itself, and can communicate with it. This results in a configuration in which N3 processors, each with a memory size of M3, are arranged in a cubic grid, and adjacent processors are connected to each other (Figure 1). Contains the 3D image.

Note: The shape of 5ubPEARY is a cube. In this way, in the line-of-sight search algorithm, -5ubPE
Since the average value of the length of the trajectory passing through ARY becomes the maximum, the amount of processing that can be processed within 5ubPEAnY increases,
Communication costs can be minimized on average.

[Outline design of functional circuit] 3.2.1.1. Processor unit configuration: 10C (Ilo Control) and PU (Pr
It consists of a processor unit) and memory. The IOC has six buses connecting adjacent processors, a communication bus with the PU, and memory for input and output queues. Note that the six buses may be realized using a data bus system, in which the PU is connected to the IOC and the raster data memory. (Figure 4) Operation: IOC - When receiving a token from another processor, it puts it in the input queue and returns an ACK. If there are no input keys, it waits until one becomes available.

- If the PU is empty, retrieve the token from the input queue and pass it to the PU to make the PU busy.

- When a token is returned from the PU, calculate the processor to which it should be given, give the token a bus name, put it in the output queue, and free up the PU. When the output queue is full, leave the PU busy and wait until the output queue becomes free.

If the bus in a certain direction is not waiting for an ACK and there is a token with that bus name in the output Kiko, the token is output to that bus and it waits for an ACK.

U ・Executes calculations such as ray tracing according to instructions from the IOC.

3.2.1.2. Cuboid surface structure: Consists of SC (5 surface control), data bus and queue for collecting and distributing data. Each SC is connected to a token delivery section and a token collection section. (Figure 5) 3.2.1. ．． 3)--Kun Delivery Department (TS: To
kenServer) Operation: Generates the necessary token and passes it to PEARY.

The order of generation is - many times on the same processor.
-Do it in short order so that you don't end up handing over the kun.

Incoming viewpoint coordinates Gaze direction vector Distance between viewpoint and screen Processing type Outgoing viewpoint Processor coordinates Position on the screen Gaze direction Vector Processing type Attributes attached to tokens (varies depending on the type of processing) 3.2.1.4 ．． Token collection unit (TC: Token
kenCollector) Operation: Collect tokens appearing on the surface of the cube to form a screen. Per one token (Cm to 18Ct)/N”
If it is not captured faster, it will cause throughput to decrease. (llJ6)3.2.1.5. Inter-chip communication unit (C7: ChipTrans) Configuration: Consists of a controller with a bus and queue connected to the processor at the end of the chip.

(Figure 7) Operation: Serially outputs tokens sent via the bus. The recipient of the token passes it to the processor within the chip based on the address the token has.

Two-way communication possible It is necessary to do so.

[Overview of three-dimensional wiring] Each processor is connected to processors in six directions. Therefore, it is better to arrange the actual chips three-dimensionally.
By regularly attaching connectors for connection in the vertical direction as shown in FIG. 8, boards can be stacked and connected. If the surface of the cube is also built-in, it is possible to increase the memory capacity using the same substrate.

(Figure 9) 3.2.2. In order to obtain an image based on the setting that the screen of the operation monitor is composed of L2 pixels, it is only necessary to obtain information about what kind of display each pixel should perform. Create the corresponding token,
Pass them along with the appropriate direction vector to the processor at the appropriate position on the surface of the PEARY (token delivery part), the position and vector being calculated from the viewpoint coordinates and the viewing direction vector. The processor that receives the token performs a line-of-sight search in its own memory space,
The obtained information is added to the token and passed to the next processor (processor section).Which of the six processors will become the next processor is calculated based on the direction vector of the token. Such a process is repeated, and tokens eventually appear on the surface of PEARY (cubic surface section).By collecting information on these tokens, an image is constructed (token collection section).

It is also possible to calculate images from multiple viewpoints at the same time.

In that case, you can attach data indicating your affiliation to the token and identify it when composing the image.

3.2.3. Example 3.2.3.1. When implemented with a single processor and a single chip (5PSC: 5in81e Process on
5in81eChip) First, consider the case where one processor is assigned to one CPU chip, and one SubPEARY is assigned to one memory chip.

This is the case when implementing this system using existing chips. (Note that it is not possible to put multiple 5ubPEARS into one memory chip, because each 5ubPEARY must be able to be accessed in parallel.) In this case, the production cost is proportional to the number of chips. increases. Therefore, due to production cost limitations, the realistic number of chips will be on the order of your choice.

For this number of processors, s u b P E
It will be understood from the later discussion that the processing time is proportional to the size of ARY. Therefore, it is necessary to evaluate the length of processing time when using as many chips as the cost allows.

In this case 1=1. Furthermore, since the process leap communication and inter-chip communication are the same waveform, Ct=Ci. At this time, the total processing time to process tokens for one screen is: time=N(C1+MCm) +M2Max (Ci, MCm),...
■It is. First, the first term on the right side is that the first token is PEA
This is the time from entering the RY to coming out.

(Ci +MCm) is one s u b P E A
This is the processing time required to process the RY and pass the token to the neighboring 5ubPEARY. The second term on the right side is the time from when the first token begins to be output until when the M f& token is output. When tokens are continuously output from PEARY, the interval is Max (Ci
, MCm), the processing in 5ubPEARY and 5
Communication between ubPEARY can be done in parallel, so Ci and M
This is because the larger Cm becomes the rate-determining step. Also, the number of tokens that one 5ubPEAR should process is M
0 can be approximated by 2 (Figure 2) = 1000. Set M=50. N=L/M
=20, so it is possible. Since C1<MCm may be satisfied, t i me -M3Cm, , ■. If Cm'qlμ seconds, time#o.

1″″0.2 seconds.

3.2.3.2. When realizing multiple processors on one chip (MPSC: Multi Processor
n SingleChiP > Consider the case where multiple processors and memories can be mounted on one chip, but not all can be mounted on one chip. This is the case when designing dedicated chips. In this case, reducing 5ubPEARY does not affect the production cost.

However, the communication cost of the processor cannot be ignored; depending on the direction of the line of sight, it will be about 1.3 M'' in the case of i and evil, but this will be ignored.

Moreover, due to the limited number of terminals on a chip, as the number of processors in a chip increases, the cost of communication between chips increases (interchip communication part), thus minimizing the total processing time. It is necessary to find the size of 5ubPEARY and the number of processors on one chip, and evaluate the processing time at that time.

At this time, the total processing time for processing tokens for one screen is time=N(I (Ci+MCm)+Ctl+M”M
ax (I2Ct, MCm) - 1, the first term on the right side is the time from when the first token enters PEARY to when it comes out. Right-sidedness: The delay associated with an increase in the area occupied by the processor section is ignored. This delay is mainly due to the increase in stray capacitance due to the length of the wiring, but it can be suppressed to a negligible level if the circuit is devised.

The second term is i &
This is the time until the final token is output.

If one chip contains Ijllll processors, each processor has its own 5ubPEA.
Each time RY is processed, 12 tokens must be passed to the adjacent chip, but since the number of terminals on the chip is limited, a bottleneck occurs here. In other words, I
This will incur a communication cost of 2Ct (Figure 3), but if the time to process 5ubPEARY (MCm>) is longer, the communication cost will be absorbed.
ax (I2Ct, MCm) is the processing time of 5ubPEARY. The number of tokens that one 5ubPEAR should process can be approximated by Mll.

In an actual situation, it can be considered that C3#Ct<MCm, and if IMN=L is used, ■ becomes time=Lcm+M"Max (I", M)Cm. Since Q=IM is determined from the limits of chip manufacturing technology, time=LCm4-Max (Q2. M'
) becomes Cm. Therefore, it is better to make M sufficiently small, but if it is made too small, the inter-processor communication cost cannot be ignored. Therefore, it is preferable to use I2ζM.

Then, time=(L+Q'')Cm, 1'#IM=Q.

Q'=1000, L=1000. Cmb; assuming lμ seconds, N=10. I=5. M=20 time”=0.01
seconds.

Q'=100, L=1000. Assuming Cm#1u seconds, N=20.1-4. M=16. time#o becomes 003 seconds.

3.2.3.3. When realizing all processors on one chip (APSC: All Process on
SingleChip) Consider the case where everything is placed on one chip. To achieve this, wafer school chips will be used. In that case, taking into account the occurrence of defective parts, wires are connected not only to the front, back, left, right, top and bottom, but also to the eight processors located diagonally to avoid defective processors. For this purpose, it is necessary to prepare several layers from the surface of PEARY as a play area. In this case, there is no problem with the communication cost of the chip, so the optimal 5ubPEAR
All you have to do is find the size of the value and the processing time at that time.

At this time, the total processing time is time=I (Ci+MCm) +M’Max (Ci, MCm) , which is the same as 5 psc.

When Ci <MCm, time=Lcl/M+LCm+M'Cmdtime/
dM=-LCi/M''+3M''Cm Therefore, time is minimum when M'=LC1/3Cm.

When Ci > MCm, time=Lci/M+LCm+M'Cidtime/
dM=-LC1/M"+2MC1 Therefore, time is minimum when M rice is L/2.

Assuming Cm-1u seconds and CI=10μ seconds, L=10
00, M#8 t i m e 'i 0, O
01 seconds.

time#o at M#10 when L=10000.

01 seconds.

3.2.4. Effects of the Invention G to show the PEARY of 1000' f%: It can be done in a calculation time of 1 second or less, and is practical.

[Brief explanation of drawings]

Figure 1 is an overview of processor connections, Figure 2 is 5ubPE
A conceptual diagram of processing for each ARY, Figure 3 is a conceptual diagram showing bottlenecks in interchip communication, Figure 4 is a configuration diagram of the processor section, Figure 5 is a configuration diagram of the cube surface section, and Figure 6 is token collection. Fig. 7 is a block diagram of the inter-chip communication section.
FIG. 8 is a schematic diagram of the three-dimensional wiring connector, and FIG. 9 is a configuration diagram of the entire system. chlpl, MCm10Cf Country 3 hlp2 ``FJ rear left, right, top and bottom view 4 ath figure figure 5 Relationship with the case of the person who amends the construction method of an image display device Address of the patent applicant 6, Item 7 of “1. Title of the invention” and “3. Detailed description of the invention” of the specification subject to the amendment, Contents of the amendment Amend "device" in line 2 of page 1 to "invention." Amend "device" in line 1 of page 2 to "invention."

Claims (1)

[Claims] In order to display rasterized three-dimensional images at high speed through distributed processing, multiple processors that share the three-dimensional raster space in memory are connected in a cubic grid, and each processor corresponds to a pixel on the screen. A method for configuring a computer graphics display device, comprising processing tokens and assembling the tokens to configure an image.