JP5610603B1 - VLSI circuit, parallel computing system and computer system - Google Patents

Abstract

To provide a parallel computing system capable of transferring data between arbitrary PEs and having scalability. In addition, a computer system utilizing such a parallel computing system is provided, and radiosity can be calculated on a small portable terminal device. HXNet is mounted on a VLSI, and data transfer between VLSIs is enabled by an additional BM. Scalability in which the number of VLSIs can be arbitrarily selected is realized, and radiosity can be calculated on a small portable terminal device. [Selection] Figure 2

Description

  The present invention relates to a VLSI circuit for parallel computing, a parallel computing system utilizing the VLSI circuit, and a computer system utilizing the parallel computing system.

Parallel computing systems aimed at speeding up computation by parallelizing computation have been researched and developed for decades.
In a parallel computing system, a plurality of calculation elements called PEs (corresponding to CPUs) are used, each PE performs calculations independently, and transfers calculation result data to other PEs. Here, since a transfer bus is required for data transfer, it is not easy to construct hardware in calculations that require a large amount of data transfer.

  For example, in the case of obtaining a numerical solution of a differential equation representing the diffusion of a substance (performing Laplacian calculation), each PE is calculated at one coordinate in the space, and is calculated at a nearby coordinate (if it is two-dimensional) Since it is sufficient to transfer data only to four (three in the case of three dimensions), a configuration in which the number of buses is not increased was possible. However, in radiosity calculation in image processing performed in recent mobile terminal devices, if each PE performs calculations on one small plane, data transfer may be required between all PEs. For this reason, in a conventional parallel computing system, sufficient high-speed computation has not been realized.

  As a method for solving the problem of data transfer between PEs, for example, Patent Document 1 discloses a parallel computing system having a communication network that specially executes data transfer. However, the construction of such a communication network requires a great deal of cost.

  In Patent Document 2, a memory corresponding to each PE arranged two-dimensionally corresponds to a bus having three or more ports, and a wide range of data transfer can be performed via a third port exceeding two dimensions. A parallel computing system for performing is disclosed. However, the specific implementation of data transfer over the third port must be individually designed.

As a parallel computing system in which PEs are arranged two-dimensionally and data transfer between arbitrary PEs is possible, one based on HXNet (Non-patent Document 1) has been known. m As ² PE (i, j) (1 ≦ i ≦ m, 1 ≦ j ≦ m), data transfer is performed in the order of PE (i, j) → PE (j, k) → PE (k, l). By doing so, it is possible to transfer data between arbitrary PEs. HXNet is a useful one that is guaranteed to be implemented.

On the other hand, in HXNet, the number of PEs is limited to m ² , and a large HXNet cannot be configured by combining a plurality of HXNets. There was no scalability to scale up small things later.

Japanese Patent Laid-Open No. 06-052125 Japanese Patent Application Laid-Open No. 06-075930

Massively parallel VLSI computer by Hiroshi Renda Industrial Research Committee

An object of the present invention is to provide a parallel computing system capable of transferring data between arbitrary PEs and having scalability.
It is another object of the present invention to provide a computer system that utilizes such a parallel computing system and to enable calculation of radiosity on a small portable terminal device.

  A small-scale HXNet is realized by a VLSI circuit. The VLSI circuit includes an additional BM for transferring data to another VLSI circuit in addition to the BM used for HXNet (BM represents “buffer memory”). Thereby, an arbitrary number of VLSIs can be combined to constitute a parallel computing system, and data transfer between arbitrary PEs becomes possible.

The VLSI circuit of the present invention is
HXNet containing m ² PEs and m ³ BMs;
It is characterized by mounting m ² (n−1) additional BMs.

  HXNet is mounted on the VLSI, and an additional BM for data transfer with other VLSI is further mounted. Here, m and n are integers of 2 or more.

The parallel computing system of the present invention includes:
Including n VLSI circuits mounted with HXNet including m ² PEs and m ³ BMs and m ² (n−1) additional BMs ,
M and n are integers of 2 or more;
In each VLSI circuit, the additional BM includes m ² sets of (n−1) additional BMs writable from each of the m ² PEs in the HXNet,
The m ² sets of the additional BM are ordered, and a PE that can be written to the i-th additional BM is represented as an i-th PE (i is an integer of 1 to m ² ),
The (n-1) additional BMs (a set of additional BMs) are ordered,
The kth order additional BM of the i-th set BM of the jth order VLSI circuit is the kth order (when k <j) or the (k + 1) th order (when k ≧ j). It can be read by the i-th PE of the VLSI circuit.

  Data transfer destination buses from each additional BM are determined, and buses between VLSIs are reduced.

The parallel computing system of the present invention includes:
When the i-th PE of the k-th order VLSI circuit is represented as PE (k, i), the data transfer from PE (k ₁ , i ₁ ) to PE (k ₂ , i ₂ )
(1) If k ₁ = k ₂ , k is executed by the HXNet in the _first VLSI circuit,
(2) If k ₁ ≠ k ₂ and i ₁ = i ₂ , PE (k ₁ , i ₁ ) writes data to a predetermined additional BM, and PE (k ₂ , i ₁ ) reads the data. Executed,
(3) If k ₁ ≠ k ₂ and i ₁ ≠ i ₂ , PE (k ₁ , i ₁ ) writes data to a predetermined additional BM, and the data is read by PE (k ₂ , i ₁ ), k the HXNet in _second VLSI circuit, characterized in that it is executed by being transferred to the _{PE (k 2, i 2)} .

  A specific data transfer procedure is given.

The computer system of the present invention
A main body CPU, the parallel computing system described above, and an interface circuit between the main body CPU and the parallel computing system are provided.

  A parallel computing system based on VLSI can be handled as one device when viewed from the main body CPU.

The computer system of the present invention
Radiosity is calculated using the parallel computing system.

  In the calculation of radiosity, there are many data transfers between PEs. The computer system of the present invention is effectively used.

The computer system of the present invention
Runs on a mobile terminal device,
Radiosity is calculated for image display in game applications.

  It is a parallel computing system with scalability and can be used in mobile terminal devices, especially in games.

  According to the present invention, there are provided a parallel computing system capable of transferring data between arbitrary PEs and having scalability, and a computer system utilizing such a parallel computing system.

FIG. 1 is a diagram showing a VLSI circuit. FIG. 2 is a diagram illustrating a parallel computing system using a plurality of VLSI circuits. FIG. 3 is a diagram illustrating the configuration of the computer. FIG. 4 is a diagram showing a radiosity calculation procedure.

  In the following, examples of the present invention will be described with an example of m = 2 and n = 3. The same operation is performed even if m and n are other values.

FIG. 1 is a diagram showing a VLSI circuit. The VLSI circuit 1 is mounted with HXNet 2 and eight additional BMs (ABMs) 4. HXNet2 has 4 (= 2 ² ) PE3 and 8 (= 2 ³ ) BMs. In addition to this, the VLSI circuit 1 includes eight ABMs. The eight ABMs are two ABMs (i, j) that can be read and written from each of the four PEs (i) (i = 1,..., J = 1, 2).

  The eight ABMs have a bus grouped for each j (for each order (for each j) related to each PM, not for each PR (for each i) to be read and written). Of course, each ABM has a separate bus, but each group has a bus (path to the outside of the VLSI circuit) in substantially the same direction.

One VLSI circuit constitutes an HXNet composed of 4PE, and operates as a parallel computing system. Although the 4PE in this embodiment, 9PE, 16PE, 25PE, any other number of PE (However, m a and ^{m 2} pieces of PE as an integer of 2 or more) may be.

  FIG. 2 is a diagram illustrating a parallel computing system using a plurality of VLSI circuits. In this embodiment, a 12PE (4PE × 3) parallel computing system using three VLSI circuits 1 is shown, but a parallel computing system using four or more VLSI circuits 1 can be similarly constructed.

  There are three VLSI circuits 1a, 1b, and 1c. A bus 5ab that connects the VLSI circuits 1a and 1b, a bus 5bc that connects the VLSI circuits 1b and 1c, and a bus 5ca that connects the VLSI circuits 1c and 1a are provided.

The buses 5ab, 5bc, and 5ca collectively represent four buses related to four ABMs. Each bus is connected as follows. For example, of the bus 5ab, the bus from the ABM (1,2) of the VLSI circuit 1a is connected to the ABM (1,1) and / or PE1 of the VLSI circuit 1b. When connecting the ABM (i ₁ , j ₁ ) of one VLSI circuit to the ABM (i ₂ , j ₂ ) or PEi ₂ of the other VLSI circuit, the relationship of i ₁ = i ₂ is maintained. In this way, PEs having the same number or ABMs related thereto are connected.

  Here, data may be copied between ABMs connected by a bus (mirroring between ABMs) or data may be transferred to the PE without rewriting the connected ABM. The purpose is to transfer the data to the PE, and it is not essential whether it is via the ABM.

Here, it is important to maintain the relationship of i ₁ = i ₂ . In HXNet, the number of PEs is m ² , and PEs are numbered by i and j that take values of 1 to m, so transfer from PE (i, j) to PE (j, k). In this case, PE (j, k) exists regardless of the value of j. However, in the present invention, when the number n of VLSI circuits is smaller than m, there is a possibility that the “j-th VLSI” does not exist for the j-th PE of the i-th VLSI. Transfer from PE (i, j) to PE (j, k) is not guaranteed. For this reason, i is assumed to be the order of PEs in each VLSI, and it is guaranteed that the transfer destination PE exists.

As described above, an arbitrary number of VLSI circuits 1 mounted with m ² (n−1) additional BMs can be connected up to a maximum of n, and data transfer between arbitrary PEs is realized. can do. Hereinafter, data transfer between arbitrary PEs will be described. When the i-th PE of the k-th order VLSI circuit is represented as PE (k, i), data transfer from PE (k ₁ , i ₁ ) to PE (k ₂ , i ₂ ) is performed according to the following procedure. Done.

If k ₁ = k ₂ , it is executed by the HXNet in the k _1st VLSI circuit. That is, data transfer by HXNet in the same VLSI.

If k ₁ ≠ k ₂ and i ₁ = i ₂ , PE (k ₁ , i ₁ ) writes data to a predetermined additional BM, and the data is read by PE (k ₂ , i ₁ ). . That is, data transfer via ABM and bus is possible between PEs in the same order in the VLSI.

If k ₁ ≠ k ₂ and i ₁ ≠ i ₂ , PE (k ₁ , i ₁ ) writes data to a predetermined additional BM, and the data is read by PE (k ₂ , i ₁ ), and the k _2nd This is executed by being transferred to PE (k ₂ , i ₂ ) by HXNet in the VLSI circuit. That is, after performing data transfer via the ABM and the bus, data transfer is performed by HXNet in the transfer destination VLSI.

  The VLSI circuit and its connection have been described above. Next, an interface circuit for realizing a parallel computing system will be described. However, the interface circuit may be the same as that disclosed in Non-Patent Document 1, and can be developed by ordinary knowledge in the technical field to which the present invention belongs without special description.

  FIG. 3 is a diagram illustrating the configuration of the computer. The computer includes a main CPU 6 and a VLSI circuit 1 for parallel computing, which are connected by an interface circuit 7. Here, the VLSI circuit 1 may be a single VLSI or a combination of a plurality of VLSIs as described above.

  The interface circuit 7 can be handled as one input / output device for the main CPU 6 as in the case of data storage. This is because some data is given and some data is received.

  The interface circuit 7 receives data (including program instructions) from the main CPU 6, causes the VLSI circuit 1 to perform parallel computing, and returns the calculation result to the main CPU 6. For this purpose, an IF-memory for storing data and an IF-CPU for controlling the operation of the VLSI circuit 1 are provided. In accordance with the instructions of the program received from the main CPU 6, data is given to each PE of the VLSI circuit 1 to instruct calculation.

  The computer that can perform parallel computing has been described above. Next, calculation of radiosity executed by the computer will be described.

  The calculation of radiosity is a calculation to obtain an image. Unlike conventional ray tracing, the reflection on the small plane that represents the surface of the object without tracking individual rays is related to other small planes. It is characteristic to calculate.

The reflectance of the xth facet is R _x , and the angular relationship between the xth facet and the yth facet (the rate at which the light reflected by the xth facet reaches the yth facet). When F _xy , the light energy radiated from the xth small plane is B _x , and the initial radiated light energy is E _x , the following equation is established. Note that R _x and F _xy may be calculated for each hue on the assumption that they differ depending on the hue.
Here, R _x is a constant determined by the material of the object surface, and E _x is a constant determined by the initial radiation light (light source). The calculation of F _xy and B _x is central to the calculation of radiosity.

FIG. 4 is a diagram showing a radiosity calculation procedure. First, F _xy is obtained, and then B _x is obtained. Here, the parallel calculation is effective in the step 8a for _obtaining F _xy and the step 8b for obtaining B _x .

Since F _xy depends on the angular relationship between the xth _facet and the yth _facet , F _xy can be calculated based only on information about the xth facet and the yth facet. That is, when the number of small planes is p, p (p−1) / 2 F _xy values are calculated, but they can be independently calculated in parallel. According to the parallel computing system including m ² n PEs, the calculation time is expected to be (1 / m ² n).

The calculation of B _x includes a method of sequentially calculating based on the above equation 1 (substituting the calculation result of the right side into the left side) and a method of solving the above equation 1 by linear matrix equations by inverse matrix calculation.

In the case of sequential computation, B _x for each x can be computed independently of those for the other x. Parallel calculation is effective.

In the case of inverse matrix calculation, parallelized calculation can be effectively utilized by the method described in Non-Patent Document 1. Here, most of the values of F _xy are non-zero, and the matrix to be subjected to inverse matrix calculation is dense, so that the effect of parallel calculation is great.

As described above, a scalable parallel computing system that can use an arbitrary number of HXNet VLSI circuits 1 having m ² PEs has been realized. In addition, a computer system utilizing this parallel computing system and calculation of radiosity executed in the computer system are shown. This realizes the use of a parallel computing system in portable terminals and the like.

  Since the parallel computing system of the present invention has scalability, it can be used for a small portable terminal device (in this case, a VLSI circuit having a small m) or a large computer (in this case). VLSI circuits with large m and n are used.), and can also be used for game machines and other devices.

  A parallel computing system capable of transferring data between arbitrary PEs and having scalability, and a computer system utilizing such a parallel computing system. Expected to be used by many mobile terminal manufacturers and computer manufacturers.

  In addition, the calculation of radiosity is also realized in portable terminals and the like, and it is expected to be used by many software developers.

1 ... VLSI circuit 2 ... HXNet
3 ... PE
4 ... Additional BM
5 ... Bus 6 ... Main CPU
7 ... Interface circuit 8 ... Parallelization step

Claims (6)

HXNet containing m ² PEs and m ³ BMs;
implement m ² (n−1) additional BMs,
The VLSI circuit, wherein m and n are integers of 2 or more . Including n VLSI circuits mounted with HXNet including m ² PEs and m ³ BMs and m ² (n−1) additional BMs ,
M and n are integers of 2 or more;
In each VLSI circuit, the additional BM includes m ² sets of (n−1) additional BMs writable from each of the m ² PEs in the HXNet,
The m ² sets of the additional BM are ordered, and a PE that can be written to the i-th additional BM is represented as an i-th PE (i is an integer of 1 to m ² ),
The (n-1) additional BMs (a set of additional BMs) are ordered,
The kth order additional BM of the i-th set BM of the jth order VLSI circuit is the kth order (when k <j) or the (k + 1) th order (when k ≧ j). The parallel computing system is readable by the i-th PE of the VLSI circuit. When the i-th PE of the k-th order VLSI circuit is represented as PE (k, i), the data transfer from PE (k ₁ , i ₁ ) to PE (k ₂ , i ₂ )
(1) If k ₁ = k ₂ , k is executed by the HXNet in the _first VLSI circuit,
(2) If k ₁ ≠ k ₂ and i ₁ = i ₂ , PE (k ₁ , i ₁ ) writes data to a predetermined additional BM, and PE (k ₂ , i ₁ ) reads the data. Executed,
(3) If k ₁ ≠ k ₂ and i ₁ ≠ i ₂ , PE (k ₁ , i ₁ ) writes data to a predetermined additional BM, and the data is read by PE (k ₂ , i ₁ ), k _3. The parallel computing system according to claim 2, wherein the parallel computing system is executed by being transferred to PE (k ₂ , i ₂ ) by HXNet in the second VLSI circuit.   A computer system comprising: a main body CPU; a parallel computing system according to claim 3; and an interface circuit between the main body CPU and the parallel computing system.   The computer system according to claim 4, wherein radiosity is calculated using the parallel computing system. Runs on a mobile terminal device,
And performing the radiosity calculations image display definitive the game application, the computer system according to claim 5.