JPH02123432A - Hardware expression/description system and its simulation system - Google Patents
Hardware expression/description system and its simulation systemInfo
- Publication number
- JPH02123432A JPH02123432A JP27881488A JP27881488A JPH02123432A JP H02123432 A JPH02123432 A JP H02123432A JP 27881488 A JP27881488 A JP 27881488A JP 27881488 A JP27881488 A JP 27881488A JP H02123432 A JPH02123432 A JP H02123432A
- Authority
- JP
- Japan
- Prior art keywords
- action
- entity
- history information
- operating
- startup
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004088 simulation Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 claims abstract description 49
- 230000008569 process Effects 0.000 claims abstract description 38
- 230000007704 transition Effects 0.000 claims abstract description 17
- 230000009471 action Effects 0.000 claims description 78
- 230000004913 activation Effects 0.000 claims description 13
- 230000006870 function Effects 0.000 claims description 9
- 230000007246 mechanism Effects 0.000 claims description 2
- 230000003542 behavioural effect Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- 230000003068 static effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Landscapes
- Advance Control (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野」
この発明は高度な並列動作を行うハードウェアの設計・
記述・検証に適した記述性の高いハードウェア表現・記
述方式と解析性の高いシミュレーション方式に関するも
のである。[Detailed Description of the Invention] "Industrial Application Field" This invention relates to the design and development of hardware that performs highly parallel operations.
It concerns hardware representation/description methods with high descriptive properties suitable for description and verification, and simulation methods with high analytical performance.
「従来の技術」
従来のハードウェア記述方式は、動作主体、動作客体の
明確な区別が’JNI: <、また記述対象に含まれる
構成要素間の接続などの静的な関係の記述と、使用11
10序などの動的な関係の記述の混在を許[2ていたた
めに、シ5.J、lノージョン時に、ある動作客体がど
のような状況でどの動作」2体から使用されたかを゛特
定−することができ−「、このために特に複親なj)U
列動作を行う設計において、ある動作客体(゛二対する
不当な競合などの設計誤りf二対する原因の解析な困翔
としでいた。``Conventional technology'' Conventional hardware description methods have a clear distinction between action subjects and action objects, and also describe static relationships such as connections between components included in the description target, 11
Mixing of descriptions of dynamic relationships such as 10 ordination is allowed [2], so 5. J, l At the time of nosion, it is possible to specify in what situation and which action a certain action object was used by two objects.
In the design of sequential motion, it has been difficult to analyze the causes of design errors such as unfair competition between a certain motion object (f2).
この発明の1]的は従来のハードウェア記述方式お、L
びそのシミコレ−ジョン方式の、高並列動作ハードウェ
アに対する検証性の低さを解決した、様々な検証を行う
に十分な情報をシミ、・レータに提供できるハードウェ
ア記述方式とこれを利用して様々な検証を実施できるシ
ミュレーション方式を提供することにある。1] The purpose of this invention is the conventional hardware description method, L
This solves the low verifiability of the Simicollation method for highly parallel operating hardware, and provides a hardware description method that can provide the Simicollation method with sufficient information to perform various verifications. The purpose of this research is to provide a simulation method that allows for accurate verification.
「課題を解決°1−るだめの手段−1
この発明は記述すべきハードウェア対象を、制メ)1)
を司る動作上体複数個と、その制御の対象である動作客
体複数個とに分け、ハードウェアの機能・構造・動作を
、動作上体1−よる動作8:体の使用と、動作主体から
他の動作上体の起動ど、動作主体から他の動作上体への
動「1の遷移と、動作上体の動作の終了どの順序(二よ
り表現17、か・つこれをシミュレーションで利用する
ことを最も−iE要な特徴とし、従来の技術とは、接続
ないl−2は静的4[記述を排除した点が大きく植:な
る。``Solving the Problem 1 - Means of Solving - 1 This invention solves the problem by defining the hardware object to be described.1)
The function, structure, and operation of the hardware are divided into multiple motion bodies that control the motion, and multiple motion objects that are the objects of control, and the functions, structures, and operations of the hardware are explained from the motion body 1 to the motion 8: body use and motion objects. Activation of other moving bodies, transition from the moving body to other moving bodies, and the order in which the movements of the moving bodies end (Expression 17 from 2) This is used in the simulation. This is the most important feature, and it differs greatly from the conventional technology in that it eliminates the static 4[description].
[゛実施例−1
第1ド1はこの発明の特許請求の範囲(])に係わる内
容の実施例を説明する図であっ′C1全体はこの発明(
二よるあるバードウコア記述形式(二上って記述された
ハードウェアの記述例の全体を示している。この中で1
は動作客体定義部、2は動作上体定義部、3は動作上体
定義部内での動作客体使用順序の記述形式、4は動作上
体間での動作上体から他の動作主体の起動形式、5は動
作上体から他の動作上体への動作の遷移形式、6は動作
上体の動作の終了形式である1、す、下この形式≦1合
わせ動作上体から他の動作主体の起動、動作−1体から
他の動作主体への動作の遷移、動作主体の動作の終了は
、各々generate、relay、finishと
呼ぶo uSeAは動作上体aが動作客体Aを使用する
ことを意味し、generate bは動作上体aが動
作上体すを起動することを表わし、relay cは動
作上体aから動作4ミ体Cへ動作の遷移を表わす。[゛Example-1 The first part 1 is a diagram illustrating an example of the content related to the claims (]) of this invention.
A certain Bird Core description format based on 2 (2 shows the entire hardware description example described above.
is the action object definition part, 2 is the action object definition part, 3 is the description format of the order of use of action objects within the action object definition part, and 4 is the activation format of another action object from the action object between action objects. , 5 is the transition form of the action from the action upper body to another action upper body, and 6 is the termination form of the action upper body action. Activation, action - The transition of an action from one action object to another action object, and the end of the action of an action object are called generate, relay, and finish, respectively. o uSeA means that action object A uses action object A. However, generate b represents that the action body a activates the action body A, and relay c represents the transition of the action from the action body a to the action body C.
動作の客体としては普通、レジスタや加算器のよう(二
簡単な機能(レジスタは値の1吊持機能、加算器は値の
)J[1算機能)と直接対応するものを選ぶ。As an object of operation, we usually choose something such as a register or an adder that directly corresponds to a simple function (a register is a function that holds one value, an adder is a function that holds one value), and an arithmetic function).
動作4三体は制御回路に対応させる。パイプライン計算
機では各ステージ毎の制御回路を各々動作上体どする。Operation 4 The three bodies correspond to the control circuit. In a pipeline computer, each stage has its own control circuit.
個々の動作上体の機能は動作客体の使用順序を記述する
こと(二より表現する。The function of each action object is expressed by describing the order of use of action objects (expressed from the second point).
−・一方、複数の動作上体Cよる並列制御は、動作主体
間での動作上体から他の動作主体の起動(genera
te )、動作上体から他の動作上体への動作の遷移(
relay )、動作主体の動作の終了(finish
)−二よって表現する。- On the other hand, parallel control by multiple operating bodies C is the activation of other operating subjects from the operating bodies between the operating subjects.
te ), the transition of movement from one working body to another working body (
relay ), the end of the action of the action subject (finish
)−2.
generateでは起動元動作上体の動作は引続き行
、1′)れ、起動元の動作上体は、起動元の動作上体の
処理の一部を分担して行う。relayでは遷移先動作
上体の動作は終了し、残りの処理は遷移先動作上体が行
う。finishはその動作上体(1任された処理の実
施が終了したことを表す。In generate, the operation of the activation source behavioral body continues (1'), and the activation source behavioral body shares part of the processing of the activation source behavioral body. In relay, the motion of the transition destination behavioral body ends, and the remaining processing is performed by the transition destination behavioral body. Finish indicates that the execution of the task has been completed.
例えばハードウェアの並列動作度を同一トさせる置いて
きぼり制御や並列制御にはgenerateとfini
shを、パイプライン制御にはre layとfini
shを適用する。For example, generate and fini are used for leave-behind control or parallel control that keeps the parallelism of hardware the same.
sh, re lay and fini for pipeline control
Apply sh.
次に化2図1はこの発明の特許請求の範囲(2)c1係
わる内容の実施例を説明する肉であって、シミ、−4レ
一シヨン時のプロセスより(仕事(二付けられた番号)
と起動履歴情報の1吊持方式を示しており、7はプロセ
スID、8は起動履歴情報である。動作中の動作上体の
みがプロセスIDと起動履歴情報を保持している。Next, Figure 2 shows an example of the content related to claim (2) c1 of the present invention, and it shows stains, -4 ratios (work (2) numbered )
7 shows the process ID and 8 is the startup history information. Only the operating body that is in operation retains the process ID and activation history information.
起動履歴情報内に保持−Cきる起動元プロセスIDの数
(二制限は無い。プロセスIDは、例えばシミュレーシ
ョン開始時刻から新たにプロセスIDが必要どなる度(
1順に1.2,3. ・ど付与される。The number of startup source process IDs that can be retained in the startup history information (there is no limit to 2).The process ID can be saved, for example, every time a new process ID is required from the simulation start time (
1, 2, 3 in order.・Granted.
動作主体aから他の動作上体すを起動する場合(gen
erate )は、起動元動作主体aの起動履歴情報に
起動元動作上体のプロセスID(プロセスID=1)を
加えて起動先動作主体すの起動履歴情報とすると共に起
動先動作主体すのプロセスIDとして新たな番号(プロ
セスID:2)を割付ける。When starting another operating entity from operating entity a (gen
erase ) adds the process ID (process ID = 1) of the startup entity to the startup history information of the startup entity a to obtain the startup history information of the destination entity a, and also creates the process of the destination entity a. A new number (process ID: 2) is assigned as the ID.
動作主体aから他の動作主体Cへの動作の遷移の場合(
relay )は、遷移先動作主体aの起動履歴情報(
プロセスID:X)を遷移先動作生体Cの起動履歴情報
とすると共に遷移元動作主体aのプロセスID(プロセ
スID:l)を遷移先動作主体CのプロセスIDとする
。In the case of a transition of an action from an action entity a to another action entity C (
relay ) is the activation history information (
Let process ID:
動作主体の動作の終了ではプロセスIDと起動履歴情報
を削除する。At the end of the operation of the operator, the process ID and activation history information are deleted.
このような仕組みにより、一つの処理が複数の動作主体
を遷移しながら実施されるパイプライン制御ではプロセ
スIDが変化せず、また置いてきぼり制御や並列制御で
は新たなプロセスIDが割り付けられると共にどのよう
な処理の一部を分担しているのかは起動履歴情報の中の
プロセスIDの中に残される。With this mechanism, the process ID does not change in pipeline control, where one process is executed while transitioning between multiple operating entities, and in left-behind control and parallel control, a new process ID is assigned and the Whether a part of the processing is shared is left in the process ID in the activation history information.
この結果として多くの動作主体(制御部)の協調作業籠
:よって実施されるハードウェアの複雑な同時動作を、
機能に直結したプロセスIDによって管理・分類するこ
とができる。As a result, the cooperative work of many operating entities (control units): thus, the complicated simultaneous operations of the hardware,
They can be managed and classified using process IDs that are directly linked to functions.
「発明の効果」
以上説明したよう(二、この発明によれば設計・記述さ
れたすべての動作に対し、その原因となる動作主体並び
にプロセスIDが対応するため(=、あるレジスタに予
期せぬ値が書き込まれた、同一組合せ回路の利用競合が
発生したといった設計誤りを検出した状況で、直ちにシ
ミュレータからその誤りの原因となった動作主体ならび
にプロセスIDを出力させることができるから、誤りの
解析をより効率的に行える利点がある。``Effects of the Invention'' As explained above (2. According to this invention, for every designed and written operation, the action entity and process ID that cause it correspond. When a design error is detected, such as a value being written or a conflict in the use of the same combinational circuit, the simulator can immediately output the operating entity and process ID that caused the error, making it easier to analyze the error. This has the advantage that it can be done more efficiently.
第1図はこの発明によるあるハードウェア記述形式(二
よって記述されたハードウェアの記述例の全体を示す図
、第2図はシミュレーシヨン時のプロセスIDと起動履
歴情報の作詩方式を示す図である。
1:動作客体定義部、2:動作主体定義部、3:動作主
体定義部内での動作客体使用順序の記述形式、4:動作
主体間での動作主体から他の動作主体の起動形式、5:
動作主体から他の動作主体への動作の遷移形式、6:動
作主体の動作の終了形式、7:プロセスID、8:起動
履歴情報。Figure 1 is a diagram showing an entire hardware description example written using a certain hardware description format (2) according to the present invention, and Figure 2 is a diagram showing a method of writing process ID and startup history information during simulation. 1: Action object definition section, 2: Action object definition section, 3: Description format of action object usage order within the action object definition section, 4: Invocation format from one action object to another action object among action objects. 5:
Transition format of an action from an action entity to another action entity, 6: Termination format of an action of an action entity, 7: Process ID, 8: Activation history information.
Claims (2)
主体複数個と、その制御の対象である動作客体複数個と
に分け、ハードウェアの機能・構造・動作を、動作生体
による動作客体の使用と、動作主体から他の動作主体の
記憶と、動作生体から他の動作生体への動作の遷移と、
動作主体の動作の終了との順序により表現することを特
徴とするハードウェアの表現・記述方式。(1) Divide the hardware object to be described into a plurality of action subjects that control control and a plurality of action objects that are the objects of control, and explain the function, structure, and operation of the hardware as described by the action objects by the action living body. use, memory of an action subject to another action subject, transition of action from an action organism to another action organism,
A hardware representation/description method characterized by representing the order of the end of the action of the action subject.
IDとどのプロセスIDから起動されたかの履歴とを記
憶する機構を設け、動作主体から他の動作生体を起動す
る場合には、起動元動作主体の起動履歴情報に起動元動
作主体のプロセスIDを加えて起動先動作主体の起動履
歴情報とすると共に起動先動作主体のプロセスIDとし
て新たな番号を割付け、動作主体から他の動作主体への
動作の遷移の場合には、遷移元動作主体の起動履歴情報
を遷移先動作主体の起動履歴情報とすると共に遷移元動
作主体のプロセスIDを遷移先動作主体のプロセスID
とすることにより、動作客体のどのような使用も、その
直接の実施元動作主体ならびに、その動作主体を動作さ
せたことにより原因を作ったプロセスIDを特定し、ま
た特定のプロセスIDを持つ動作生体ならびにそのプロ
セスIDを起動履歴情報にふくむ全ての動作主体が実施
した全ての動作客体の使用を特定できることを特徴とす
るシミュレーション方式。(2) A mechanism is provided on the simulator to store the process ID and the history of which process ID has been started for each operating entity, and when an operating entity starts another operating organism, the starting operating entity Adding the process ID of the starting action entity to the startup history information of the startup action entity to create the startup history information of the startup action entity, and assigning a new number as the process ID of the startup action entity, and instructing the action from the action entity to another action entity. In the case of a transition, the startup history information of the transition source action entity is set as the startup history information of the transition destination action entity, and the process ID of the transition source action entity is set as the process ID of the transition destination action entity.
By doing so, any use of an action object identifies the action object that directly executed it, the process ID that caused the action by operating that action object, and the action object with a specific process ID. A simulation method characterized in that it is possible to specify the use of all action objects carried out by all action subjects whose activation history information includes living organisms and their process IDs.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27881488A JPH02123432A (en) | 1988-11-02 | 1988-11-02 | Hardware expression/description system and its simulation system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27881488A JPH02123432A (en) | 1988-11-02 | 1988-11-02 | Hardware expression/description system and its simulation system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02123432A true JPH02123432A (en) | 1990-05-10 |
Family
ID=17602532
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27881488A Pending JPH02123432A (en) | 1988-11-02 | 1988-11-02 | Hardware expression/description system and its simulation system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02123432A (en) |
-
1988
- 1988-11-02 JP JP27881488A patent/JPH02123432A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE102008005515A1 (en) | Virtual architecture and virtual instruction set for the calculation of parallel instruction sequences | |
JPS63291134A (en) | Logically integrated circuit | |
CA1182579A (en) | Bus sourcing and shifter control of a central processing unit | |
JP3318051B2 (en) | Translation processing method | |
JPH02123432A (en) | Hardware expression/description system and its simulation system | |
Zozulya et al. | Algorithmization of the software testing system based on finite automata. | |
Yaroshko et al. | Multithreaded evolutionary computing | |
JPH07271755A (en) | Data driven type information processor | |
JPH04503125A (en) | Modular Black Boat Base Expert System | |
Waldschmidt et al. | FPGA synthesis for cellular processing | |
JPH0644389A (en) | Data driving information processor | |
Brooker | Further autocode facilities for the Manchester (Mercury) computer | |
Igel et al. | An example of communicating production systems | |
JPH0769831B2 (en) | Register allocation method in compiler | |
JPS58225469A (en) | Multi-processor controlling system | |
Ishijima et al. | A Small Engineering Workbench On A Personal Computer | |
JPS6365530A (en) | Code optimizing system | |
JPH09288506A (en) | Sequence control circuit capable of programming | |
JPH03119472A (en) | Vector register allotment system | |
JPH02110636A (en) | Debugging device for tag architecture machine and its compiler | |
JPS63289648A (en) | Production system | |
JPS61123904A (en) | Logic arithmetic device | |
JPH03148730A (en) | Process queue processing system | |
JPH06337789A (en) | Rule execution system of event driven type inference shell | |
JPH04149738A (en) | Program optimization device |