JPS61123904A - Logic arithmetic device - Google Patents
Logic arithmetic deviceInfo
- Publication number
- JPS61123904A JPS61123904A JP59244448A JP24444884A JPS61123904A JP S61123904 A JPS61123904 A JP S61123904A JP 59244448 A JP59244448 A JP 59244448A JP 24444884 A JP24444884 A JP 24444884A JP S61123904 A JPS61123904 A JP S61123904A
- Authority
- JP
- Japan
- Prior art keywords
- pointer
- address
- program
- sub
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/18—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form
- G05B19/4093—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Geometry (AREA)
- Human Computer Interaction (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Programmable Controllers (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はディジタル計算機によるシーケンサに係り、特
に1類似の論理を多数含むシーケンサに好適な論理演算
装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a sequencer using a digital computer, and more particularly to a logic operation device suitable for a sequencer including a large number of logics similar to one.
従来のディジタル計算機によるシーク/すにおいて、同
等の論理を複数個もつシーケンサを実現する手段として
は、(1)共通の論理演算式を定義し九プログラムを一
つ作成し、上位計算機を用いてこの共通論理演算式プロ
グラムに固有なパラメータを付加、編集して個々の論理
を生成する方法、(2)共通の論理演算式を一つの演算
要素として解釈し演算するよう、実行プログラムの中に
組み入れる方法などがある。しかし、シーク/すが完成
した後に、共通の論理演算式を変更する場合には、(1
)の方法では共通の論理演算式を使用している個々の論
理を変更するか、又は、共通の論理演算式プログラムを
変更した後、再度上位計算機を用いて個々の論理を生成
する必要があるため、労力を要するという難点がらり、
(2)の方法では、一般に、論理演算要素の接続関係を
定義する言後と異なる言後で書かれた実行プログラムを
変更する必要があるため、専門の技術を要するという難
点がある。In conventional seek/sequence using a digital computer, the means to realize a sequencer with multiple equivalent logics is (1) define a common logical operation formula, create one program, and use a high-level computer to execute this program. A method of adding and editing unique parameters to a common logical operation expression program to generate individual logic; (2) A method of incorporating a common logical operation expression into an execution program so that it is interpreted and operated as one operation element. and so on. However, if you change the common logical expression after the seek/su is completed, (1
) method, it is necessary to change the individual logics that use the common logical operation expressions, or to generate the individual logics again using a host computer after changing the common logical operation expression program. Therefore, there is a drawback that it requires a lot of effort.
The method (2) generally has the disadvantage that it requires specialized skills because it is necessary to change the execution program written after a statement different from the statement that defines the connection relationship of logical operation elements.
なお、この種の装置として関連するものには、例えば、
特開昭58−56124がある。Note that related devices of this type include, for example,
There is Japanese Patent Application Laid-Open No. 58-56124.
本発明の目的は、繰シ返し使用する共通的な論理演算式
と、容易に変更し得る論理演算方式を提供することにあ
る。An object of the present invention is to provide a common logical operation formula that is used repeatedly and a logical operation method that can be easily changed.
本発明の特徴は、繰り返し使用する共通的な論理演算式
を、一般の論理と同様の言後で基本論理演算要素の接続
関係を定義したものを一つだけもつことにより実現した
点にある。A feature of the present invention is that a common logical operation formula that is repeatedly used is realized by having only one formula that defines the connection relationship of basic logical operation elements using the same expressions as in general logic.
以下、本発明の一実施例を第1図ないし第7図によシ説
明する。An embodiment of the present invention will be described below with reference to FIGS. 1 to 7.
第1図で、論理演算式テーブル1は、基本論理演算要素
2を演算すべき順序で配列したもので構成され、末尾に
は演算全終了させるための終了要素3が置かれる。基本
論理演算要素2は、演算結果の出刃先アドレスを示す出
力パラメータ11と、例えば、論理和や論理積などの演
算の種別ごとに対応して定めた演算種別コード12と、
パラメータ個数13と、例えば、演算に用いる入力デー
タの入力元アドレスや定数などであって、この演算の種
別ととに順序と意味を定めた幾つかのパラメータ14と
から構成される。パラメータ14の数は、パラメータ個
数13に等しい。出力パラメータ11およびパラメータ
14の各々には、直接参照か間接参照かの区別を示す参
照区別フラグ20が付いている。参照区別フラグ20の
値が0のとき、直接参照であシ、出力パラメータ11、
または、パラメータ14自身がアドレスや定数であるこ
とを示す。参照区別フラグ20の値が1のとき、間接参
照であシ、副プログラムの中くだけ現われるもので、出
力パラメータ111.または、パラメータ14は、副プ
ログラムを参照した主プログラム中の基本論理演算要素
のパラメータ14の順序番号であシ、アドレスや定数は
副プログラムの出力パラメータ11、または、パラメー
タ14が指し示す主プログラムのパラメータ11の中に
存することを示す。In FIG. 1, a logical operation expression table 1 is made up of basic logical operation elements 2 arranged in the order in which they should be operated, and a termination element 3 for terminating all operations is placed at the end. The basic logical operation element 2 includes an output parameter 11 indicating the cutting edge address of the operation result, and an operation type code 12 defined corresponding to each type of operation, such as logical sum and logical product, for example.
It consists of a number of parameters 13, and several parameters 14, such as input source addresses and constants of input data used in calculations, whose order and meaning are determined by the type of calculation. The number of parameters 14 is equal to the number of parameters 13. Each of the output parameters 11 and 14 is attached with a reference distinction flag 20 indicating whether it is a direct reference or an indirect reference. When the value of the reference distinction flag 20 is 0, direct reference is allowed, output parameter 11,
Alternatively, it indicates that the parameter 14 itself is an address or a constant. When the value of the reference distinction flag 20 is 1, it is an indirect reference and only appears in the subprogram, and the output parameter 111. Alternatively, parameter 14 is the order number of parameter 14 of the basic logical operation element in the main program that referred to the subprogram, and the address or constant is the output parameter 11 of the subprogram or the main program parameter pointed to by parameter 14. 11.
第2図で、論理演算式テーブル1を逐次解釈しながら演
算するプログラムの動作を説明する。最初に、論理演算
式テーブル1の先頭アドレスをポインタPへ記憶する。The operation of a program that performs calculations while sequentially interpreting the logical operation expression table 1 will be explained with reference to FIG. First, the start address of logical operation expression table 1 is stored in pointer P.
アドレス(P+1)よシ演算種別コード12を読み、演
算種別に対応するルートへ分岐する。基本論理演算の場
合、例えば、論理和や論理積などの演算を実行し、アド
レス(P)より出力パラメータ11を読んで出刃先アド
レスへ演算結果を記憶し、アドレス(P+2 )よりパ
ラメータ個数13を読んで基本論理演算要素2の長さを
求め、ポインタPを次の基本論理演算要素の先頭まで進
める。演算種別が副プログラムへのジャンプ(CALL
)の場合、第3図で、論理演算式テーブル1のアドレス
を指すポインタPの値を別のポインタP11へ保存し、
アドレスPより副プログラムの先頭アドレスを読んでポ
インタPへ記憶する。演算種別が主プログラムへの戻り
(RETURN) の場合、第4図で、前に保存した
ポインタP8の値を、再び、ポインタPへ記憶した後、
第2図で、アドレス(P+2)よシパラメータ個数13
t−読んで基本論理演算要素2の長さを求め、ポインタ
Pを次の基本論理演算要素の先頭まで進める。このよう
に、基本論理演算要素、副プログラムへのジャンプ、主
プログラムへの戻シを各々実行した後、ポインタPの値
は次に演算すべき基本論理演算要素の先頭アドレスを指
し示しており、再び、演算種別に対応するルートへ分岐
する処理以下金繰り返すことによプ、論理演算式テーブ
ル1を逐次解釈しながら演算することになる。演算株別
が終了(END)の場合、演算プログラムは動作を終了
する。なお、基本論理演算の実行において、出力パラメ
ータ11、ま九は、パラメータ14t−参照するとき、
第1図、第5図で、参照区別フラグ20の値が01.す
なわち、直接参照の場合には、ポインタPの値が指し示
す基本論理演算要素のパラメータを参照し、参照区別フ
ラグ20の値が1、すなわち、間接参照の場合にはアド
レス(PS1+2)にポインタPの値が指し示す基本論
理演算要素のパラメータの値を加えたアドレスよシパラ
メータを参照する。Read the operation type code 12 at address (P+1) and branch to the route corresponding to the operation type. In the case of basic logical operations, for example, perform operations such as logical sum and logical product, read output parameter 11 from address (P), store the operation result in the cutting edge address, and calculate the number of parameters 13 from address (P+2). The length of basic logic operation element 2 is determined by reading, and the pointer P is advanced to the beginning of the next basic logic operation element. Operation type is jump to subprogram (CALL
), in FIG. 3, the value of pointer P pointing to the address of logical operation table 1 is saved to another pointer P11,
The start address of the subprogram is read from address P and stored in pointer P. If the operation type is return to the main program (RETURN), in FIG. 4, after the previously saved value of pointer P8 is stored in pointer P again,
In Figure 2, the address (P+2) and the number of parameters are 13.
t-read to determine the length of basic logic operation element 2, and advance pointer P to the beginning of the next basic logic operation element. In this way, after executing the basic logic operation element, jumping to the subprogram, and returning to the main program, the value of pointer P points to the start address of the basic logic operation element to be operated next, and the process is repeated again. By repeating the process of branching to the route corresponding to the operation type, the logical operation expression table 1 is sequentially interpreted and the operation is performed. If the calculation stock is ended (END), the calculation program ends its operation. In addition, in the execution of the basic logical operation, the output parameter 11, ma9, when referring to the parameter 14t,
In FIGS. 1 and 5, the value of the reference distinction flag 20 is 01. That is, in the case of a direct reference, the parameter of the basic logical operation element pointed to by the value of the pointer P is referenced, and the value of the reference distinction flag 20 is 1, that is, in the case of an indirect reference, the value of the pointer P is set to address (PS1+2). Refers to the address parameter plus the value of the parameter of the basic logical operation element pointed to by the value.
論理演算式の具体的な例として、第6図で、副プログラ
ム5を使用した主プログラム4を考えると、対応する論
理演算式テーブル1は、第7図の主プログラム6および
副プログラム7のようになる。As a specific example of a logical operation expression, if we consider the main program 4 that uses the subprogram 5 in FIG. become.
この実施例の他に、保存用ポインタP s t Pg。In addition to this embodiment, a storage pointer PstPg.
。
PRI + Psi、・・・・・・のように、複数個設
けることにより、副プログラムの中で更に別の副プログ
ラムを多重に参照することが可能である。. By providing a plurality of programs such as PRI + Psi, it is possible to refer to another subprogram multiple times within a subprogram.
本発明によれば、類似の論理を多数含むシーケンサにお
いて、繰シ返し使用せる共通的な論理を一般の論理と同
様の言後で作成することができ、しかも、使用する回数
にかかわらず一つだけ作成すれば済むので、シーケンサ
が完成した後でも共通論理を容易に変更できる。According to the present invention, in a sequencer that includes a large number of similar logics, it is possible to create a common logic that can be used repeatedly in the same way as general logic, and one The common logic can be easily changed even after the sequencer is completed.
第1図は本発明の論理式テーブルの構成図、第2図は論
理式テーブルを逐次解釈し演算するプログラムの流れ概
念図、第3図は第2図の中の副プログラムヘジャンプす
る箇所の詳細流れ図、第4図は第2図の中の主プログラ
ムへ戻る箇所の詳細流れ図、第5図は第2図の中の基本
論理演算においてパラメータを参照する箇所の詳細流れ
図、第6図はシーケンサの論理ブロック線図、第7図は
第6図に対応する論理式テーブル内容の具体例図である
。
1・・・論理演算式テーブル、2・・・基本論理演算要
素、3・・・終了要素、4・・・シーケンサ論理ブロッ
ク線図、5・・・副プログラム論理ブロック線図、6・
・・主プログラム論理演算式テーブル、7・・・副プロ
グラム論理演算式テーブル、20・・・パラメータ参照
区別フVp 1図 //
第2図Figure 1 is a configuration diagram of the logical formula table of the present invention, Figure 2 is a conceptual diagram of the flow of a program that sequentially interprets and calculates the logical formula table, and Figure 3 shows the jump to the subprogram in Figure 2. Detailed flowchart, Figure 4 is a detailed flowchart of the part in Figure 2 that returns to the main program, Figure 5 is a detailed flowchart of the part in Figure 2 that refers to parameters in basic logical operations, and Figure 6 is a detailed flowchart of the sequencer. FIG. 7 is a concrete example of the contents of the logical formula table corresponding to FIG. 6. DESCRIPTION OF SYMBOLS 1...Logic operation formula table, 2...Basic logic operation element, 3...End element, 4...Sequencer logic block diagram, 5...Sub program logic block diagram, 6...
・・Main program logic operation formula table, 7...Sub program logic operation formula table, 20...Parameter reference distinction function Vp Figure 1 // Figure 2
Claims (1)
算式を記憶したテーブルを逐次解釈しながら演算するデ
ィジタル計算機によるシーケンサにおいて、 前記基本論理演算要素を複数個組み合わせて接続関係を
定義した主プログラムの他に、前記主プログラムと同様
に前記基本論理演算要素を複数個組み合わせて接続関係
を定義した副プログラムをもち、前記主プログラムの中
で前記副プログラムの名称とパラメータを組み込むこと
によ繰り返し前記副プログラムを参照できる機能を設け
たことを特徴とする論理演算装置。[Scope of Claims] 1. In a sequencer using a digital computer that performs operations while sequentially interpreting a table in which logical operation expressions formed by combining a plurality of basic logical operation elements are combined, a connection relationship is established by combining a plurality of the basic logical operation elements. In addition to the main program that defines the above, it has a sub-program that combines a plurality of the above-mentioned basic logic operation elements and defines the connection relationship in the same manner as the main program, and incorporates the name and parameters of the sub-program in the main program. A logic arithmetic device characterized in that it is further provided with a function of repeatedly referencing the subprogram.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59244448A JPS61123904A (en) | 1984-11-21 | 1984-11-21 | Logic arithmetic device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59244448A JPS61123904A (en) | 1984-11-21 | 1984-11-21 | Logic arithmetic device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61123904A true JPS61123904A (en) | 1986-06-11 |
Family
ID=17118800
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59244448A Pending JPS61123904A (en) | 1984-11-21 | 1984-11-21 | Logic arithmetic device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61123904A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011070539A (en) * | 2009-09-28 | 2011-04-07 | Mitsubishi Electric Corp | Programmable controller |
-
1984
- 1984-11-21 JP JP59244448A patent/JPS61123904A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011070539A (en) * | 2009-09-28 | 2011-04-07 | Mitsubishi Electric Corp | Programmable controller |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4791558A (en) | System and method for generating an object module in a first format and then converting the first format into a format which is loadable into a selected computer | |
JP2002502516A (en) | Selective emulation interpretation using post-translation instructions | |
US3698007A (en) | Central processor unit having simulative interpretation capability | |
RU96119968A (en) | PROCESSING SYSTEM AND METHOD FOR ITS FUNCTIONING | |
JP3318051B2 (en) | Translation processing method | |
JPS61123904A (en) | Logic arithmetic device | |
Bobrow et al. | List processing and extension of language facility by embedding | |
JPH03135630A (en) | Instruction scheduling system | |
EP0348563A1 (en) | A system and method for generating program object modules | |
Duncan et al. | The DEUCE alphacode translator | |
JP3240647B2 (en) | Computer language structured processing | |
JPH0417031A (en) | System for optimizing propagation of constant value | |
JPS62226336A (en) | Microprogram control system | |
Wilkes | Associative tabular data structures | |
Iliffe | DIGITAL SYSTEMS LABORATORY I | |
Wilkes | Associative tabular data structures | |
JPH0675757A (en) | Link system for virtual space resident program | |
JPS63276629A (en) | Sorting system for record in file | |
Nilges | A Brief History of Compiler Technology | |
JPS6275736A (en) | Prologue processor | |
JPS61224042A (en) | Optimizing code generating system relating to approach of arrangement element in virtual storage system | |
JPS605341A (en) | Information processing device | |
Schlechtendahl | Approach | |
JPS62216037A (en) | Message managing system using source library | |
JPH064348A (en) | Program debugging system |