JPS605341A - Information processing device - Google Patents

Abstract

PURPOSE:To make microinstruction branching of an optional branching number with one microinstruction, by using an operated result itself as a microinstruction address. CONSTITUTION:A microprogram sequencer 1 consists of an address register 6, address updating circuit 5, register 8 which holds the output result of an operator 4, and address selecting circuit 7. A microinstruction stored in a control storage device 2 is read out in accordance with addresses selected by the address selecting circuit 7 and set in a microinstruction register 3. When a microinstruction is to be branched by means of the output result of the operator 4, the output of the register 8 is selected by the address selecting circuit 7 and the branching is performed by using the selected output of the register 8 itself as a microinstruction address. Therefore, microinstruction branching of an optional branching number can be performed with one microinstruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a microprogram-controlled information processing device.

[Background of the invention]

A microprogram-controlled information processing device is programmed with a set of microinstructions that specify the basic operations of the processing device, stores this in a control storage device, and reads and executes microinstructions as needed to control the processing device. Realize the action. This microinstruction reading control is performed by a microprogram sequencer.

A block diagram of a processing device using a conventional microprogram sequencer is shown in FIG.

The microprogram sequencer 1 shown in this example includes an address register 6, an address update circuit 5, a register 8 that holds a part of the output result of the arithmetic unit 4, and an address selection circuit 7.
According to the address selected by the address selection circuit 7, the microinstruction stored in the control storage device 2 is read out and set in the microinstruction register 3. Based on the contents set in the microinstruction register 3, the arithmetic unit 4. The operation of the microprogram sequencer 1 is determined. If there is a process in which a microinstruction changes the subsequent operation depending on the output result of the arithmetic unit 4, as shown in FIG. One part of the data 10 is combined and branched as the next microinstruction address. At this time, the address selection circuit 7 selects the combined address.

As shown in this example, when branching a microinstruction using the microprogram sequencer of a conventional information processing device, if the microinstruction is to be branched based on the operation result, the branch address part of the microinstruction and the operation result are combined and the branch is executed. Since addresses were created, the number of branches was determined by the data length of register 8. For example, register 8
In the case of a 4-way branch with a data length of 2 bits,
Since it is possible to branch only in 4 ways, if you want to branch in 16 ways, first branch into 4 ways depending on the calculation result, then shift the calculation result to the right by 2 bits, and use this result to branch into 4 more ways. was.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing device that is capable of branching with an optimal number of branches using one microinstruction.

[Summary of the invention]

The present invention is characterized in that by using the operation result itself as a microinstruction address, microinstruction branching can be performed by an arbitrary number of branches using one microinstruction.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 6 is a block diagram of an information processing device showing an embodiment of the present invention.

The microprogram sequencer 1 is composed of an address register 6, an address update circuit 5, a register 8 that holds the output results of the arithmetic unit 4, and an address selection circuit 7. The stored microinstruction is read out and set in the microinstruction register 3.

The data length of register 8 is 3 microinstructions.

If the data length of the output result of the arithmetic unit is longer than the data length, the upper bits are ignored and only the lower bits are set in the register 8. When the microinstruction wants to branch based on the output result of the arithmetic unit, the address selection circuit 7 selects the output of the register 8, and branches using the output of the register 8 itself as the microinstruction address.

Next, an example in which the microprogram sequencer is used to branch in 16 ways depending on the operation result will be explained based on the operation for each microinstruction step.

Step 1 Set the output result of the operation to be tested in the work register 1 in the processing device.

Step 2 Set the logical product of the contents of the work register 1 and the values in which the lower 4 bits are all 1'' and the upper bits are all 0'' to the work register 2. The value in which the lower three bits are all 1'' and the upper bits are all lO'' is given from the literal part of the microinstruction (the value of the microinstruction itself is a numerical value) and is 4 + .

Step 3 Set the reference address of the branch address to work register B. The reference address is given from the literal part of the microinstruction with the lower 4 bits all being plus values.

Step 4 Take the logical sum of work register 2 and work register 6 and register 8 of the microprogram sequencer.
Set to .

Step 5 Branch using the value of register 8 as the microinstruction address.

By executing steps 1 to 5, the microinstruction can be branched based on the value of the lower 4 bits of the operation result. In this example, a method of branching in 16 ways has been described, but it is also possible to branch in more than 16 ways by changing the value of the literal part of the microinstruction.

With the above control, according to this embodiment, an arbitrary number of bits of the operation result and the reference branch address are synthesized using a microinstruction to form a microinstruction address, so that any bit of the operation result can be generated with one microinstruction. It is possible to branch according to the value of the number.

〔Effect of the invention〕

According to the present invention, when the processing of a microinstruction becomes difficult due to the operation result, it is possible to branch to any number of branches using one microinstruction, so that the processing time required for branching can be shortened, and the processing time can be reduced. Effective in speeding up the device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an information processing device showing a conventional example, FIG. 2 is an explanatory diagram showing a conventional branch address creation method, and FIG. 3 is a block diagram of an information processing device showing an embodiment of the present invention. It is a diagram. DESCRIPTION OF SYMBOLS 1... Micro program sequencer, 2... Control storage device, 3... Micro instruction register, 4... Arithmetic unit, 5... Address update circuit, 6... Address register, 7... Address selection circuit, 8...operation p2 output holding registers 1, 7. No. ／ Illustration February

Claims (1)

[Claims] In a microprogram-controlled information processing device in which microinstructions stored in a control storage device are sequentially read out to a microinstruction register and executed according to specifications of a microprogram sequencer that controls reading of the microinstructions, The program sequencer consists of a register that holds only the same length as the microinstruction address out of the output results of the processor, an address register that holds the results of the address update circuit, and a selection circuit that selects both registers. An information processing device characterized by: