JPH02122628A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02122628A JPH02122628A JP27675188A JP27675188A JPH02122628A JP H02122628 A JPH02122628 A JP H02122628A JP 27675188 A JP27675188 A JP 27675188A JP 27675188 A JP27675188 A JP 27675188A JP H02122628 A JPH02122628 A JP H02122628A
- Authority
- JP
- Japan
- Prior art keywords
- contact hole
- etching
- semiconductor device
- conductive film
- shape
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 238000005530 etching Methods 0.000 claims abstract description 38
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- 229910018503 SF6 Inorganic materials 0.000 claims abstract description 5
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229960000909 sulfur hexafluoride Drugs 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 25
- 238000012545 processing Methods 0.000 abstract description 10
- 230000006866 deterioration Effects 0.000 abstract 1
- 230000007423 decrease Effects 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 4
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 229920006254 polymer film Polymers 0.000 description 1
- 229920005597 polymer membrane Polymers 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体装置のコンタクトホールの製造方法、特に微細な
コンタクトホールのドライエツチングによる加工方法に
関し。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for manufacturing contact holes in a semiconductor device, particularly a method for processing fine contact holes by dry etching.
このコンタクトホールのドライエツチングにおいて安定
性、信頼性の高いプロセスを駆使して。We make full use of a highly stable and reliable process for dry etching this contact hole.
上部のみがテーパー形状のコンタクトホールを提供する
ことを目的として。Only the top part is intended to provide a tapered contact hole.
コンタクトホールの側面を基板にほぼ垂直に形成した後
、六弗化硫黄を含むエツチングガスを用いた準異方性エ
ツチングにより、コンタクトホールの上部のみを、側面
がテーパー形状になるように拡大する。After the side surfaces of the contact hole are formed substantially perpendicular to the substrate, only the upper part of the contact hole is enlarged so that the side surface has a tapered shape by quasi-anisotropic etching using an etching gas containing sulfur hexafluoride.
本発明は、半導体装置のコンタクトホールの製造方法、
特に微細なコンタクトホールのドライエツチングによる
加工方法に関する。The present invention provides a method for manufacturing a contact hole in a semiconductor device,
In particular, it relates to a method of processing fine contact holes by dry etching.
半導体装置の高集積化に伴い1 コンタクトホール径は
ますます小さくすることが要求されている。As semiconductor devices become more highly integrated, contact hole diameters are required to become smaller and smaller.
コンタクトホールの径が小さくなっても、そのエツチン
グ対象の絶縁膜の膜厚はデバイス特性から必ずしも比例
して小さくすることは出来ない。Even if the diameter of the contact hole is reduced, the thickness of the insulating film to be etched cannot necessarily be reduced proportionally due to device characteristics.
従って、コンタクトホールの深さと径の比率。Therefore, the ratio of the depth and diameter of the contact hole.
即ちアスペクト比は微細化により増大し、後工程での導
電性膜のスパッタ法による形成において。That is, the aspect ratio increases with miniaturization, and in the formation of a conductive film by sputtering in a subsequent process.
コンタクトホール部での膜の厚さが部分的に薄くなり、
断線等の障害を引き起こす。このため、半導体装置の性
能の安定性、信頼性を高めるために。The thickness of the film at the contact hole area becomes partially thinner.
This may cause problems such as wire breakage. For this reason, to improve the stability and reliability of semiconductor device performance.
コンタクトホールのアスペクト比の増大によって悪化し
た導電性膜のカバレッジを改善する必要がある。It is necessary to improve the coverage of the conductive film, which has deteriorated due to the increase in the aspect ratio of the contact hole.
(従来の技術〕
従来の半導体装置のコンタクトホール形成方法を第3図
に示す。(Prior Art) A conventional method for forming contact holes in a semiconductor device is shown in FIG.
従来の形成方法では、下地の導電性膜10の上の絶縁膜
11にコンタクトホール12をドライエツチングで加工
すると第3図(a)に示すようにほぼ垂直な断面形状が
得られていた。このコンタクトホール12にスパッタ法
で導電性膜13を付与させると。In the conventional forming method, when a contact hole 12 is formed in the insulating film 11 on the underlying conductive film 10 by dry etching, a substantially vertical cross-sectional shape as shown in FIG. 3(a) is obtained. A conductive film 13 is applied to this contact hole 12 by sputtering.
第3図(b)に示すように膜厚の薄い部分が出来る。As shown in FIG. 3(b), a thin portion is formed.
平らな部分での導電性膜の膜厚を1とした時のコンタク
トホールでの最も薄い部分での導電性膜の膜厚の比を「
カバレッジ」と呼ぶ。このカバレッジは、コンタクトホ
ールでのアスペクト比が大きくなるに従って小さくなり
、半導体装置の信頼性は著しく低下する。When the thickness of the conductive film at the flat part is 1, the ratio of the thickness of the conductive film at the thinnest part of the contact hole is "
It is called "coverage". This coverage decreases as the aspect ratio of the contact hole increases, and the reliability of the semiconductor device decreases significantly.
そこで、このコンタクトホールをテーパー形状に加工し
て上面部分を第3図(c)に示すように大きくしてカバ
レッジを改善する方法が幾つか提唱されている。例えば
テーパー形状を得るために。Therefore, several methods have been proposed for improving the coverage by processing the contact hole into a tapered shape and enlarging the upper surface portion as shown in FIG. 3(c). For example to obtain a tapered shape.
エツチングガスに酸素を入れてレジストとの選択比を落
として上部を大きくする方法(例1)や。There is a method (Example 1) in which oxygen is added to the etching gas to lower the selectivity to the resist and make the upper part larger.
デポジット性の高いガス条件でエツチングレートを落と
してテーパーエッヂングを行い、下部面積を小さくした
りする方法(例2)がある。例1゜例2の方法で加工し
たコンタクトホールの形状を図示した第3図(c)にお
いて、14は導電性膜、 15は絶縁膜、16はコンタ
クトホール117はテーパー形状を示す。There is a method (Example 2) in which tapered etching is performed by lowering the etching rate under gas conditions with high deposition properties to reduce the lower area. Example 1 In FIG. 3(c) showing the shape of a contact hole processed by the method of Example 2, 14 is a conductive film, 15 is an insulating film, and 16 is a contact hole 117 having a tapered shape.
〔発明が解決しようとする課題]
上記のような方法でコンタクトホールを加工すると、は
ぼ垂直な形状のコンタクトホールを加工する場合と比較
して2例1では、レジストとの選択比の低下、エツチン
グ終点検出精度の低下などの問題が起こり9例2では、
エツチング終点検出精度の低下の他に、装置の汚染等に
よる洗浄周期の短縮等の問題が起こる。[Problems to be Solved by the Invention] When a contact hole is processed by the method described above, compared to the case where a contact hole having a nearly vertical shape is processed, in Example 1, there is a decrease in the selectivity with respect to the resist, In Case 2, problems such as a decrease in etching end point detection accuracy occurred.
In addition to a decrease in the accuracy of etching end point detection, problems such as a shortening of the cleaning cycle due to equipment contamination and the like occur.
その結果、コンタクトホールの加工プロセスの安定性、
信頼性は低下し、半導体装置の動作不良の原因となる。As a result, the stability of the contact hole processing process,
Reliability decreases, causing malfunction of the semiconductor device.
本発明は、このコンタクトホールのドライエツチングに
おいて安定性、信頼性の高いプロセスを駆使して、上部
がテーパー形状に後加工されるコンタクトホールを提供
することを目的とする。An object of the present invention is to provide a contact hole whose upper portion is post-processed into a tapered shape by making full use of a highly stable and reliable dry etching process.
(課題を解決するための手段〕
コンタクトホールに対して、異方性エツチングを行うと
その側面には高分子膜が付着することが知られている。(Means for Solving the Problems) It is known that when a contact hole is subjected to anisotropic etching, a polymer film will adhere to the side surfaces of the contact hole.
逆にその高分子膜が側壁を保護しほぼ垂直な形状を保つ
理由となっている。コンタクトホールをほぼ垂直な形状
でエツチングすることが高い安定性と信頼性を有するプ
ロセス加工法であることは、前述の通りであり、コンタ
クトホールをエツチングするプロセス自体は垂直形状を
得ることを目的とした条件で行うことが望ましい。On the contrary, the polymer membrane protects the side walls and is the reason why it maintains its almost vertical shape. As mentioned above, etching a contact hole in a nearly vertical shape is a process method with high stability and reliability, and the process itself of etching a contact hole is aimed at obtaining a vertical shape. It is desirable to carry out the test under the following conditions.
しかし、このままでは、コンタクトホール上部側面のテ
ーパー形状は得られない。However, in this state, the tapered shape of the upper side surface of the contact hole cannot be obtained.
従って本発明は、コンタクトホールのほぼ垂直な形状を
得られる条件でエツチングをおこなった後にコンタクト
ホール上部のみを側面がテーパー形状になるよう後加工
して、その面積を拡大して導電性膜のカバレッジを良く
するものである。Therefore, in the present invention, after etching is performed under conditions that allow a nearly vertical shape of the contact hole to be obtained, only the upper part of the contact hole is post-processed so that the side surface becomes tapered, thereby expanding the area and increasing the coverage of the conductive film. It is something that makes things better.
第1図は1本発明の原理説明図である。先ず。FIG. 1 is a diagram explaining the principle of the present invention. First.
第1図(a)に示すように、従来の方法により、下地の
導電性膜l上の絶縁膜2にレジスト等のマスキングを行
い、はぼ垂直な形状で第一のエツチングを行って、コン
タクトホール3をパタニングする。第1図において、1
は導電性膜、2は絶縁膜。As shown in FIG. 1(a), using a conventional method, the insulating film 2 on the underlying conductive film 1 is masked with resist or the like, and a first etching is performed in a nearly vertical shape to form a contact. Pattern hole 3. In Figure 1, 1
is a conductive film, and 2 is an insulating film.
3はコンタクトホールである。3 is a contact hole.
次に、第1図(b)に示すように、レジストが工・ンジ
から後退するようなガス条件で、且つ、絶縁膜をエツチ
ングできる条件で第二のエツチングを行う。その結果、
レジストの後退によりコンタクトホール上部でのテーパ
ー形状4が得られる。Next, as shown in FIG. 1(b), a second etching is performed under gas conditions such that the resist recedes from the etching and under conditions that allow etching of the insulating film. the result,
A tapered shape 4 at the top of the contact hole is obtained by retreating the resist.
本発明では、第1図(a)に示したように第一のエツチ
ングは従来どうりのほぼ垂直な形状を得るエツチングな
ので、コンタクトホールを安定性。In the present invention, as shown in FIG. 1(a), the first etching is an etching to obtain a substantially vertical shape as in the conventional etching, so that the contact hole is stable.
信鯨性良く加工することで、終点検出精度の低下などの
問題を回避することができる。Processing with good reliability can avoid problems such as a decrease in end point detection accuracy.
そして、第1図(b)に示したように、エツチングガス
に六弗化硫黄を加えて、テーパー加工のコントロールの
し易いドライエツチングを採用して。Then, as shown in Figure 1(b), sulfur hexafluoride was added to the etching gas, and dry etching was adopted, which made it easier to control the taper process.
コンタクトホール上部の面積のみを選択的に大きくする
ことで、導電性膜のカバレッジを改善することができる
。更にコンタクトホールの底部面積を大きくしないこと
で他の配線層との電気的な接触、リーク、干渉が避けら
れ、この点でも、半導体装置の安定性、信頼性が増大す
る。By selectively increasing only the area above the contact hole, the coverage of the conductive film can be improved. Furthermore, by not increasing the bottom area of the contact hole, electrical contact, leakage, and interference with other wiring layers can be avoided, and in this respect as well, the stability and reliability of the semiconductor device are increased.
本発明の実施例を第2図に示す。 An embodiment of the invention is shown in FIG.
コンタクトホールのほぼ垂直な断面形状を得る第一のエ
ツチングと、前記コンタクトホールの上部のみをテーパ
ー形状に加工する第二のエツチングの二段階に分けて、
加工を行う。The etching process is divided into two stages: a first etching process to obtain a substantially vertical cross-sectional shape of the contact hole, and a second etching process to process only the upper part of the contact hole into a tapered shape.
Perform processing.
第一のエツチングは、第2図(a)に示すように下地の
導電性膜5の上に燐珪酸ガラス、或いは化学気相成長法
や熱拡散法により成長した二酸化シリコン酸化膜等の絶
縁膜6を形成し、従来の方法によりレジスト7を塗布し
、コンタクトホール8をパタニングする。その後で2反
応性イオンエツチング(RIB)装置を用い、エツチン
グガスとして四弗化炭素(CF4)、三弗化メタン(C
HF、)を使用し。The first etching is performed by forming an insulating film such as phosphosilicate glass or a silicon dioxide film grown by chemical vapor deposition or thermal diffusion on the underlying conductive film 5, as shown in FIG. 2(a). 6 is formed, a resist 7 is applied by a conventional method, and a contact hole 8 is patterned. After that, using a two-reactive ion etching (RIB) device, carbon tetrafluoride (CF4) and trifluoromethane (C
HF,) is used.
ガス流量をCI’4=40secm 、 CHF、=
50secm+ 圧力・0゜3Torr、出力・60
0−の条件で異方性エツチングして、はぼ垂直な形状が
得られるように加工する。The gas flow rate is CI'4=40sec, CHF,=
50sec+ Pressure: 0°3 Torr, Output: 60
Anisotropic etching is performed under 0- conditions to obtain a substantially vertical shape.
次に、上記のコンタクトホール8の上部のみをテーパー
状に加工する第二のエツチングを2例えば以下のような
準異方性エツチングの条件で実施する。Next, a second etching process is performed to process only the upper part of the contact hole 8 into a tapered shape, for example, under the following quasi-anisotropic etching conditions.
上記と同様なRIE装置を用い、エツチングガスとして
、 CF4.ClIF5に六弗化硫黄(sp、)を加え
、ガス流量をCF4=405CC111,CHF5=5
03CC111SF&=100!IccI+圧力0.4
Torr出力60囲の条件で、第2図(b)に示すよう
なテーパー形状9に加工する60秒間のエツチングを行
う。Using the same RIE apparatus as above, CF4. Add sulfur hexafluoride (sp, ) to ClIF5 and change the gas flow rate to CF4=405CC111, CHF5=5
03CC111SF&=100! IccI+pressure 0.4
Etching is performed for 60 seconds to form a tapered shape 9 as shown in FIG. 2(b) under conditions of a Torr output of around 60.
エツチング時間は、エツチング条件にもよるが時間が短
いとテーパーが−E部のみで不足し、逆に時間が長いと
テーパーが下部に及び、更に長くすると底面部分の面積
が大きくなってしまう。エツチング時間は設計及びデバ
イスの性能により最適の時間を選択する。The etching time depends on the etching conditions, but if the etching time is short, the taper will be insufficient only at the -E portion, whereas if the etching time is long, the taper will extend to the lower part, and if the etching time is longer, the area of the bottom portion will become larger. The optimum etching time is selected depending on the design and device performance.
以上説明したように9本発明によれば、先ず従来どおり
のほぼ垂直な形状でコンタクトホールの側面を加工する
ため、加工による安定性、信頼性を損ねることがなく、
更に、その後でコンタクトホールの上部のみを大きくテ
ーパー形状に加工することで、カバレッジの良い形状を
得ることが可能であり、電極配線の故障のない信頼性の
高い半導体装置を製造することができる。As explained above, according to the present invention, since the side surface of the contact hole is first processed in a substantially vertical shape as in the conventional method, stability and reliability due to processing are not impaired.
Furthermore, by subsequently processing only the upper part of the contact hole into a largely tapered shape, it is possible to obtain a shape with good coverage, and a highly reliable semiconductor device without failure of electrode wiring can be manufactured.
第1図は本発明の原理説明図。
第2図は本発明の一実施例の模式断面図。
第3図は従来例の模式断面図である。
図において。
1は導電性膜。
2は絶縁膜。
3はコンタクトホール。
4はテーパー形状
5は導電性膜。
6は絶縁膜。
7はレジスト。
8はコンタクトホール。
9はテーパー形状
本島用の禾姪i先明図
gb 1 図
本me月刀−′X′ハシ炒9/)F弊氏歯〒m ε巧仇
采令)n碩′に、照面図
第
図FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a schematic sectional view of one embodiment of the present invention. FIG. 3 is a schematic sectional view of a conventional example. In fig. 1 is a conductive film. 2 is an insulating film. 3 is the contact hole. 4 is a tapered shape 5 is a conductive film. 6 is an insulating film. 7 is resist. 8 is a contact hole. 9 is a tapered shape for the main island.
Claims (1)
チングにおいて、該コンタクトホールの側面を基板にほ
ぼ垂直に形成した後、六弗化硫黄を含むエッチングガス
を用いた準異方性エッチングにより、該コンタクトホー
ルの上部のみを、側面がテーパー形状になるように拡大
することを特徴とする半導体装置の製造方法。In dry etching for forming contact holes in semiconductor devices, the side surfaces of the contact holes are formed almost perpendicular to the substrate, and then the upper part of the contact holes is etched by quasi-anisotropic etching using an etching gas containing sulfur hexafluoride. 1. A method of manufacturing a semiconductor device, comprising enlarging only the side surface of the semiconductor device so that the side surface thereof has a tapered shape.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27675188A JPH02122628A (en) | 1988-11-01 | 1988-11-01 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27675188A JPH02122628A (en) | 1988-11-01 | 1988-11-01 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02122628A true JPH02122628A (en) | 1990-05-10 |
Family
ID=17573837
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27675188A Pending JPH02122628A (en) | 1988-11-01 | 1988-11-01 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02122628A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6476496B1 (en) | 1999-06-28 | 2002-11-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
JP2009071009A (en) * | 2007-09-13 | 2009-04-02 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
WO2010058528A1 (en) * | 2008-11-20 | 2010-05-27 | シャープ株式会社 | Semiconductor layer and method for forming same |
JP2013110331A (en) * | 2011-11-24 | 2013-06-06 | Sumitomo Electric Ind Ltd | Semiconductor device manufacturing method |
-
1988
- 1988-11-01 JP JP27675188A patent/JPH02122628A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6476496B1 (en) | 1999-06-28 | 2002-11-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
JP2009071009A (en) * | 2007-09-13 | 2009-04-02 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
WO2010058528A1 (en) * | 2008-11-20 | 2010-05-27 | シャープ株式会社 | Semiconductor layer and method for forming same |
JPWO2010058528A1 (en) * | 2008-11-20 | 2012-04-19 | シャープ株式会社 | Semiconductor layer and method for forming the same |
US8415673B2 (en) | 2008-11-20 | 2013-04-09 | Sharp Kabushiki Kaisha | Thin film transistor and semiconductor layer |
JP2013110331A (en) * | 2011-11-24 | 2013-06-06 | Sumitomo Electric Ind Ltd | Semiconductor device manufacturing method |
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