JPH02122553A - Resin sealed semiconductor device - Google Patents
Resin sealed semiconductor deviceInfo
- Publication number
- JPH02122553A JPH02122553A JP27577788A JP27577788A JPH02122553A JP H02122553 A JPH02122553 A JP H02122553A JP 27577788 A JP27577788 A JP 27577788A JP 27577788 A JP27577788 A JP 27577788A JP H02122553 A JPH02122553 A JP H02122553A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resin
- chip
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 229920005989 resin Polymers 0.000 title claims abstract description 29
- 239000011347 resin Substances 0.000 title claims abstract description 29
- 229910003460 diamond Inorganic materials 0.000 claims abstract description 7
- 239000010432 diamond Substances 0.000 claims abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 5
- 238000007789 sealing Methods 0.000 abstract description 21
- 238000000034 method Methods 0.000 abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 14
- 239000000758 substrate Substances 0.000 abstract description 8
- 229910052681 coesite Inorganic materials 0.000 abstract description 7
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 7
- 239000000377 silicon dioxide Substances 0.000 abstract description 7
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 7
- 229910052682 stishovite Inorganic materials 0.000 abstract description 7
- 229910052905 tridymite Inorganic materials 0.000 abstract description 7
- 239000000463 material Substances 0.000 abstract description 6
- 230000002950 deficient Effects 0.000 abstract description 2
- 230000006866 deterioration Effects 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- 230000001788 irregular Effects 0.000 abstract 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 abstract 1
- 239000010408 film Substances 0.000 abstract 1
- 229910017604 nitric acid Inorganic materials 0.000 abstract 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 238000005336 cracking Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000011889 copper foil Substances 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- RTZKZFJDLAIYFH-UHFFFAOYSA-N ether Substances CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Abstract
Description
【発明の詳細な説明】
〔概 要〕
半導体チップを、その背面を固定用あるいは電極用ステ
ージに固着せずそのまま樹脂封止する樹脂封止型半導体
装置に関し、
半導体チップ背面と封止用樹脂との密着性を改善し、半
導体装置の耐湿性の向上および半導体チップ割れの防止
による歩留りおよび信幀度の向上を図ることを目的とし
、
半導体チップの背面が粗成されて凹凸がつけられ、前記
凹凸がつけられた背面にＳｉＯＮ膜、 Ｓｔ、Ｎ４膜、
Ｓｉ３Ｎ４膜、ＳｉＯ２膜またはダイヤモンド膜が形
成され、少なくとも前記膜の表面が樹脂で覆われている
ことを特徴とする。[Detailed Description of the Invention] [Summary] Regarding a resin-sealed semiconductor device in which a semiconductor chip is sealed with a resin as it is without fixing the back side of the semiconductor chip to a fixing or electrode stage, the back side of the semiconductor chip and the sealing resin are bonded together. In order to improve the adhesion of semiconductor devices, improve the moisture resistance of semiconductor devices, and improve yield and reliability by preventing semiconductor chip cracking, the back surface of semiconductor chips is roughened and roughened. SiON film, St, N4 film,
A Si3N4 film, a SiO2 film, or a diamond film is formed, and at least the surface of the film is covered with a resin.
本発明は、半導体チップを、その背面を固定用あるいは
電極用ステージに固着せずそのまま樹脂封止する樹脂封
止型半導体装置に関する。The present invention relates to a resin-sealed semiconductor device in which a semiconductor chip is resin-sealed as it is without fixing the back surface of the semiconductor chip to a fixing or electrode stage.
半導体ＩＣにおいては、近時その集積度の向上による半
導体チップ上の隣接する電極間隔の近接化およびパッケ
ージの多ピン化や需要の増大による量産性の必要上、組
立工程においてフィルムキャリアを用いたテープオート
メ−ティラドボンディング（以下ＴＡＢと略す）方式が
採用されている。In semiconductor ICs, tapes using film carriers are used in the assembly process due to the need for mass production due to the recent improvement in the degree of integration of semiconductor ICs, which has brought the distance between adjacent electrodes on semiconductor chips closer together, and the increase in the number of pins in packages and increased demand. An automated rad bonding (hereinafter abbreviated as TAB) method is employed.
フィルムキャリアを用いたＴＡＢ方式とは、引出しリー
ドとなるＳｎメツキの施された薄い銅箔を固着したポリ
イミドフィルムキャリアを、半導体チップ上適当な位置
に載置することにより、−度に半導体チップに引出しリ
ードを形成する方式で、精細度性・量産性にすぐれてい
る。The TAB method using a film carrier is a polyimide film carrier to which a thin Sn-plated copper foil, which serves as the lead-out lead, is fixed, and is placed at an appropriate position on the semiconductor chip. This method forms drawer leads and has excellent precision and mass production.
木方式を用いた半導体装置においては、通常、半導体チ
ップは、その背面を固定用あるいは電極用ステージに固
着せずそのまま樹脂封止されるが、固定用あるいは電極
用ステージを有する半導体装置と同様の歩留り、信軌度
が要求されることは言うまでもない。In a semiconductor device using the wood method, the semiconductor chip is usually sealed with resin without fixing its back side to a fixing or electrode stage, but it is similar to a semiconductor device having a fixing or electrode stage. Needless to say, yield and reliability are required.
［従来の技術］
第３図は、従来例の樹脂封止型半導体装置の断面図であ
る。[Prior Art] FIG. 3 is a sectional view of a conventional resin-sealed semiconductor device.
図において、１１１ はＳｉチ・ンブ、１０２はへＵバ
ンフ゛、１０．１ は厚さ３５μｍ程度の銅箔にＳｎメ
ンキを施した引出しリード、１０６は引出しリードをボ
ンディングするところにはＡｕメツキ１０８が施されて
いるＳｎメンキ銅のアウターリード、１０７は封止用樹
脂である。In the figure, 111 is a Si chip, 102 is a U-banf, 10.1 is a lead lead made of Sn-plated copper foil with a thickness of about 35 μm, and 106 is an Au plating 108 where the lead lead is bonded. The Sn-coated copper outer lead 107 is a sealing resin.
封止用樹脂１０７は、耐湿性・密着性およびコスト性の
面より、主にエポキシ系の樹脂が用いられるが、耐熱性
を重視するときにはシリコン系の樹脂も用いられる。As the sealing resin 107, an epoxy resin is mainly used from the viewpoint of moisture resistance, adhesion, and cost efficiency, but a silicone resin is also used when heat resistance is important.
ところで、Ｓｉチップ１１１は、その厚みを９周整する
必要から、ウェハ段階で背面がラッピングされる。この
ときのラップ材は、樹脂封止の場合は特定されないが、
チップがステージ上に固着されるセラミック封止の場合
には、固着性の向上のため、チップ背面の粗さをある程
度密にする必要性から、粗さ１１５００〜＃３００のも
のが要求される。By the way, since the thickness of the Si chip 111 needs to be adjusted nine times, the back surface of the Si chip 111 is lapped at the wafer stage. The wrap material at this time is not specified in the case of resin sealing, but
In the case of ceramic sealing in which the chip is fixed on a stage, a roughness of 11500 to #300 is required because it is necessary to make the roughness of the back surface of the chip denser to some extent in order to improve the adhesion.
しかし、ウェハ段階ではセラミック封止するか、あるい
は樹脂封止するか、必ずしも確定していないので、一般
にはセラミック封止にも対応できるように上記ラップ材
を用いてラッピングしている。However, at the wafer stage, it is not necessarily determined whether to perform ceramic sealing or resin sealing, so wrapping is generally performed using the above-mentioned wrapping material so that it can also be used for ceramic sealing.
従って、該チップが電極用ステージに固着しないＴＡＢ
方式を用いた樹脂封止型半導体’ＡＩにも搭載されてい
る。Therefore, the TAB chip does not stick to the electrode stage.
It is also installed in resin-sealed semiconductor 'AI' using this method.
しかし、最近では、かかるＳｉチップ１１１の背面と封
止用樹脂１０７との密着性が問題となっている。However, recently, the adhesion between the back surface of the Si chip 111 and the sealing resin 107 has become a problem.
一般に、封止用樹脂１０７、特にエポキシ系の封止用樹
脂は、０１１基やエーテル結合をもっているので、半導
体チップとの密着性が良好であるといわれているが、実
際には十分な密着性を保証しないことが実験的に確かめ
られている。In general, the sealing resin 107, especially the epoxy sealing resin, has 011 groups and ether bonds, so it is said that it has good adhesion to semiconductor chips, but in reality, it has insufficient adhesion. It has been experimentally confirmed that this is not guaranteed.
このため、第３図の構造においては、Ｓｉチップ１１１
の背面と封止用樹脂１０７との界面に沿って外から水分
が侵入し易くなり、温度サイクル試験や熱衝撃試験等の
環境試験を行うと、内部に蓄積した水分が膨張してＳｉ
チップが割れるという問題があった。Therefore, in the structure shown in FIG.
It is easy for moisture to enter from the outside along the interface between the back surface of the Si and the sealing resin 107, and when an environmental test such as a temperature cycle test or a thermal shock test is performed, the moisture accumulated inside expands and the Si
There was a problem with the chip breaking.
また高温バイアス温度試験（ＲＨＢＴ試験）等の加速試
験やフィールドでの動作中においても、水分による半導
体素子の特性劣化が生じるという問題があった。Further, there is a problem in that the characteristics of semiconductor elements are deteriorated due to moisture even during accelerated tests such as high temperature bias temperature tests (RHBT tests) or during operation in the field.
上記課題は、半導体チップの背面が粗成されて凹凸がつ
けられ、前記凹凸がつけられた背面にＳｉＯＮ膜、５ｉ
Ｊ４膜、 Ｓｉ３Ｎ４膜、ＳｉＯ２膜またはダイヤモン
ド膜が形成され、少なくとも前記膜の表面が樹脂で覆わ
れていることを特徴とする樹脂封止型半導体装置によっ
て達成される。The problem described above is that the back surface of a semiconductor chip is roughly formed and has an uneven surface, and a SiON film is formed on the uneven back surface.
This is achieved by a resin-sealed semiconductor device characterized in that a J4 film, a Si3N4 film, a SiO2 film, or a diamond film is formed, and at least the surface of the film is covered with a resin.
本発明では、半導体チップ背面を一定の組成手段で粗成
して凹凸をつけ、半導体チップ背面と樹脂と接触する表
面積を増やしているので、密着性が向上する。In the present invention, the back surface of the semiconductor chip is roughened using a certain compositional means to form irregularities, thereby increasing the surface area that contacts the back surface of the semiconductor chip and the resin, thereby improving adhesion.
また、半導体チップ背面に、封止用樹脂中のＯＨ基また
はエーテル結合の存在により、樹脂との密着性を増すＳ
ｉＯＮ膜、 ５ｉＪａ ｔＰＪ、 Ｓｔｏｗ膜、または
ダイヤモンド膜を形成しているので、化学的な面からも
密着性を向上させることができる。In addition, the presence of OH groups or ether bonds in the sealing resin makes S
Since an iON film, 5iJatPJ, Stow film, or diamond film is formed, adhesion can be improved from a chemical standpoint as well.
従って、半導体チップ背面と樹脂との界面には空隙が生
じることがなく、外から水分が浸入を防ぐことができる
。Therefore, no voids are formed at the interface between the back surface of the semiconductor chip and the resin, and moisture can be prevented from entering from the outside.
第４図は、従来例の半導体装置と本発明の半導体装置と
でパッケージの割れに関しての強廣を、実験的に比較し
た図である。FIG. 4 is a diagram experimentally comparing the strength of a conventional semiconductor device and a semiconductor device of the present invention with respect to package cracking.
実験としては、チップ背面に３４０ｇ膜が形成された本
発明の半導体装置とチップ背面に５ｔｙｘ膜が形成され
ていない従来例の半導体装置とを用いて行った。The experiment was conducted using a semiconductor device of the present invention in which a 340g film was formed on the back surface of the chip and a conventional semiconductor device in which a 5tyx film was not formed on the back surface of the chip.
実験条件としては、チップサイズが１０１０ｍｍＸ１０
、エポキシ系の樹脂封止のパッケージサイズが２８ｍｍ
Ｘ２８ｍｍで厚みが３．４ｍｍのものを用いた。そして
、本発明の半導体装置においては、＃８００程度のラッ
プ材でラッピングしたチップ背面に厚さ０．２μｍのＳ
ｉ３Ｎ４膜、ＳｉＯ２膜が形成されている。これに対し
、従来例の半導体装置は、従来どうり、チップ背面はむ
しろ平坦で、また特にチップ背面に３４０ｇ膜が形成さ
れていない。The experimental conditions were that the chip size was 1010 mm x 10
, the package size of the epoxy resin seal is 28mm.
A piece with a width of 28 mm and a thickness of 3.4 mm was used. In the semiconductor device of the present invention, a 0.2 μm thick S
An i3N4 film and a SiO2 film are formed. On the other hand, in the conventional semiconductor device, the back surface of the chip is rather flat, and the 340g film is not particularly formed on the back surface of the chip.
このようにして作成した従来例の半導体装置と本発明の
半導体装置を１５個ずつ混在し、所定の割れテストを行
った。A predetermined cracking test was conducted using a mixture of 15 semiconductor devices of the conventional example and 15 semiconductor devices of the present invention thus produced.
実験方法は、まず１２５℃の高温槽中に２４時間いれて
おき、次に８５°Ｃ３８５％の高温・高湿度の槽にいれ
て吸湿させる。次に２６０℃の半田槽に１０秒いれる。The experimental method was to first put it in a high temperature tank at 125°C for 24 hours, then put it in a high temperature and high humidity tank at 85°C and 385% to absorb moisture. Next, it is placed in a soldering bath at 260°C for 10 seconds.
この後、パッケージに割れが生じたか否かをみて密着性
を判定した。After that, adhesion was determined by checking whether or not the package was cracked.
第４図に示すように、横軸に８５℃、８５％の高温・高
湿度の槽にいれる吸湿時間をとり、縦軸にパッケージが
割れた割合をとっている。As shown in FIG. 4, the horizontal axis shows the moisture absorption time in a bath at 85°C and 85% high temperature and high humidity, and the vertical axis shows the percentage of packages cracked.
図で示されるように、本発明の半導体装置によれば、４
８時間ではまったく割れが生じていない。As shown in the figure, according to the semiconductor device of the present invention, 4
No cracking occurred at all after 8 hours.
これに対して、従来例では７５％に割れが生じている。On the other hand, in the conventional example, cracks occur in 75% of the cases.
このように、本発明の半導体装置の方が従来例の半導体
装置に比べて割れにくい。In this way, the semiconductor device of the present invention is more difficult to break than the conventional semiconductor device.
次に、本発明の実施例について、図を参照しながら説明
する。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜 （ｇ）は、本発明の樹脂封止型半導体
装置の製造工程断面図であり、第２図は、第１図（ｅ）
の工程におけるフィルムキャリア引出しり一ドボンディ
ング工程を、更に詳しく説明するための平面図である。FIGS. 1(a) to 1(g) are cross-sectional views of the manufacturing process of the resin-sealed semiconductor device of the present invention, and FIG. 2 is the same as FIG. 1(e).
FIG. 3 is a plan view for explaining in more detail the film carrier drawer bonding step in the step of FIG.
まず、第１図（ａ）に示すように、表面に能動素子が形
成・配置されたＳｉ基板ｌに、これと同一の表面にメツ
キ法等により厚（Ａｕバンプ２を形成する。このＡｕバ
ンブ２はポリイミドフィルムキャリア５の引出しリード
４をボンディングするためのもので、かなり厚く形成す
る必要がある。First, as shown in FIG. 1(a), thick (Au bumps 2) are formed on the same surface of the Si substrate l on which active elements are formed and arranged by plating or the like. 2 is for bonding the lead 4 of the polyimide film carrier 5, and needs to be formed quite thick.
次に同図（ｂ）に示すように、上述の能動素子が形成・
配置されたｓｔｙ仮１の背面を、粗さｌ６００〜ｌ８０
０のラップ材でラッピングする。Next, as shown in FIG.
The back surface of the placed sty temporary 1 has a roughness of l600 to l80.
Wrap with 0 wrapping material.
ここでのラッピングは、封止用樹脂７と直接、接するこ
とになる背面に一定のサイズ・密度以上の凹凸をつける
ことにより、機械的に封止用樹脂７との密着性を向上さ
せるために行うものであるが、Ｓｉ基板の厚さ調整用の
ラッピングと兼ねさせることもできる。但し、密着性を
良くするために、１１０００以下のランプ材を使用する
必要がある。この後、ラッピングの際にできた表面欠陥
層を取除くため、ＨＦ／ ＨＮＯ，系のエツチング液で
軽（Ｓｉ基板Ｉの背面をエツチングする。The wrapping here is done in order to mechanically improve the adhesion with the sealing resin 7 by creating irregularities of a certain size and density on the back surface that will be in direct contact with the sealing resin 7. However, it can also be used as lapping for adjusting the thickness of the Si substrate. However, in order to improve adhesion, it is necessary to use a lamp material of 11000 or less. Thereafter, in order to remove the surface defect layer formed during lapping, the back surface of the Si substrate I is lightly etched using an HF/HNO etching solution.
なお、背面を粗す方法としては、実施例のラッピング法
以外に、小粒を噴射するブラスト法や化学的エツチング
法によってもよい。Note that as a method for roughening the back surface, in addition to the lapping method of the embodiment, a blasting method in which small particles are sprayed or a chemical etching method may be used.
次に同図（ｃ）に示すように、凹凸をつけたＳｉｉ板１
の背面に、厚さ５００〜５０００人程度のＳｉｎｇ膜３
を、ＣＶＩ）法により被着する。Next, as shown in the same figure (c), the Sii plate 1 with unevenness
There is a Sing film 3 with a thickness of about 500 to 5000 on the back of the
is deposited by the CVI) method.
そして、上記工程後、同図（ｄ）に示すように、ウェハ
をＳｉチップ１１に分割する。この分割はダイシングと
いい、グイサーを使って行われる。After the above steps, the wafer is divided into Si chips 11 as shown in FIG. This division is called dicing and is done using a dicer.
次に、Ｓｉチップ１１をパッケージへ入れる組立工程に
はいる。Next, an assembly process is started in which the Si chip 11 is put into a package.
ここでは、ＴＡＢ方式を用いた組立工程について説明す
る。Here, an assembly process using the TAB method will be explained.
先ず、同図（ｅ）に示すように、Ｓｉチップ１１の引出
しリード４へのボンディングが行われる。First, as shown in FIG. 4(e), bonding of the Si chip 11 to the lead-out leads 4 is performed.
この工程を、第２図を参照しながら更に詳細に説明する
。第２図は、第１図（ｅ）の工程に対応する平面図であ
る。This process will be explained in more detail with reference to FIG. FIG. 2 is a plan view corresponding to the step of FIG. 1(e).
図において、５は厚さ約３５μｍのＳｎメツキ銅箔が被
着されたポリイミドフィルムキャリヤであり、該銅箔の
パターニングにより引き出しり一ド４やテスト用パッド
２１等が形成されている。またＣはポリイミドフィルム
キャリヤの開口部であり、その中央部にはＳｉチップ１
１が配置されている。In the figure, reference numeral 5 denotes a polyimide film carrier on which a Sn-plated copper foil with a thickness of about 35 μm is adhered, and the drawer pad 4, test pad 21, etc. are formed by patterning the copper foil. Further, C is an opening in the polyimide film carrier, and a Si chip 1 is placed in the center of the opening.
1 is placed.
そして、Ｓｉチップ１１上のＡｕバンブ２と引き出しり
−ド４とは熱圧着ボンディングされている。従って、こ
のときテスト用パッド２１を介してＳｉチップ１１に形
成されている能動素子の機能をテストし、不良チップが
チエツクされる。この後、−点鎖線で示す切断部Ｂを切
断すると、ポリイミドフィルムキャリヤ５からＳｉチン
ブ１１が切り離され、弓き出しリード付のＳｉチップが
得られる。The Au bumps 2 on the Si chip 11 and the lead-out leads 4 are bonded by thermocompression. Therefore, at this time, the functions of the active elements formed on the Si chip 11 are tested via the test pads 21 to check for defective chips. Thereafter, by cutting along the cutting portion B indicated by the dashed line, the Si chip 11 is separated from the polyimide film carrier 5, and a Si chip with an exposed lead is obtained.
次に第１図（ｆ）に示すように、銅よりなる強固な材料
で形成されたアウターリード６の先端部分に引出しり一
層４の一端を、熱圧着によりボンディングする。引出し
リード４は、薄くて変形し易いので、別途強固なリード
で補強する必要があるからである。Next, as shown in FIG. 1(f), one end of the drawer layer 4 is bonded to the tip of the outer lead 6 made of a strong material such as copper by thermocompression bonding. This is because the pull-out lead 4 is thin and easily deformed, and therefore needs to be reinforced with a separate strong lead.
次いで同図（ｇ）に示すように、Ｓｉチップ１１周辺を
封止用樹脂７で覆って固める。外部環境の影響を受けに
くいように、および取扱い易いようにするためである。Next, as shown in FIG. 2(g), the periphery of the Si chip 11 is covered with a sealing resin 7 and hardened. This is to make it less susceptible to the influence of the external environment and easier to handle.
封止用樹脂７として、通常、コスト性・耐湿性を考慮し
てエポキシ系のものが使われる。しかし、コスト性は不
利になるが、耐熱性を必要とする用途に用いられる場合
にはシリコン系のものが使われることもある。As the sealing resin 7, an epoxy resin is usually used in consideration of cost and moisture resistance. However, silicon-based materials are sometimes used when used in applications that require heat resistance, although they are disadvantageous in terms of cost.
このようにして作成した本発明の実施例装置においては
、Ｓｉチンプ１１背面に所定の粗さの凹凸が形成されて
いるので、樹脂との密着性が良く、またＳｉチップ１１
背面にＳｉＯ２膜を形成しているので、より一層、密着
性が増している。In the example device of the present invention created in this way, since the unevenness of a predetermined roughness is formed on the back surface of the Si chip 11, the adhesion with the resin is good, and the Si chip 11
Since a SiO2 film is formed on the back surface, the adhesion is further improved.
なお、実施例では５ｉｏｔＷｉを用いた場合について説
明したが、ＳｉＯＮ膜、５ｉ３Ｎａ膜、ダイヤモンド膜
のいずれを用いても、実施例と同様な効果を得ることが
できる。Although the example uses 5iotWi, the same effects as in the example can be obtained by using any of the SiON film, 5i3Na film, and diamond film.
以上のように本発明によれば、Ｓｉチップの背面に所定
の粗さの凹凸が形成されているので、樹脂との密着性が
良い。また、そのチップ１１背面の上に５ｉｎ２膜、
ＳｉＯＮＩＩ！！ｌ、 Ｓｉ３Ｎ４膜またはダイヤモン
ド膜等を形成しているので、より一層、密着性が増して
いる。As described above, according to the present invention, since the unevenness with a predetermined roughness is formed on the back surface of the Si chip, the adhesion with the resin is good. In addition, a 5in2 film is placed on the back of the chip 11.
SiONII! ! 1. Since a Si3N4 film or a diamond film is formed, the adhesion is further improved.
これにより、Ｓｉチップの背面と封止用樹脂との界面に
水分が浸入することが防止できるので、半導体装置の割
れや回路素子の電気的特性の劣化が防止でき、半導体装
置の歩留り、信転度の向上を図ることができる。This prevents moisture from entering the interface between the back surface of the Si chip and the sealing resin, thereby preventing cracks in the semiconductor device and deterioration of the electrical characteristics of the circuit elements, thereby increasing the yield and reliability of the semiconductor device. It is possible to improve the level of performance.
第１図（ａ）〜（ｇ）は、本発明の樹脂封止型半導体装
置の製造工程断面図、
第２図は、本発明の実施例に係るフィルムキャリア引出
しリードボンディング工程を示す平面図、第３図は、従
来例の樹脂封止型半導体装置断面図、
第４図は、従来例と本発明の半導体装置の割れ強度を比
較した図である。
〔符号の説明］
■・・・Ｓｉ基板、
２．１０２−Ａｕバンブ、
３・・・Ｓｉ３Ｎ４膜、ＳｉＯ２膜、
４．１０４・・・引出しリード、
５・・・ポリイミドフィルムキャリア、６．１０６・・
・アウターリード、
７．１０７・・・封止用樹脂、
訊１０８・・・へＵメツキ、
１１．１１１・・・Ｓｉチップ、
２１・・・テスト用パッド
を示す。1(a) to (g) are cross-sectional views of the manufacturing process of a resin-sealed semiconductor device of the present invention; FIG. 2 is a plan view showing a film carrier drawer lead bonding process according to an embodiment of the present invention; FIG. 3 is a sectional view of a conventional resin-sealed semiconductor device, and FIG. 4 is a diagram comparing the cracking strengths of the conventional semiconductor device and the semiconductor device of the present invention. [Explanation of symbols] ■...Si substrate, 2.102-Au bump, 3...Si3N4 film, SiO2 film, 4.104...drawer lead, 5...polyimide film carrier, 6.106.・
・Outer lead, 7.107...Sealing resin, U plating to 108...Si chip, 21...Test pad.
Claims (1)
４膜、ＳｉＯ＿２膜またはダイヤモンド膜が形成され、
少なくとも前記膜の表面が樹脂で覆われていることを特
徴とする樹脂封止型半導体装置。[Claims] The back surface of the semiconductor chip is roughened and has an uneven surface, and an SiON film, Si_3N_, is formed on the uneven back surface.
4 film, SiO_2 film or diamond film is formed,
A resin-sealed semiconductor device, wherein at least a surface of the film is covered with a resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27577788A JPH02122553A (en) | 1988-10-31 | 1988-10-31 | Resin sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27577788A JPH02122553A (en) | 1988-10-31 | 1988-10-31 | Resin sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02122553A true JPH02122553A (en) | 1990-05-10 |
Family
ID=17560257
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27577788A Pending JPH02122553A (en) | 1988-10-31 | 1988-10-31 | Resin sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02122553A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010182973A (en) * | 2009-02-06 | 2010-08-19 | Sony Corp | Semiconductor device |
-
1988
- 1988-10-31 JP JP27577788A patent/JPH02122553A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010182973A (en) * | 2009-02-06 | 2010-08-19 | Sony Corp | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5773896A (en) | Semiconductor device having offsetchips | |
| JP2978861B2 (en) | Molded BGA type semiconductor device and manufacturing method thereof | |
| JP3287310B2 (en) | Semiconductor device and manufacturing method thereof | |
| TWI284960B (en) | Manufacturing method of semiconductor device | |
| US5567656A (en) | Process for packaging semiconductor device | |
| US6753238B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2005064499A (en) | Method of manufacturing semiconductor device | |
| JP2002280485A (en) | Semiconductor device and manufacturing method therefor | |
| JP3262728B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2002231854A (en) | Semiconductor device and its manufacturing method | |
| JP2000269166A (en) | Manufacture of integrated circuit chip and semiconductor device | |
| KR20020068420A (en) | Bond pad of semiconductor device having advantage against thermo-mechanical stress and method for fabricating thereof | |
| JPH11135675A (en) | Semiconductor device and manufacture thereof | |
| JPH02122553A (en) | Resin sealed semiconductor device | |
| JP3682468B2 (en) | Semiconductor integrated circuit device | |
| KR20100032309A (en) | Method of manufacturing semiconductor device | |
| CN1983573A (en) | Semiconductor device and method for fabricating the same | |
| JPH09330992A (en) | Semiconductor device mounting body and its manufacture | |
| KR100968008B1 (en) | A Semiconductor device and a method of manufacturing the same | |
| JP2000228424A (en) | Semiconductor device and manufacture of semiconductor device | |
| KR100336576B1 (en) | Wafer level package | |
| JP3645391B2 (en) | Manufacturing method of semiconductor integrated circuit device | |
| JP3397045B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH10209154A (en) | Semiconductor device | |
| JPH0330347A (en) | Semiconductor device |