JPH02121511A - Current mirror circuit - Google Patents

Current mirror circuit

Info

Publication number
JPH02121511A
JPH02121511A JP63275013A JP27501388A JPH02121511A JP H02121511 A JPH02121511 A JP H02121511A JP 63275013 A JP63275013 A JP 63275013A JP 27501388 A JP27501388 A JP 27501388A JP H02121511 A JPH02121511 A JP H02121511A
Authority
JP
Japan
Prior art keywords
bipolar
reference current
mirror circuit
bipolar transistors
current input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63275013A
Other languages
Japanese (ja)
Inventor
Minoru Sasaki
稔 佐々木
Akira Nakada
章 中田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP63275013A priority Critical patent/JPH02121511A/en
Publication of JPH02121511A publication Critical patent/JPH02121511A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain a current mirror circuit which is extremely stable to the fluctuation of a characteristic by arranging alternately the reference current input bipolar transistors TR and the constant current output bipolar TRs. CONSTITUTION:A current mirror circuit consists of plural bipolar TRs having the same electrical characteristics. For at least one of these bipolar TRs, the emitter electrode is connected to a common power supply terminal with the base and collector electrodes connected to a reference current input terminal respectively by a 1st connection method. For other bipolar TRs, the emitter electrodes are connected to the common power supply terminal with the base electrodes connected to the reference current input terminal respectively by a 2nd connection method. Then the bipolar TRs of the 1st and 2nd connection methods are alternately arranged in the same direction. Thus, the fluctuation of element characteristics if occurs are offset each other since the reference current input bipolar TRs and the constant current output bipolar TRs are laternately arranged.

Description

【発明の詳細な説明】 〔産業上の利用分野1 本発明は、1を子回路技術に関するもので、特に半導体
集積回路に使用して好適なものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to slave circuit technology, and is particularly suitable for use in semiconductor integrated circuits.

〔従来の技術1 電子回路においては、入力電流値に比例した出力電流が
必要となる場合が多くあり、カレントミラー回路が一般
的に使用されている。バイボラ・トランジスタによるカ
レントミラー回路は、エミッタ電極を共通電源端子に接
続し、ベース電極とコレクタ電極を基$1i流入力端子
に接続した基準電流入カバイボーラ・トランジスタと、
エミッタ電極を共通電源端子に接続し、コレクタ電極を
定電流出力端子に接続した定電流出力バイポーラ・トラ
ンジスタから成り、特殊な場合を除き、前記基準電流入
力バイポーラ・トランジスタと定電流出力バイポーラ・
トランジスタとは同一の電気的特性を有するバイポーラ
・、トランジスタが使用される。入力電流のm/n倍の
出力電流を得たい場合は、n個の基準電流入カバイボー
ラ・トランジスタとm(11の定電流出力バイポーラ・
トランジスタとを使用して、所望の出力電流を得ること
ができる。このようなカレントミラー回路を作成する際
に、従来は、配線の簡便なことから、片側に基準電流入
力バイポーラ・トランジスタをn個並べて配置し1反対
側に定電流出力バイポーラ・トランジスタをm個並べて
配置するという手法が行なわれてきた。正確にm/n倍
の出力電流を得る為には、使用する各バイポーラ・トラ
ンジスタの特性が完全に同一でなければならない。
[Prior Art 1] In electronic circuits, an output current proportional to an input current value is often required, and a current mirror circuit is generally used. A current mirror circuit using a bibolar transistor includes a bibolar transistor with a reference current input whose emitter electrode is connected to a common power supply terminal, and whose base electrode and collector electrode are connected to a base current input terminal.
It consists of a constant current output bipolar transistor whose emitter electrode is connected to a common power supply terminal and whose collector electrode is connected to a constant current output terminal.
A bipolar transistor having the same electrical characteristics as the transistor is used. If you want to obtain an output current that is m/n times the input current, use n reference current input bipolar transistors and m (11 constant current output bipolar transistors).
A desired output current can be obtained using a transistor. When creating such a current mirror circuit, conventionally, for ease of wiring, n reference current input bipolar transistors are arranged side by side on one side, and m constant current output bipolar transistors are arranged side by side on the other side. The method of arranging has been used. In order to obtain exactly m/n times the output current, the characteristics of each bipolar transistor used must be completely the same.

般に、半導体集積回路化すれば、同一チップ内では比較
的特性のそろったバイポーラ・トランジスタを得ること
ができるが、それでも製造条件の不均一や動作時の温度
の不均一により、各素子の特性に0.5%〜1.5%程
度の特性変化が生じることは避けられない、第2図は、
従来の技術によるカレントミラー回路で、例としてm=
4、n=3の場合を示している。左側に配置された01
〜Q3が基準電流入力、バイポーラ・トランジスタの右
側に配置された04〜Q7が定電流出力バイポーラ・ト
ランジスタである。製造条件の不均一や温度の不均一に
より、左端の01の特性が+1.5%変動し、以下右へ
向かってQ2の特性が+1%、Q3の特性が+0.5%
、中央のQ4は特性変動なし、Q5、Q6、Qlがそれ
ぞれ−0,5%、−1%、−1,5%変動した場合には
、基準電流が+3%、出力電流が一3%変動するので、
入力対出力では一6%の変動を生じてしまう。
In general, when semiconductor integrated circuits are fabricated, it is possible to obtain bipolar transistors with relatively uniform characteristics within the same chip. However, due to uneven manufacturing conditions and uneven operating temperatures, the characteristics of each element can vary. It is inevitable that a characteristic change of about 0.5% to 1.5% will occur in Figure 2.
In a current mirror circuit according to conventional technology, for example, m=
4, the case where n=3 is shown. 01 placed on the left side
~Q3 is a reference current input, and 04~Q7 placed on the right side of the bipolar transistor are constant current output bipolar transistors. Due to uneven manufacturing conditions and temperature, the characteristics of 01 on the left end fluctuate by +1.5%, and moving towards the right, the characteristics of Q2 +1% and the characteristics of Q3 +0.5%.
, Q4 in the center has no characteristic change, and when Q5, Q6, and Ql change by -0.5%, -1%, and -1.5%, respectively, the reference current changes by +3% and the output current changes by 13%. So,
There is a 6% variation in input versus output.

[発明が解決しようとする課題] 本発明は、従来技術にみられるような欠点を解決しよう
とするもので、素子の特性変動はランダムに発生するも
のではなく、配置場所とその方向に深く関係しているこ
とに着目して、素子の配置方法を改良することによって
特性変動の影響を受けなくすることを目的としている。
[Problems to be Solved by the Invention] The present invention attempts to solve the drawbacks seen in the prior art. Variations in device characteristics do not occur randomly, but are deeply related to the placement location and direction. The aim of this study is to eliminate the effects of characteristic fluctuations by improving the method of arranging elements.

[課題を解決するための手段1 本発明のカレントミラー回路は、同一の電気的特性を有
する複数のバイポーラ・トランジスタから成り、前記複
数のバイポーラ・トランジスタのうち少なくとも1個の
バイポーラ・トランジスタは、エミッタ電極を共通電源
端子に接続し、ベース電極とコレクタ電極を基準電流入
力端子に接続した第1の接続方法で接続されており、他
の少なくとも1個以上のバイポーラ・トランジスタは、
エミッタ電極を共通電源端子に接続しベース電極を基準
電流入力端子に接続した第2の接続方法で接続されてお
り、前記第1の接続方法のバイポーラ・トランジスタと
第2の接続方法のバイポラ°・トランジスタとが交互に
かつ同じ方向に配置されていることを特徴としている。
[Means for Solving the Problems 1] The current mirror circuit of the present invention is composed of a plurality of bipolar transistors having the same electrical characteristics, and at least one bipolar transistor among the plurality of bipolar transistors has an emitter. The at least one other bipolar transistor is connected by a first connection method in which the electrode is connected to a common power supply terminal and the base electrode and the collector electrode are connected to a reference current input terminal.
The bipolar transistor of the first connection method and the bipolar transistor of the second connection method are connected by a second connection method in which the emitter electrode is connected to the common power supply terminal and the base electrode is connected to the reference current input terminal. The transistors are arranged alternately and in the same direction.

〔作 用〕[For production]

本発明の上記の構成によれば、素子の特性変動が生じて
も、基準電流入力バイポーラ・トランジスタと定電流出
力バイポーラ・トランジスタが交互に配置しであるため
、特性変動が相殺され、安定した定電流出力を得ること
ができる。
According to the above configuration of the present invention, even if the characteristics of the device vary, the reference current input bipolar transistors and the constant current output bipolar transistors are arranged alternately, so the characteristic changes are canceled out and a stable constant is maintained. Current output can be obtained.

[実 施 例] 第1図は本発明の実施例で、m=4.n=3の場合のバ
イポーラ・トランジスタの配置を示している。Ql−Q
3が基準電流入力バイポーラ・トランジスタであり、Q
4〜Q7が定電流出力バイポーラ・トランジスタである
。従来例と同様に、左端の04の特性が+1.5%変動
し、以下右に向かってQlの特性が+1%、Q5の特性
が+0.5%、中央の02は特性変動なし、Q6の特性
が−0,5%、Q3の特性が−15%と変動した場合に
は、基準電流入力バイポーラ・トランジスタQ1〜Q3
の特性変動の合計は0%、定電流出力バイポーラ・トラ
ンジスタQ4〜Q7の特性変動も0%となり、そのため
入力電流と出力電流との比率は3:4のまま一定に保た
れていることが明らかである。第3図は本発明の第2の
実施例でありm=6、n=2で、入力電流対出力電流が
1=3の場合を示している。この場合も、製造条件の不
均一や温度の不均一によって生じる各素子の特性変動を
相殺することができ、したがって安定した定電流出力を
得ることができる。
[Example] FIG. 1 shows an example of the present invention, where m=4. The arrangement of bipolar transistors is shown for n=3. Ql-Q
3 is a reference current input bipolar transistor, and Q
4 to Q7 are constant current output bipolar transistors. Similar to the conventional example, the characteristic of 04 on the left side changes by +1.5%, and then towards the right, the characteristic of Ql is +1%, the characteristic of Q5 is +0.5%, the characteristic of 02 in the middle is unchanged, and the characteristic of Q6 is changed by +1.5%. If the characteristic changes to -0.5% and the characteristic of Q3 changes to -15%, the reference current input bipolar transistors Q1 to Q3
The total characteristic variation of is 0%, and the characteristic variation of constant current output bipolar transistors Q4 to Q7 is also 0%, so it is clear that the ratio of input current to output current is kept constant at 3:4. It is. FIG. 3 shows a second embodiment of the present invention, where m=6, n=2, and the input current to output current is 1=3. In this case as well, variations in the characteristics of each element caused by non-uniform manufacturing conditions or non-uniform temperatures can be offset, and a stable constant current output can therefore be obtained.

〔発明の効果〕〔Effect of the invention〕

以上の説明のように、基準電流入カバイボーラ・トラン
ジスタと定電流出力バイポーラ・トランジスタを交互に
配置することにより、特性の変動に対し極めて安定性の
高いカレントミラー回路を得ることが可能になる。
As described above, by alternately arranging reference current input bipolar transistors and constant current output bipolar transistors, it is possible to obtain a current mirror circuit with extremely high stability against fluctuations in characteristics.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のカレントミラー回路の一実施例を示す
回路構成図で、1〜3は基準電流入カバイボーラ・トラ
ンジスタQl−03,4〜7は定電流出力バイポーラ・
トランジスタQ4〜Q7゜lOは基準電流端子、11は
定電流出力端子、12は共通電源端子、である、第2図
は従来のカレントミラー回路を示す構成図、第3図は、
本発明の第2の実施例を示す構成図であり、8〜9は定
電流出力バイポーラ・トランジスタ08〜Q9である。 以上 第
FIG. 1 is a circuit configuration diagram showing one embodiment of the current mirror circuit of the present invention, in which 1 to 3 are reference current input bipolar transistors Ql-03, and 4 to 7 are constant current output bipolar transistors.
Transistors Q4 to Q7゜O are reference current terminals, 11 is a constant current output terminal, and 12 is a common power supply terminal. Fig. 2 is a configuration diagram showing a conventional current mirror circuit, and Fig. 3 is:
It is a block diagram which shows the 2nd Example of this invention, and 8-9 are constant current output bipolar transistors 08-Q9. That's all

Claims (1)

【特許請求の範囲】[Claims]  同一の電気的特性を有する複数のバイポーラ・トラン
ジスタから成り、前記複数のバイポーラ・トランジスタ
のうち少なくとも1個のバイポーラ・トランジスタは、
エミッタ電極を共通電源端子に接続し、ベース電極とコ
レクタ電極を基準電流入力端子に接続した第一の接続方
法で接続されており、他の少なくとも1個以上のバイポ
ーラ・トランジスタは、エミッタ電極を共通電源端子に
接続し、ベース電極を基準電流入力端子に接続しコレク
タ電極を定電流出力端子に接続した第二の接続方法で接
続されており、前記第一の接続方法のバイポーラ・トラ
ンジスタと第二の接続方法のバイポーラ・トランジスタ
とが、交互に配置されていることを特徴とするカレント
ミラー回路。
consisting of a plurality of bipolar transistors having the same electrical characteristics, at least one bipolar transistor among the plurality of bipolar transistors:
The emitter electrode is connected to a common power supply terminal, and the base electrode and the collector electrode are connected to a reference current input terminal. The bipolar transistor of the first connection method is connected to the bipolar transistor of the first connection method and the second A current mirror circuit characterized in that bipolar transistors and bipolar transistors connected in the following manner are arranged alternately.
JP63275013A 1988-10-31 1988-10-31 Current mirror circuit Pending JPH02121511A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63275013A JPH02121511A (en) 1988-10-31 1988-10-31 Current mirror circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63275013A JPH02121511A (en) 1988-10-31 1988-10-31 Current mirror circuit

Publications (1)

Publication Number Publication Date
JPH02121511A true JPH02121511A (en) 1990-05-09

Family

ID=17549665

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63275013A Pending JPH02121511A (en) 1988-10-31 1988-10-31 Current mirror circuit

Country Status (1)

Country Link
JP (1) JPH02121511A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004503974A (en) * 2000-06-09 2004-02-05 サンディスク コーポレイション Multi-output current mirror with improved accuracy

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004503974A (en) * 2000-06-09 2004-02-05 サンディスク コーポレイション Multi-output current mirror with improved accuracy

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