JPH02119719U - - Google Patents
Info
- Publication number
- JPH02119719U JPH02119719U JP2646289U JP2646289U JPH02119719U JP H02119719 U JPH02119719 U JP H02119719U JP 2646289 U JP2646289 U JP 2646289U JP 2646289 U JP2646289 U JP 2646289U JP H02119719 U JPH02119719 U JP H02119719U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- output
- whose
- transistor
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Description
第１図は本考案の一実施例を示す回路図、第２
図は第１図に示す短絡保護回路の起動時の動作を
説明する波形図である。
２……短絡保護回路、３……負荷、４……トラ
ンジスタ、２０……比較回路、Ｒ１〜Ｒ４……レ
ジスタ、Ｃ１，Ｃ２……キヤパシタ。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
This figure is a waveform diagram illustrating the operation of the short-circuit protection circuit shown in FIG. 1 at startup. 2... Short circuit protection circuit, 3... Load, 4... Transistor, 20... Comparison circuit, R1 to R4... Register, C1, C2... Capacitor.
Claims (1)
ツタ（またはコレクタ）が接続され、直流電圧Ｖ
ｏが出力される出力端子にコレクタ（またはエミ
ツタ）が接続され、制御信号がベースに供給され
たトランジスタ、 (B) 前記入力端子に一端が接続され、接地母線
に他端が接続され、第１の分割信号Ｖ＋を出力す
る第１のレジスタＲ１と第２のレジスタＲ２から
なる第１の電圧分割器、 (C) 前記出力端子に一端が接続され、前記接地
母線に他端が接続され、第２の分割信号Ｖ−を出
力する第３のレジスタＲ３と第４のレジスタＲ４
からなり、その抵抗値の関係が ＶｏＲ４／Ｒ３＋Ｒ４＞ＶｉＲ２／Ｒ１＋Ｒ２ すなわち、負荷短絡のない状態でＶ＋＞Ｖ− を満足する第２の電圧分割器、 (D) 前記入力端子に一端が接続され、前記第３
のレジスタＲ３と第４のレジスタＲ４との接続点
に他端が接続された第１のキヤパシタ、 (E) 前記接地母線に一端が接続され、前記第１
のレジスタＲ１と第２のレジスタＲ２との接続点
に他端が接続された第２のキヤパシタ、 (F) 前記第１と第２の分割信号とを比較し、 Ｖ＋＞Ｖ− の場合、前記トランジスタをＯＮ状態にし、 Ｖ＋＜Ｖ− の場合、前記トランジスタをＯＦＦ状態にする
前記制御信号を、前記ベースに向けて送出する比
較回路、 とを含むことを特徴とする短絡保護回路。[Claims for Utility Model Registration] (A) An emitter (or collector) is connected to the input terminal to which the DC voltage Vi is supplied, and the DC voltage V
(B) A transistor whose collector (or emitter) is connected to the output terminal from which o is output, and whose base is supplied with a control signal; (B) one end is connected to the input terminal, the other end is connected to the ground bus, and the first a first voltage divider consisting of a first resistor R1 and a second resistor R2 that output a divided signal V + ; (C) one end connected to the output terminal and the other end connected to the ground bus; A third register R3 and a fourth register R4 that output the second divided signal V −
(D) a second voltage divider whose resistance value relationship is VoR4/R3+R4>ViR2/R1+R2, that is, V + >V − in the absence of a load short circuit; (D) one end of which is connected to the input terminal; , the third
(E) a first capacitor whose other end is connected to the connection point between the resistor R3 and the fourth resistor R4;
a second capacitor, the other end of which is connected to the connection point between resistor R1 and second resistor R2; (F) compares the first and second divided signals, and if V + >V − ; A short-circuit protection circuit comprising: a comparison circuit that turns the transistor on and sends the control signal to the base to turn the transistor off when V + <V − .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2646289U JPH02119719U (en) | 1989-03-07 | 1989-03-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2646289U JPH02119719U (en) | 1989-03-07 | 1989-03-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02119719U true JPH02119719U (en) | 1990-09-27 |
Family
ID=31248110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2646289U Pending JPH02119719U (en) | 1989-03-07 | 1989-03-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02119719U (en) |
-
1989
- 1989-03-07 JP JP2646289U patent/JPH02119719U/ja active Pending
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