JPS5854714U - constant voltage circuit - Google Patents

constant voltage circuit

Info

Publication number
JPS5854714U
JPS5854714U JP15002481U JP15002481U JPS5854714U JP S5854714 U JPS5854714 U JP S5854714U JP 15002481 U JP15002481 U JP 15002481U JP 15002481 U JP15002481 U JP 15002481U JP S5854714 U JPS5854714 U JP S5854714U
Authority
JP
Japan
Prior art keywords
transistor
constant voltage
base
voltage circuit
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15002481U
Other languages
Japanese (ja)
Inventor
村重 伸一
Original Assignee
オムロン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by オムロン株式会社 filed Critical オムロン株式会社
Priority to JP15002481U priority Critical patent/JPS5854714U/en
Publication of JPS5854714U publication Critical patent/JPS5854714U/en
Pending legal-status Critical Current

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  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の定電圧回路を示す分布抵抗を考慮した回
路図、第2図は第1図の定電圧回路の負荷短絡時の状態
を示す回路図、第3図は本考案の1実施例に係る定電圧
回路を示す回路図、第4図は第3図の実施例における負
荷短絡時の状態を示す回路図、そして第5図および第6
図はそれぞれ本考案の他の実施例を示す回路図である。 1、 2. 3・・・・・・トランジスタ、4.13・
・・・・・ツェナダイオード、5,6.14・・・・・
・ダイオード、 −7・・・・・・コンデンサ、8.1
0.12・・・・・・抵抗。 第3図 −筬へM
Figure 1 is a circuit diagram of a conventional constant voltage circuit that takes into account distributed resistance, Figure 2 is a circuit diagram of the constant voltage circuit of Figure 1 when the load is short-circuited, and Figure 3 is an implementation of the present invention. 4 is a circuit diagram showing the constant voltage circuit according to the example, FIG. 4 is a circuit diagram showing the state at the time of load short circuit in the embodiment of FIG. 3, and FIGS.
The figures are circuit diagrams showing other embodiments of the present invention. 1, 2. 3...Transistor, 4.13.
...Zena diode, 5,6.14...
・Diode, -7...Capacitor, 8.1
0.12...Resistance. Figure 3 - M to the reed

Claims (1)

【実用新案登録請求の範囲】 1゛入力端子と負荷との間に挿入されて負荷への出力電
圧を制御する第1のトランジスタと、この第1のトラン
ジスタのベース電流を制御する第2のトランジスタと、
この第2のトランジスタのペニス電流を制御する第3の
トランジスタと、この第3のトランジスタのベースと出
力との間に接続されたツェナダイオードと、前記第2の
トランジスタのベースと出力との間に接続され負荷短絡
時にこの第2のトランジスタのベース電流をシャントし
てこの第2のトランジスタおよび前記第1のトランジス
タをオフさせるダイオードとを具備する定電圧回路にお
いて、前記負荷短絡時における前記第1のトランジスタ
のコレクタ電流を制御する手段を有する−ことを特徴と
する定電圧回路。 2 前記第1のトランジスタのコレクタ電流を制限する
手段が、この第1のトランジスタのエミッタと前記入力
端子との間に挿入された抵抗と、前記第2のトランジス
タのコレクタとこの入力、端子との間の電圧を分圧して
前記第1のトランジスタのベースに付与する分圧手段と
からなる前記実用新案登録請求の範囲第1項記載の定電
圧回路。 3 前記分圧手段が抵抗からなる前記実用新案登録請求
の範囲第2項記載の定電圧回路。 4 前記分圧手段が前記入力端子と前記第1のト   
 □ランジスタのベースとの間に接続されたツェナ −
m−ダイオードを含む前記実用新案登録請求の範囲−第
2項記載の定電圧回路。 5 前記分圧手段が前記入力端子と前記第1のトランジ
スタのベースとの間に接続されたダイオードと抵抗との
直列回路を含む前記実用新案登録請求の範囲第2項記載
の定電圧回路。
[Claims for Utility Model Registration] 1. A first transistor inserted between an input terminal and a load to control the output voltage to the load, and a second transistor to control the base current of the first transistor. and,
a third transistor that controls the penis current of the second transistor; a Zener diode connected between the base and the output of the third transistor; and a Zener diode connected between the base and the output of the second transistor. A constant voltage circuit including a diode that is connected to shunt the base current of the second transistor to turn off the second transistor and the first transistor when the load is short-circuited. 1. A constant voltage circuit comprising means for controlling collector current of a transistor. 2. The means for limiting the collector current of the first transistor includes a resistor inserted between the emitter of the first transistor and the input terminal, and a resistor inserted between the collector of the second transistor and the input terminal. 2. The constant voltage circuit according to claim 1, further comprising voltage dividing means for dividing a voltage between and applying the divided voltage to the base of the first transistor. 3. The constant voltage circuit according to claim 2, wherein the voltage dividing means comprises a resistor. 4 The voltage dividing means connects the input terminal and the first
□Zener connected between base of transistor −
The constant voltage circuit according to claim 2 of the utility model registration claim, which includes an m-diode. 5. The constant voltage circuit according to claim 2, wherein the voltage dividing means includes a series circuit of a diode and a resistor connected between the input terminal and the base of the first transistor.
JP15002481U 1981-10-12 1981-10-12 constant voltage circuit Pending JPS5854714U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15002481U JPS5854714U (en) 1981-10-12 1981-10-12 constant voltage circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15002481U JPS5854714U (en) 1981-10-12 1981-10-12 constant voltage circuit

Publications (1)

Publication Number Publication Date
JPS5854714U true JPS5854714U (en) 1983-04-14

Family

ID=29942771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15002481U Pending JPS5854714U (en) 1981-10-12 1981-10-12 constant voltage circuit

Country Status (1)

Country Link
JP (1) JPS5854714U (en)

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