JPH02119414A - Malfunction preventing circuit for electronic switch - Google Patents

Abstract

PURPOSE:To prevent malfunction due to external noise by allowing a digital circuit to process the operation such that it is not regarded as a normal signal if a photodetection pulse is not inputted consecutively for N times and it is not discriminated as absence of a signal after the pulse is regarded as the normal signal once so long as the photodetection pulse is not missing consecutively for N times. CONSTITUTION:A digital circuit processes the operation such that it is not regarded as a normal signal if a photodetection pulse is not inputted consecutively for N times and it is not discriminated as absence of a signal after the pulse is regarded as the normal signal once so long as the photodetection pulse is not missing consecutively for N times. That is, the electric noise is almost an intermittent noise such as spark noise due to on/off of a switch and the condition of consecutive N-time input is rarely established, then the output stage of a terminal Q of a D flip-flop 2 is unchanged due to noise. Thus, malfunction due to noise is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to electronic switches such as photoelectric switches and proximity switches, and relates to a malfunction prevention circuit that does not easily pick up noise and malfunction.

[Conventional technology]

Generally, electronic switches such as photoelectric switches and proximity switches have an internal pulse oscillation circuit, and a method is used to detect intermittent signals. However, intermittent noise such as spark noise that occurs when contact type switches open and close is also used. As a result, it was difficult to distinguish between signals and noise, often causing malfunctions.

To prevent this malfunction, a synchronization detection method is generally used, but this method only reduces the probability of malfunction due to noise, but cannot prevent malfunctions if the signal and noise overlap. Ta. For this reason, as shown in Figure 4, after synchronization detection is performed, the voltage level is integrated by the integrating circuit, and the detection signal is output only when it reaches a certain level, unless the signal is input several times in succession. A method is used to prevent malfunctions by not treating the signal as an original signal.

On the other hand, the circuits of electronic switches are equipped with short-circuit protection circuits to prevent them from accidentally shorting the power supply during wiring and damaging the output transistors. At the very least, a malfunction occurs in which electrical noise is picked up and the output is cut off. Therefore, a new problem has arisen in that in areas where noise occurs frequently, malfunctions of the short-circuit protection circuit also frequently occur. Therefore, in order to prevent the short-circuit protection circuit from malfunctioning due to noise, an integrating circuit is provided in a part of the circuit to reduce the response speed of the circuit and prevent malfunction.

[Problem to be solved by the invention]

By the way, most of the detection circuits of electronic switches have been miniaturized by using integrated circuits (ICs), and in recent years, it has been considered to integrate the entire circuit into a single chip, but as mentioned above, If an integrating capacitor is used to prevent malfunction, a capacitance of at least several hundred PF is required, so if the entire circuit is integrated into one chip by incorporating the capacitor, the mounting area will become very large. Therefore, it is completely impossible to integrate into one chip in this state.

On the other hand, when the integrating capacitor is externally attached, the number of terminals of the IC increases, resulting in a larger external size, which defeats the purpose of making the IC smaller.

This also applies to short-circuit protection circuits equipped with integration circuits that require capacitors, further increasing the obstacles to miniaturizing the entire circuit or integrating it into a single chip.

Furthermore, since the integrating circuit itself inherently requires time to fall, a time lag occurs between the received light pulse and the detection output, making it impossible to ensure high accuracy.

[Means to solve the problem]

Therefore, in the present invention, the signal is not considered to be a normal signal unless the received light pulse enters N concave spaces in a row, and once it is considered to be a normal signal, the signal is no longer recognized unless the received light pulse passes N times in succession. This solves the above-mentioned problems by processing non-judgmental operations using digital circuits and omitting the use of capacitors.

The means for this purpose are an N-ary counter that uses a synchronization signal as a clock input, a flip-flop that uses a synchronized light reception pulse as a set input, and a reset signal that uses the drive signal of the emitter, and the Q output of this flip-flop that is used as the N-ary counter. an exclusive OR gate Ex-OR which outputs the output of the latch means as a detection signal and operates based on the Q output of the flip-flop and the inverted output of the latch means; A detection circuit is used, which includes an AND gate AND2 established by the output of the logical OR gate Ex-OR and the inverted output of the synchronizing signal, and resets the N-ary counter with the old output of this gate.

An AND gate AND5 established by a specific value of the N-ary counter and a short-circuit signal outputted by a short-circuit of an output transistor, etc. in the subsequent stage, means for inverting the output of the AND gate AND5, and turning off the detection signal by this inverted output. A means was also used in which a short-circuit protection circuit was added to the detection circuit, which included an AND gate AND4 and cut off the detection signal if the short-circuit detection signal continued for a period of time up to the specific count value.

[Function] The Q output of the flip-flop becomes obsolete upon receiving the light reception pulse in the synchronized state, and the latching means for this Q output initially becomes one (
The output Q of the output circuit (on the output circuit side) is Lo, and the output ζ of the other (Ex-OR side) is old. Even if the output of the exclusive OR gate Ex-OR that receives this output becomes Hi when the Q output of the flip-flop is inverted, the counter is not reset because it is cut off by the AND gate AND2 at the next stage.

Therefore, the counter sequentially counts in accordance with the clock input of the synchronization signal, and outputs a signal when it reaches the N value. Triggerd by this signal, the latch means latches the Q state of the flip-flop, and the Q output on the output circuit side becomes Hi and outputs a detection signal.

In addition, if a dropout occurs in the received light pulse for some reason, the output of the exclusive OR gate Ex-OR is reversed to Lo and the counter is not reset and starts counting, but the received light pulse is input before the predetermined number of times is reached. Then, the output of -OR to the exclusive OR gate E is inverted again and the counter is subsequently reset, so that the periodic signal is not sent to the latch means and the output state of the detection signal is maintained.

Next, if the received light pulses are not input consecutively a predetermined number of times due to a light shielding state, the output of the exclusive OR gate Ex-OR remains Lo, the counter reset is not effective, and the count amplifier signal is counted a predetermined number of times. The Lo output of the flip-flop is latched and output of the detection signal is stopped.

On the other hand, in the case of a device equipped with a short-circuit protection circuit, when a short-circuit signal occurs, a counter with a specific count value set in advance will
AND5 outputs the old signal, but it is inverted midway and the Lo signal is sent to the AND gate AND4.
Since a large input is applied, the AND gate AND4 is not established, and the detection signal from the latch means is cut off here, thereby preventing damage to the output transistor due to a short circuit.

〔Example〕

FIG. 1 is a block diagram of an integrated circuit for an electronic switch, which includes comparators CMPI to 3 to which a light emission signal from a light emitter is input via a light receiving circuit/amplifier AMP, a clock signal from an oscillation circuit, and a light receiving signal from a comparator CMPI. An input digital PLL (phase locked loop) circuit,
A detection circuit into which the light reception pulse output from comparator CMP2 is input, and comparators CMPI・3 and PL.
Power is supplied to the IIL circuit, which consists of a stability display circuit that indicates a stable output state based on input from the L circuit, an output circuit that receives the detection signal from the detection circuit, and the oscillation, PLL, stability display, and detection circuits mentioned above. It consists of a parallel type constant voltage circuit.

In this IC, a photodiode is also integrated into a single chip to form a photo HC, and input/output is performed using six terminals.

FIG. 2 is a detailed logic circuit diagram of the detection circuit including the malfunction prevention circuit of the present invention, and ANDI is the comparator CMP2.
The received light pulse from P is transmitted through the transmission/reflection switching circuit.
The AND gate whose condition is satisfied by the synchronization signal output of the LL circuit is a set-priority RS flip-flop that receives the old output of the ANDI and holds the output of the terminal Q at the old value, and also It is reset by receiving the LED drive output. 2 is the above RS flip-flop 1
A D flip-flop receiving an output from a terminal Q of
This input latches the output of terminals Q-Q, which is in a constant state, by the count-up signal (clock signal) of the counter that decreases, and when the input to the terminal is initially old, it is until the next count amplifier signal is received. Q output to Lo,
It is set so that the output of Q is maintained at the old value.

Ex-OR is an exclusive OR gate, which uses the Q output of the RS flip-flop 1 as the A input and the Q output of the D flip-flop 2.
Let the output be the B input. AND2 is an AND gate established by the output of the exclusive OR gate Ex-OR and the output from the inverter INVI of the synchronization signal of the PLL circuit, and its output is input to the reset terminal R of the counter via the AND gate AND3. . 3 is N base (octal here)
In the counter, the inverter INVI is connected to the clock terminal CK.
The signal is inputted, and the inverted signal of the synchronization signal of the PLL circuit is used as the clock signal.

Further, when a pulse is inputted N times (in this case, seven times) in succession, a count-up signal is outputted to the terminal CK as a clock signal for the D flip-flop 2. Reference numeral 4 denotes an RS flip-flop which maintains the current state except when a falling short-circuit signal is input, and outputs Hi to the terminal Q of the D flip-flop 2 to the output circuit via the AND gate AND4.

FIG. 3 is a time chart of the detection circuit, and (1) is the LED drive voltage waveform ( )/16 Duy pulse waveform), which is used for lighting the LED and as a reset input for the RS flipflop 1. (2) The light from the LED is received by the light receiving element, and this is sent to the amplifier A? After amplification by IP, the received light pulse waveform passed through comparator CMPI, (3
) is a synchronizing signal waveform, which also serves as a clock signal for the octal counter at the falling edge of the pulse. (4) is the Q side output signal waveform of RS flip-flop 1, and its waveform is (2)
When there is an output, the old one is held until the next cycle and the next LE is output.
It is reset by the rising waveform of D drive (1).

If there is a subsequent received light pulse waveform (2), the old one is held again. (5) is the output waveform of exclusive OR gate Ex-OR,
(6) is the output waveform of AND3 for resetting the counter 3, and (7) is the count-up signal waveform, which is the clock input to the D flip-flop 2. (8) shows the output waveform of the terminal Q of the D flip-flop, and (9) shows the output waveform of the terminal Q of the D flip-flop.

Note that the initial output waveform of the D flip-flop 2 is set so that the Q output is set to LO% and the u output is set to Hi.

Next, to describe the operation of the circuit of the present invention, the received light pulse (
When the timings of 2) and the synchronization signal (3) match, the AND gate AND1 condition is established, the old output is input to the terminal S of the RS flip-flop 1, and the high ratio output is output from the terminal Q. Since the received light pulse is output through an amplifier circuit, etc., there is a time lag, so it is instantaneously reset by the LED drive output (1) and the output is inverted, but RS flip-flop 1 is set priority type. Tame, LE
Even if it is reset by the D drive output (11), as soon as the light reception pulse is output, the set takes priority and the old output from Q is held.

The old output (4
) is branched and one is exclusive or gate Ex-OR A
The other side is input to the terminal of the D flip-flop 2. Also, the Q output of D flip-flop 2 is input to the B side of the exclusive OR gate Ex-OR, but if the B inputs are old, the exclusive OR gate Ex-OR operates in the same way as an inverter with A inputs. , the waveforms (4) and (5) are in an inverted relationship between to and tl in the time chart of FIG. Therefore, when the received light pulse waveform (1) has an appropriate interval, the output of AND2 maintains Lo, and therefore, resetting the counter 3 does not work.

By the way, the clock input of counter 3 is inverter IN.
Since it is the inverted waveform of the synchronization signal (3) by VI, (
3) Count up at the falling edge of the waveform.

Therefore, when the count pulse (clock signal) is input seven times in a row, the counter 3 outputs the count amplifier signal (7), and at the rising edge of that signal, the D flip-flop 2 in the next stage latches the D input. The state coincides with the state of the output (4) of the RS flip-flop 1 at the time (tl). That is, since the Q output of the RS flip-flop 1 is Hi, the terminal Q of the D flip-flop 2 stores the old value and becomes one input of the AND gate AND4. At the same time, the direction of the D flip-flop 2 is from It to Lo.
, so the B side of the exclusive OR gate Ex-OR is L.
It becomes o. Therefore exclusive or gate t! Since the x-OR functions as a simple buffer, its output waveform (
5) coincides with the Q output (4) of the RSS flip-flop in the interval from t1 to t2. In other words, after tl, the output of the exclusive OR gate Ex-OR becomes old and the output of inverter INVI becomes old, so the AND gate AND
Condition 2 is satisfied and the old output is input to the AND gate AND3, but since the other input normally maintains the old value, the reset terminal R of the counter 3 is operated to reset it. Return the counter value to O.

It is not until the light reception pulses are input seven times in succession that the conditions for the detection output to determine the presence or absence of an object are established.

Next, the 8th pulse is input and counter 3 attempts to count 1, but the condition of AND gate AND2 is met and a reset signal is sent, so it returns to 0 and the counter stops counting without increasing. . Next, when a drop occurs in the received light pulse of number 9/to due to the presence or absence of an object, the input condition A-B of the exclusive OR gate Ex-OR becomes Lo -
It becomes Lo, and the output of (5) increases.

As a result, the AND2 condition is not satisfied and counter 3 is not reset, so the counter accumulates and starts counting up. However, when the light reception pulse is input again at the 11th time, the ungate AND2 condition is satisfied and counter 3 is reset. Therefore, it will return to 0.

In other words, after the received light pulse has been input 7 times or more in a row and is considered to be a regular signal, the pulse input is 2.3 times or more.
Even if the circuit passes through, the count-up signal is not input to the clock terminal of the D flip-flop, so the output from the terminal Q of the D flip-flop to the output circuit is held.

Next, the 12th to 18th indicate a state in which the light reception pulse is missed seven times in a row, that is, a light blocking state rather than noise. During this time, the input condition A- of the exclusive OR gate Ex-OR
B becomes Lo -Lo, and its output beam.

continues to be held, so the counter is not reset.

Therefore, the octal counter 3 counts up in response to the arrival of the clock signal via the inverter INVI, and 1.2.
. . . advances to 6, and when it reaches the value of 7, outputs a count amplifier signal to the clock terminal CK of the D flip-flop 2. At this point (t2), the D input of the D flip-flop 2 is Lo, so the Q output of the D flip-flop 2 is also inverted from the old to Lo, and accordingly, the Q becomes the old, and the exclusive or game 1-Ex -The input condition A-B of OR is satisfied at Lo-old, and its output becomes Hi and the AND gate AND
It is reset by inputting it to the reset terminal of counter 3 via 2.AND3, and returns the value of the counter to 0. At this point (t2), that is, after the 19th pulse, the D flip-flop 2
The Q output of is maintained at Lo, and no detection signal is sent to the output circuit.

In other words, after it is determined that the received light pulse is missing 7 times in a row and there is no output signal, the received light pulse may be missed 2 times due to noise etc.
．． Even after inputting three times, the count-up signal remains D.
Do not input to the clock terminal CK of flip-flop 2.
In other words, since it is not regarded as a regular signal, it is maintained in a state where it is not output to the output circuit, and only when the received light pulse starts to be input seven times in a row is it regarded as a regular signal.

However, most of the electrical noise is intermittent noise such as spark noise caused by turning ON and OFF switches, and the condition of inputting 7 times in a row is almost impossible to achieve, so noise causes the D flip-flop to The output state of terminal Q of No. 2 does not change. Therefore, malfunctions due to noise can be reliably prevented.

Note that the N value of the counter period varies depending on the amplification degree of the entire circuit and the state of the shield, but is usually set to 4 to 0. In other words, if the N value is increased, the probability of malfunction due to noise is reduced, but the response speed during normal operation is reduced, while if the N value is decreased, the response speed is increased, but the malfunction rate due to noise increases.

Next, prevention of malfunction of the short-circuit protection circuit, which is another feature of the circuit of the present invention, will be described. In Figure 2, when a short circuit in the output transistor is detected in the external circuit, the old output is sent to the inverter INV2, but it is inverted by the inverter INV2 and the condition of the AND gate AND3 is not satisfied, so the counter 3 is not reset either. , the counter starts counting.

Here, if the count amplifier value 5 is created by the counter 3 and the AND gate AND5 is used to input this and the old short circuit signal, then when the above short circuit signal reaches 5 counts Vt and the count up signal 5 is output, This signal and the input of the short circuit signal form an AND gate AND5, whose old output is input to means 4 for inverting it. That is, the flip-flop 4 is set with the old output, and Lo is output from Q of the RSS flip-flop, so the subsequent AND gate AND4 is not established. Therefore, the detection signal is no longer output to the output circuit, and damage to the output transistor due to short circuit can be prevented.

By the way, as mentioned above, even if noise etc. is continuous, there are at most 2
Since the count is 3 times, the count amplifier signal 5 will not be output due to the occurrence of noise alone, and the AND gate will not be output.
The condition of ND5 is not satisfied. Furthermore, since the cumulative value of the counter 3 has reached 5 counts, it is assumed that this is not due to noise but a short circuit, and the output is turned off so as not to damage the output transistor.

Once the output transistor is short-circuited, the output of the detection signal is held OFF by the RS flip-flop 4, but since the Q of the D flip-flop 2 is connected to the reset of the RSS flip-flop, the power supply of the electronic switch itself is When the RSS flip-flop is reset, the RSS flip-flop is also reset, and when the output transistor is output again, if the short-circuited state of the output transistor is not released, the short-circuit protection circuit will function again and protect the output circuit.

〔Effect of the invention〕

As described above, the malfunction prevention circuit of the present invention does not consider the received light pulse to be a regular signal unless it inputs N consecutive input pulses. By using a digital circuit to process the operation in which it is not determined that the signal has disappeared unless the signal is lost, malfunctions caused by external noise can be reliably prevented, and since no capacitors are required, the detection circuit can be easily miniaturized into an IC. Can be done.

In addition, the short-circuit protection circuit uses a digital circuit to process the operation in which the signal is not determined to be a short-circuit signal unless it is continuously input for a certain period of time, thereby reliably preventing damage to the output transistor and making it easy to integrate into an IC. .

Therefore, according to the circuit of the present invention, a linear digital hybrid IC mixed with a photodiode, an amplifier, etc.
- This is made possible by Mo5 technology, and the entire electronic switchboard circuit can be completely integrated into one chip.

Furthermore, this IC has a photo IC structure in which a photodiode is integrated into one chip, and furthermore, it is possible to perform input and output with a small number of terminals.

[Brief explanation of drawings]

Figure 1 is a block diagram of an integrated circuit for electronic switches, Figure 2 is a logic circuit diagram of a detection circuit, and Figure 3 is a block diagram of each output (1) to (9).
), and FIG. 4 is a block diagram of a conventional detection circuit and a time chart of each output. In the figure, 1...flip-flop, 2...latch means, 3...counter. that's all

Claims (1)

[Claims] 1. An N-ary counter 3 which uses a synchronization signal as a clock input;
It consists of a flip-flop 1 whose set input is a synchronized light reception pulse and whose reset signal is a drive signal of the emitter, and means 2 which latches the Q output of this flip-flop 1 with the periodic signal of the N-ary counter 3. An exclusive OR gate Ex-OR which outputs the output of the means 2 as a detection signal and operates based on the Q output of the flip-flop 1 and the inverted output of the latch means 2; The N-ary counter 3 is provided with an AND gate AND2 established by the inverted output of the synchronization signal, and the High output of this gate AND2 causes the N-ary counter 3 to
A malfunction prevention circuit for an electronic switch, characterized in that the circuit resets the malfunction of an electronic switch. 2. AND gate AND5 established by a specific numerical value of the N-adary counter and a short circuit signal output by short circuit of the output transistor in the subsequent stage, and this AND gate AND5
short-circuit protection, comprising means 4 for inverting the output of , and an AND gate AND4 for cutting off the detection signal by the inverted output, and turning off the detection signal if the short-circuit detection signal continues for a period of time reaching the specific count value. A malfunction prevention circuit for an electronic switch according to claim 1, further comprising a circuit.