JPH02119172A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simplify a manufacturing process and improve the integrity of an IC by a method wherein well regions and channel stopper regions having conductivity types different from each other are formed in a self-alignment manner by utilizing the difference in thickness between oxide films on a substrate surface. CONSTITUTION:Ions are selectively implanted for impurity introduction by utilizing the difference in thickness between SiO2 films 11 and 14 on a substrate 10 to form an ion-implanted region 15A. Then the ions in the region 15A are activated by a thermal treatment to form a P-type well region 15 so as to be aligned with an N-type well region 13 in a self-alignment manner. Further, when a field SiO2 film 18 is formed by subjecting the substrate 10 surface to thermal oxidation, P-type and N-type channel stopper regions 17 and 19 are selectively formed so as to be aligned with the well regions 13 and 15 and the film 18 in a self-alignment manner, so that a mask alignment process can be eliminated. With this constitution, a manufacturing process can be simplified and a high integrity IC can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technology for manufacturing a semiconductor integrated circuit device that constitutes a complementary insulated gate field effect transistor.

The conventional CMO8IC process involves forming a P-type well region on the surface of an N-type silicon substrate.

There is a method in which N-type and P-type channel stopper regions are formed in alignment with this P-type well region, and a field 5in2 film is further formed by selective oxidation treatment. Such a process is known, for example, from Japanese Patent Laid-Open No. 53-62487 filed by the same applicant as the present applicant. However, the invention described in this publication has a problem in that a special mask alignment process is required to align and form the channel stopper with respect to the P-type well region.

An object of the present invention is to provide a novel method for manufacturing a semiconductor device that solves the above problems.

The manufacturing method according to the present invention is characterized by forming regions of different conductivity types on the surface of a semiconductor substrate in a self-aligned manner, and embodiments shown in the accompanying drawings will be described in detail below.

FIGS. 1a to 10 illustrate 0M according to an embodiment of the present invention.
It shows the manufacturing process of O8IC, and the steps (aJ to (0)) corresponding to each figure are as follows.

(1) For example, a specific resistance of 10 exhibiting a (100) crystal orientation
After preparing a semiconductor substrate 10 made of N-type silicon of Ωα, the surface of this substrate 100 is heated to about 300 A by thermal oxidation.
A film 11 of Sin is formed to a thickness of . And Sin,
After a Si3N4 film 12 is deposited on the film 11 by CVD or the like, this Si, N4 film 12 is selectively etched away in accordance with a predetermined N-type well formation pattern. Hot phosphoric acid is used as the etching solution. Another method is to use plasma. At this time, the Sin film 11 serves as an etching stopper. Next, the remaining S
i. Using the N4 film 12 as a mask, arsenic ions are selectively implanted into the substrate surface, for example, as shown by arrows, to form an ion implantation region 13A. That is, ion implantation is performed on the entire main surface of the substrate 10. however,
Arsenic ions do not reach the surface of the substrate 10 on which the Si, N4 film 12 is formed. Therefore, Si, N4
An ion implantation region 13A defined by membrane 12 is formed. The implant energy was 125 KeV, and the ion dose was 1.3 x 10” atoins / (7
/( is preferred.

(b) Next, the surface of the substrate 10 is thermally oxidized, and the Si, N4 film 1
At the same time, the heat treatment at this time activates and redistributes the arsenic ions in the ion implantation region 13A to form the N-type well region 13 into a Sin film 14 with a thickness of about 110 OA defined by Formed in the surface of the substrate 10 below the membrane 14.

As a result, the N-type well region 13 is formed in a self-aligned relationship with the Sin film 14. A portion of this N-type well region is formed to serve as a channel stopper.

(c) After removing the Si3N41 layer 12, impurities are introduced using the difference in film thickness. That is, thick Sin,
Although it does not pass through the membrane 14, it is thin! For example, I3F with energy such as 55 KeV that passes through the membrane 11.
, ions are selectively implanted into the surface of the substrate 10 to form an ion implantation region 15A.

That is, the ion implantation region defined by the Sin film 14 is selectively formed. The ion dose at this time is preferably 3.8×10 atoms/J.

(d1 Next, for example, 12
By performing heat treatment at 06° C. for 6 hours, ions in the ion implantation region 15A are activated and redistributed, and P-
A mold well region 15 is formed.

At this time, the P-type well region 15 is replaced by the N-type fell region 1.
3 in a self-aligned manner. After this, about 140
By depositing new Si and N4 to the thickness of OA and selectively etching away unnecessary parts, 5isN4 films 16a, 16 corresponding to the active region arrangement pattern are formed.
b, 16c remain.

(elsi, N4 film 16b and Sin, film 14 and Si
, N, and the P-type well region 15 using the film 16C as a mask.
BF and ions are selectively implanted into the surface to form a channel stopper ion implantation region 17A. At this time, the ion implantation energy is preferably 5QI (eV), and the ion dose is preferably 4×10'' atoms/CrI.

(f) Next, using the Si, N4 films 16a, 161), 16c as a mask, the substrate surface is selectively thermally oxidized to form a field SiO, film 18 with a thickness of about 1 μm, and the The heat treatment activates and redistributes ions in the ion implantation region 17A to form the channel stopper P-type region 17, and at the same time, the N-type well region 13 is formed.
An impurity (arsenic) is stretched and diffused under the field Sin and the film 18 to form an N-type region 19 for a channel stopper.

As a result, under the field Sin and the film 18, an N-type region 19 for channel strike and a channel resist is formed in a self-aligned manner with the N-type well region 13, and an N-type well region 13 and a P-type well region 19 are formed. A channel stopper P type region 17 is formed in a self-aligned manner with the type well region 15, and these regions 17° 19 are connected to the field Sin and the film 18.
It is also formed in a self-consistent manner.

(gls! 3N4 films 16a, 16b and the S below these
In, the film is removed by a selective etching process using the field Sin and film 18 as a mask to form holes 18a, tab, and 18c for arranging the active region in the field 5in1 film 18.
Provided for.

(1 refield Sin, holes 18a, 18b of membrane 18.

The surfaces of the N-type well region 13 and P-type well region 15 in 18c are thermally oxidized to form a gate S to a thickness of about 40OA.
In, the films 20, 21a, and 21b are formed. Thereon, (i) a polycrystalline silicon layer with a thickness of about 350 OA was deposited on the SiO films 18, 20, 21a, and 21b by the CVD method, and this was doped with phosphorus to lower the resistance. Further, this low-resistance poly 8i is patterned to form gate electrode layers 22 and 23.

(jl The surfaces of the gate electrode layers 22, 230 and the exposed surfaces of the N-type well region and P-type well region are thermally oxidized and covered with a Si film 24.

(10 Deposit a Si, N4 film 25 on the upper surface of the substrate.

The thickness of this SI, N4 film 25 is preferably about 500 mm.

(1) S l s N < Its 25 Top surface K CV
A 5in2 film 26 with a thickness of 3000 Å is formed by method D. This Sin.

The N film is selectively etched away to form the source and drain regions of the P-channel MOS transistor.
The Si, N4 film 25 on the − type well region 13 is exposed. Thereafter, by ion implantation processing, the P+ type ion implantation region 40A and the P+ type ion implantation region 41A, which are self-aligned with the gate portion (gate electrode layer 22 and the underlying gate film 20), are converted into N− type. It is formed in the well region 13.

Poron is used as the impurity ion at this time. Further, the ion implantation energy is 301 (eV), and the ion implantation dose is 3×10” atoms/(i).

(+r) With the SiOt film 2G remaining, Si, N, and Sin with a thickness of 3000 Å are deposited on the upper surface of the film 25 by CVD again.

Deposit membrane 27. And this Sin, film 27
The S film 26 on the P-type well region 15 where the source and drain regions of the N-channel MOS transistor are to be formed is selectively etched away.
i. The N4 film 25 is exposed.

Thereafter, an ion implantation process is performed to convert the N+ type ion implantation region 42A and the N+ type ion implantation region 43A, which are self-aligned to the gate portion (the gate electrode layer 23 and the gate SiO film 21a thereunder), into a P− type well region. 15. Phosphorus is used as the impurity ion at this time. The ion implantation energy is 8QI (eV), and the ion implantation dose is 8 x 10” atoms/d.
It is.

(n) Remove the S i OH film 27 and 26 and further 1c
si, N.

The film 25 is removed. After that, a thickness of 60 mm was applied to the upper surface of the substrate lO.
A PSG (phosphosilicate glass) film 28 of 00A is deposited. Thereafter, heat treatment is performed in an Nt atmosphere to activate the impurities in the ion implantation regions 40A, 41A, 42A, and 43A, and cause them to be stretched and diffused. As a result, the P-type source region 40. P+ type drain region 41. N+ type drain region 4
2 and N+ type source regions 43 are formed to desired depths. Note that the N-type region 44 is another N-channel MO8)
Shows the source or drain region of the run lister.

(o) PSG film 28 and the underlying Sin film 2
After forming contact holes by selectively etching 4, electrode metals such as A7 are deposited and patterned appropriately to form electrodes (or wiring layers) 29, 3.
0.31.32 is formed. Here, the electrode layer 31 is in ohmic contact with the source region 43 of the N-channel MO8 type FET, and is normally grounded. In addition, the electrode layer 30
is the drain region 42 of the N-channel MO8 type FET.
and the drain region 41 of the P-channel MO8 type FET, and serve as an output terminal. Furthermore, the electrode layer 29 is in ohmic contact with the source region 40 of the P-channel MO8 type PET and is connected to an operating voltage source. Note that the gate electrode layers 22 and 33 are integrated at a portion not shown, and an input terminal is connected to this portion. Due to this connection relationship, the above-mentioned P-channel MO8 type FET and N-channel MO8 type PET
constitutes an inverter circuit. Note that such a connection relationship is just one example and does not limit the present invention in any way.

As described above, according to the method of the present invention, a P-type well region is formed in a self-aligning manner with respect to an N-type well region by utilizing the difference in oxide film thickness, so that special mask alignment work is not required. Unnecessary, again, P.

The MOS transistors of each channel of N are respectively N,
Since it is formed in each well region of P, excellent effects such as characteristics such as VTll are not directly controlled by the impurity concentration of the substrate can be obtained.

Moreover, each of the P and N well regions and the corresponding channel stopper region are formed in a self-aligned manner, and each channel stopper region and the field S i O, film (
Since the isolation insulating film) is formed in a self-aligned manner, the mask alignment work that would otherwise be required is unnecessary in these respects as well, which is advantageous from the viewpoint of process simplification. As mentioned above, eliminating the need for several mask alignment operations means that there is no need to provide mask alignment margins on the substrate, so the manufacturing method according to the present invention It is clear that this method is suitable for realizing the following.

Furthermore, the specific method of the present invention has a major feature in that an 8i, N4 film is formed in step (k). That is, due to the presence of this Si, N4 film, step (1)
And when the Sin films 26 and 27 are selectively etched in steps 8 & 4, the field Sin film 18 is not etched. Therefore, no step is generated in the field Sin or the film 18, so that no step breaks in the wiring layer occur.

According to the method of the present invention, the oxidation-resistant film 7Si, N4 film 12
Although this is used alone, the present invention is not limited thereto, and may be a multilayer film in which Si and N4 films are formed on a polycrystalline silicon film. In particular, a part of this polycrystalline silicon film may be left as is as a wiring or an electrode.

[Brief explanation of the drawing]

FIGS. 1a to 10 illustrate 0M according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of a substrate showing a mounting process of O8IC. 10...Semiconductor substrate, 11.14...5in2 film,
12.16a, 16b, 16c・-8i, N4 film,
13... N-type well region, 15... P-type well region, 17... P-type region for channel stopper, 18
・・・Fee/')' S i Ox Ill 9・
...N-type region for channel stopper, 25...S i
, N4 film, 28...PSO film. Fig./2 Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. J Fig. Fig. Fig. Fig. Cause

Claims (1)

[Claims] 1. A step of selectively disposing a first oxidation-resistant film on the surface of a semiconductor substrate, and a selective impurity introduction treatment using the first oxidation-resistant film as a mask to form a first conductivity type on the surface of the substrate. a step of forming an oxide film on the substrate surface into which the impurity of the first conductivity type has been introduced by selective oxidation treatment using the first oxidation-resistant film as a mask; a step of introducing an impurity of a second conductivity type opposite to the first conductivity type into the substrate surface by selective impurity introduction treatment using the oxide film as a mask after removing the oxidation-resistant film of No. 1; a step of diffusing the introduced impurities of the first conductivity type and the second conductivity type to form a first well region of the first conductivity type and a second well region of the second conductivity type; A step of selectively arranging a film serving as a mask for impurity introduction on each of the second well regions, and a selective impurity introduction process using the oxide film and the film as a mask result in a second well region being formed on the surface of the second well region. A step of introducing an impurity having a conductivity type and a higher impurity concentration than the second well region, and selectively oxidizing the surface of the second well region into which the second conductivity type impurity is introduced. 1. A method for manufacturing a semiconductor device, comprising the step of forming a field oxide film.