JPH02118955U - - Google Patents
Info
- Publication number
- JPH02118955U JPH02118955U JP2658289U JP2658289U JPH02118955U JP H02118955 U JPH02118955 U JP H02118955U JP 2658289 U JP2658289 U JP 2658289U JP 2658289 U JP2658289 U JP 2658289U JP H02118955 U JPH02118955 U JP H02118955U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- thin film
- film transistor
- layer
- contact layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000010409 thin film Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 1
- 239000012535 impurity Substances 0.000 claims 1
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Description
第１図はこの考案の薄膜トランジスタの構成を
示す断面図である。
１……ガラス基板、２……ゲート電極、３……
ゲート絶縁膜、４……半導体層、５……コンタク
ト層、６……ソース電極、７……ドレイン電極。
FIG. 1 is a sectional view showing the structure of the thin film transistor of this invention. 1... Glass substrate, 2... Gate electrode, 3...
Gate insulating film, 4... semiconductor layer, 5... contact layer, 6... source electrode, 7... drain electrode.
Claims (1)
を順に積層し、この半導体層上にコンタクト層を
介して一対の電極を形成してなる薄膜トランジス
タにおいて、 前記半導体層をアモルフアス・シリコンにより
形成し、前記コンタクト層を不純物を含まない微
結晶シリコンで形成したことを特徴とする薄膜ト
ランジスタ。[Claims for Utility Model Registration] A thin film transistor in which a gate electrode, a gate insulating layer, and a semiconductor layer are sequentially laminated on a substrate, and a pair of electrodes are formed on the semiconductor layer via a contact layer, wherein the semiconductor layer is 1. A thin film transistor, characterized in that it is formed of amorphous silicon, and the contact layer is formed of microcrystalline silicon that does not contain impurities.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2658289U JPH02118955U (en) | 1989-03-10 | 1989-03-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2658289U JPH02118955U (en) | 1989-03-10 | 1989-03-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02118955U true JPH02118955U (en) | 1990-09-25 |
Family
ID=31248341
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2658289U Pending JPH02118955U (en) | 1989-03-10 | 1989-03-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02118955U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61214476A (en) * | 1985-03-19 | 1986-09-24 | Agency Of Ind Science & Technol | Thin-film transistor |
-
1989
- 1989-03-10 JP JP2658289U patent/JPH02118955U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61214476A (en) * | 1985-03-19 | 1986-09-24 | Agency Of Ind Science & Technol | Thin-film transistor |