JPH02117688U - - Google Patents
Info
- Publication number
- JPH02117688U JPH02117688U JP2552689U JP2552689U JPH02117688U JP H02117688 U JPH02117688 U JP H02117688U JP 2552689 U JP2552689 U JP 2552689U JP 2552689 U JP2552689 U JP 2552689U JP H02117688 U JPH02117688 U JP H02117688U
- Authority
- JP
- Japan
- Prior art keywords
- package
- lsi
- pad
- multilayer board
- lsi package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Landscapes
- Manufacturing Of Electrical Connectors (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
第１図は本考案の実施例を示す図、第２図は従
来のバイア断線救済方法を示す図である。
図において、１０はＬＳＩパツケージ、１１は
パツド、１２は基板、１３はバイア、１４は電源
供給用パツド、１５はアース供給用パツド、１６
はＬＳＩパツケージの端子、１７，１８はワイヤ
を示す。
FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional via disconnection relief method. In the figure, 10 is an LSI package, 11 is a pad, 12 is a board, 13 is a via, 14 is a power supply pad, 15 is a ground supply pad, 16 is a
1 indicates terminals of the LSI package, and 17 and 18 indicate wires.
Claims (1)
ないパツド１１を複数個設けると共に、該ＬＳＩ
パツケージ１０を搭載する多層基板１２にはパツ
ド１４を設けておき、該ＬＳＩパツケージ１０を
前記多層基板１２に搭載したとき、多層基板１２
内のバイアが断線している場合は、ＬＳＩパツケ
ージ１０に設けたパツド１１を中継点にしてＬＳ
Ｉパツケージ１０の前記断線しているバイアに接
続される端子１６と、基板１２に設けられたパッ
ド１４との間をワイヤ１７，１８にて接続するよ
うにしたことを特徴とするバイア修復構造。 The LSI package 10 is provided with a plurality of pads 11 that are not connected to any one, and the LSI
A pad 14 is provided on the multilayer board 12 on which the package 10 is mounted, and when the LSI package 10 is mounted on the multilayer board 12, the multilayer board 12
If the via in the LSI package is broken, use the pad 11 provided on the LSI package 10 as a relay point to
A via repair structure characterized in that a terminal 16 connected to the disconnected via of the I-package 10 and a pad 14 provided on a substrate 12 are connected by wires 17 and 18.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2552689U JPH02117688U (en) | 1989-03-08 | 1989-03-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2552689U JPH02117688U (en) | 1989-03-08 | 1989-03-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02117688U true JPH02117688U (en) | 1990-09-20 |
Family
ID=31246337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2552689U Pending JPH02117688U (en) | 1989-03-08 | 1989-03-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02117688U (en) |
-
1989
- 1989-03-08 JP JP2552689U patent/JPH02117688U/ja active Pending
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