JPH02117145A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To make gate pad parts have a structure in which the gate pad parts are not peeled off and obtain a transistor that is superior in high-frequency amplification characteristics by forming an insulating film on a semi-insulating semiconductor substrate and forming the gate pad electrodes on the insulating film after forming recessed parts in the insulating film. CONSTITUTION:An insulating film 6 is formed on a semiinsulating semiconductor substrate 1 and recessed parts 7 are formed on the insulating film. Gate pad electrodes are formed on the insulating film including the recessed parts in order to connect gate electrodes 10a to outside terminals. As a transformation layer does not arise very much on the semi-insulating semiconductor substrate during the process of manufacturing and the capacitance of a gate pad electrode part decreases, high frequency amplification characteristics are drastically improved; besides, the gate pad electrodes are not peeled off because of the anchor effect caused by the recessed parts, even though wire bonding is performed. Products excellent in quality are thus manufactured at a high yielding rate.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention provides a high frequency field effect transistor (hereinafter abbreviated as FET) using a novel gate pad formation method.
Relating to a manufacturing method.

<Conventional technology> In recent years, with the development of advanced epitaxial technology and ultra-fine processing technology, MES (Metal
Improving the performance of Semiconductor type FETs or HEMT (High Electron Mob)
The practical application of utility transistors has progressed,
The operating frequency band of these FETs is also 30G)Iz or higher.
It is being expanded to the HF band. This type of high-frequency FET generally has a structure as shown in FIGS. 3 and 4, and has a drain pad 9b on one side of a linear gate electrode 10a for connection to an external terminal. Electrode 9
a and has a similar source pad 8b on the other side.
Three source electrodes 8 connected to each other in a letter-shaped pattern
a, and gate pads 10b for connecting the gate electrodes 10a to external terminals are provided between the E-shaped patterns. The gate pad tab is for connecting the gate electrode 10a of the FET and the external terminal (not shown) of the packaging stem with a lead wire.
The active layer 21 of the FET has MBE (MO
regular BeaIIIEpitaxy), MO
(Metal Org'anic) CV D, V P
When formed by an epitaxial growth method such as E (Vapor Phase Epitaxy), semi-insulating GaA
The mesa is etched up to the s-substrate 22 and formed thereon.

Furthermore, when the active layer of the FET is selectively formed by ion implantation technology or the like, it is formed directly on the semi-insulating GaAs substrate.

However, the surface of the semi-insulating GaAs substrate 22 on which the gate pad 10b is to be formed is always exposed to air or subjected to heat during the process, and thus a metamorphosed layer is likely to occur. The metamorphic layer is
There are more impurities than in other parts of the substrate, resulting in an increase in the impurity concentration under gate pad 10b. Further, the gate pad lob requires a relatively large area in order to effectively bond the lead wire, and as a result, the capacitance of the gate pad portion increases in the total gate input capacitance.

FIG. 5 shows the relationship between the total gate input capacitance Cgt/gate pad capacitance CgP ratio and the impurity concentration N under the gate pad.
Four types of gate pad area Ap/gate area Ag ratio are shown, and the impurity concentration N under the gate is l 017
cm-" (Microwave Journal, April 1978). For example, in PET with a gate length of 1/2μ or less and a relatively large gate pad, Ap/Ag = 20.
~30, so if the impurity concentration N of the substrate under the gate pad becomes N* = 1014 cm-'' due to the above metamorphic layer, the Cgt/Cgp ratio becomes approximately 2 (see point A in Figure 2). , it can be seen that the capacitance CgP of the gate pad portion is as much as half of the total gate input capacitance i1cgt.

The capacitance Cgl) of the gate pad section is the FET shown in Fig. 6.
It is shown as 23 in the equivalent circuit of the input section, and as this capacitance value increases, the source S and gate G.

It acts as a bypass circuit for the high frequency input signal applied between them, and significantly reduces the gain in the high frequency band, particularly in the EHF band. Therefore, FE operating in the EHF band
Regarding T, it is strongly required to reduce the capacitance of the gate pad portion as much as possible.

<Problems to be Solved by the Invention> In order to reduce the capacitance of the gate pad portion in the conventional PET described above, it is necessary to make the area of the gate pad tab as small as possible, or to reduce the surface area of the semi-insulating GaAs substrate 22 under the gate pad 10b. It is possible to reduce the impurity concentration by reducing metamorphosis. Since the former has the aforementioned limitations due to lead wire bonding, an insulating film of SiNx or SiOx is deposited on the semi-insulating GaAs substrate 22 to prevent surface deformation, and a gate pad is formed on it. The latter method is relatively simple and effective.

However, the adhesion strength between the SiNx or SiOx insulating film deposited to a thickness of 1000 Å or more by plasma CVD or the like and the gate pad made of Au/Ti or Au/Mo deposited thereon is weak, and when lead wire bonding There is a problem in that defects such as gate pad peeling occur frequently.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a field effect transistor of high quality and good high frequency amplification characteristics by making the gate pad part a structure that does not peel off during lead wire bonding and reducing the capacitance of the gate pad part. be.

Means for Solving the Problems> In order to achieve the above object, the method for manufacturing a field effect transistor of the present invention includes forming an insulating film on a semi-insulating semiconductor substrate, forming a recess in the insulating film, and then forming a recess in the insulating film. A gate pad electrode for connecting the gate electrode and an external terminal is formed on the insulating film including the recessed portion. Furthermore, before forming the gate pad electrode, the semi-insulating semiconductor substrate on which the gate butt electrode is to be formed is irradiated with an electron beam or an ion beam to reduce the impurity concentration in the surface layer of the semi-insulating semiconductor substrate. You can also.

Effect> Since the field effect transistor according to the present invention has an insulating film formed on a semi-insulating semiconductor substrate, it is possible to eliminate the metamorphic layer that has conventionally existed on the surface of a semi-insulating semiconductor substrate, or even if there is, the entire gate input The effect on capacitance is small, and the capacitance of the gate pad electrode portion is reduced. In addition, 1. Since the recess is formed in the insulating film E, the gate pad electrode formed on the insulating film has good adhesion and is difficult to peel off, allowing for good lead wire bonding. Furthermore, if the semi-insulating semiconductor substrate is irradiated with an electron beam or an ion beam through the insulating film before forming the gate pad electrode, the impurity concentration in the surface layer of the semi-insulating semiconductor substrate can be reduced, and the gate The capacitance of the pad electrode portion is further reduced.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

1 and 2 are a plan view and a sectional view showing an example of a field effect transistor (F'ET) manufactured by the manufacturing method of the present invention, and the appearance shown in FIG. Since there is almost no difference from the example, the same parts are given the same numbers and the explanation will be omitted.

In Figure 2, 1 is a semi-insulating GaAs substrate, 2.3
．． 4 is sequentially deposited by the MBE (molecular beam epitaxy) method, and then a region 5 (the first
As shown in the figure, the buffer layer, n-type GaAs active layer, n"-GaAs
Layer 6 is plasma C so as to fill the mesa etched area.
A SiNx film 7 is deposited as an insulating film to a thickness of approximately 3000 mm using the VD method, and plasma etching is performed on the SiNx film 6 on which the source, gate, and drain electrode pads are to be formed. Depth approximately 250 mm
Cylindrical recess formed in 0 person, 8,9jOa, 10b
After forming an ohmic contact by vapor depositing and alloying an electrode metal on the SiNx film 6, recess etching is performed to form a source electrode (including an electrode pad) and a drain electrode (including an electrode pad) separated from each other as shown in Figure 1.2. including),
Gate electrode, gate electrode pad,! 1 is a padded thin film formed by depositing SiNx on these electrodes and removing the deposited film at the electrode pad portion.

The recessed portion 7 has a hole diameter of 50 μl at the source and drain electrode butt portions 8 b and 9 b, and 20 μl at the gate pad portion tab, and these four portions 7 have a diameter of F” after manufacturing.
Traces of this can be seen on each electrode pad of the ET as circular depressions shown in Figure 1.2. Further, in the source electrode butt portion 8b having a large area, the recess 7 is provided not only at the four corners but also at the center, as shown in FIG.

In PET with the above structure, a semi-insulating GaAs substrate l
Since the thick insulating SiNx film 6 is formed on the substrate layer 2, the GaAs substrate is hardly exposed to heat during the manufacturing process, and a metamorphic layer is not formed on the substrate surface as in the conventional method. rarely occurs. Therefore, the impurity concentration N shown on the horizontal axis in FIG. 3 decreases, and the ratio of the gate pad capacitance Cgl) to the total gate input capacitance fficgt decreases sharply. Furthermore, the thick insulating film 6 reduces the influence of the GaAs substrate on the gate pad capacitance, resulting in a reduction in gate pad capacitance. In this way, the total gate input capacitance was reduced to about 60 to 70% of the conventional example, and the gain of the FET in the EHF' band of 20 GHz or higher was significantly improved.

On the other hand, each electrode pad 8b, 9b, 10b is deeply fitted into the recess 7 provided in the underlying SiNx film 6 at its four corners, so it has strong adhesion and is difficult to peel off, making it suitable for external terminals such as ceramic stems. Even with lead wire bonding, the electrode pads do not peel off and result in defective products as in the conventional case. In other words, high performance FETs can be manufactured with high yield.

Furthermore, as a modified example, before depositing the gate electrode butt tab, 300 S
The iNx film 6 was irradiated with a 150 KeV Xe ion beam. Then, the carrier concentration of the GaAs substrate decreases, and the gate bed capacitance decreases as described above.
EI (The gain of F'ET in the F band has been significantly improved.

In the above embodiment, the SiNx film 6 as an insulating film was formed after partially removing the buffer layer 2 by mesa etching, but the buffer layer 2 was completely removed and an insulating film was formed directly on the Ga substrate 1. may be formed.

It goes without saying that the present invention is not limited to the illustrated embodiment.

<Effects of the Invention> As is clear from the above description, the method for manufacturing a field effect transistor of the present invention includes forming an insulating film on a semi-insulating semiconductor substrate, forming a recess in the insulating film, and then forming a recess in the recess. Since a gate pad electrode for connecting the gate electrode and an external terminal is formed on the above insulating film containing , even if it occurs, its effect on the total gate input capacitance is small, and the capacitance of the gate pad electrode portion is reduced, so high frequency amplification characteristics are greatly improved, and the anchoring effect of the above recess allows the gate pad electrode to be easily used during lead wire bonding. There is no peeling, and high-quality products can be manufactured at high yields. In addition, if the semi-insulating semiconductor substrate is irradiated with an electron beam or the like before forming the gate pad electrode,
By reducing the impurity concentration in the surface layer of the semi-insulating semiconductor substrate, high frequency amplification characteristics can be further improved.

[Brief explanation of drawings]

Figures 1 and 2 show P manufactured by the manufacturing method of the present invention.
3 and 4 are plan views and perspective views showing conventional FETs, and FIG. 5 shows total gate input capacitance/gate pad capacitance and impurity concentration under the gate pad. FIG. 6 is an equivalent circuit of the F'ET input section. ! ... Semi-insulating GaAs substrate, 2... Buffer layer, 3-n-type GaAs active layer, 4-n''-GaAs layer, 6
... SiNx film, 7 ... recess, 8b ... source electrode pad, 9b ... drain electrode pad, 10b ... gate electrode pad, 11 ... passivation film. Patent applicant: Sharp Corporation Agent
Patent attorney: Mr. Hajime and 1 other person Figure 1 ■ Figure 3 Figure 2 Figure 74

Claims (2)

[Claims] (1) After forming an insulating film on a semi-insulating semiconductor substrate and forming a recess in this insulating film, a gate pad electrode is placed on the insulating film including the recess for connecting the gate electrode and an external terminal. A method for manufacturing a field effect transistor. (2) In the method for manufacturing a field effect transistor according to claim 1, before forming the gate pad electrode, an electron beam or A method for manufacturing a field effect transistor, which reduces the impurity concentration in the surface layer of the semi-insulating semiconductor substrate by irradiating with an ion beam.