JPH02117075A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPH02117075A
JPH02117075A JP63269693A JP26969388A JPH02117075A JP H02117075 A JPH02117075 A JP H02117075A JP 63269693 A JP63269693 A JP 63269693A JP 26969388 A JP26969388 A JP 26969388A JP H02117075 A JPH02117075 A JP H02117075A
Authority
JP
Japan
Prior art keywords
circuit wiring
islands
hybrid integrated
integrated circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63269693A
Other languages
Japanese (ja)
Inventor
Shigeki Nara
奈良　茂樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63269693A priority Critical patent/JPH02117075A/en
Publication of JPH02117075A publication Critical patent/JPH02117075A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Landscapes

  • Multi-Conductor Connections (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To realize densification and high integration by providing 2 islands to which a circuit wiring substrate for mounting elements are sticked at fixed intervals, and adhering the circuit wiring substrate to each of the islands. CONSTITUTION:Two islands 3 of a lead frame are arranged at intervals, e.g., 3mm, and circuit wiring substrates 1 are adhered to each of the islands. Leads 2 for terminals are made up alternately so that they can be connected from the respective wiring substrates. Thereby, it is possible to constitute the circuit of 2 sheets of circuit wiring substrates 1 and double an allowable area for stretching a wire around, and also realize densification and high integration.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、混成集積回路の構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to the structure of hybrid integrated circuits.

〔従来の技術〕[Conventional technology]

近年の高品質化、自動実装化の要求に伴ない、トランス
ファーモールド型の混成集積回路が製品化されている。With the recent demand for higher quality and automatic mounting, transfer mold type hybrid integrated circuits have been commercialized.

この混成集積回路は、リードフレーム上に回路配線基板
が貼り付けられ、この回路配線基板上に能動素子等が搭
載され、電気的に接続された後トランスファーモールド
で成型された構造を有している。従来、この種の混成集
積回路は、第２図（ａ）、（ｂ）に示すように、金属製
リードフレームの１つのアイランド３に１枚の回路配線
基板１を接着し、その基板１上のみに素子を搭載し、電
気的接続を行なうことによって構成されていた。なお、
２は端子用リードである。This hybrid integrated circuit has a structure in which a circuit wiring board is pasted on a lead frame, active elements, etc. are mounted on this circuit wiring board, and after being electrically connected, it is molded using a transfer mold. . Conventionally, this type of hybrid integrated circuit has been constructed by bonding one circuit wiring board 1 to one island 3 of a metal lead frame, as shown in FIGS. 2(a) and 2(b). It was constructed by mounting an element only on the chip and making electrical connections. In addition,
2 is a terminal lead.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の混成集積回路は、１つの回路配線基板上
にのみ素子を搭載して構成されているので、高密度化、
高集積化の点において不利である。すな、わち、回路配
線基板上での素子搭載及び配線引き回しの許容面積がせ
ばめられている。The conventional hybrid integrated circuit described above is configured with elements mounted only on one circuit wiring board, so it is possible to increase the density and
This is disadvantageous in terms of high integration. In other words, the allowable area for mounting elements and wiring on a circuit wiring board is becoming narrower.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、金属製リードフレームのアイランド上に回路
配線基板を接着し、能動及び受動素子等を搭載して電気
的に接続した混成集積回路において、素子搭載用の回路
配線基板を貼り付けるアイランドをある一定の間隔をお
いて２つ設は各々のアイランドに回路配線基板を接着し
たことを特徴とする。The present invention relates to a hybrid integrated circuit in which a circuit wiring board is adhered to an island of a metal lead frame, and active and passive elements are mounted and electrically connected. The two islands are arranged at a certain interval, and a circuit wiring board is bonded to each island.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。第１図
は本発明の一実施例を示す図で、第１図（ａ）は平面図
、第１１図（ｂ）は側面図である。リードフレームのア
イランド３は３■の間隔をおいて２つ配置されており、
それぞれに回路配線基板］が接着されている。端子用リ
ード２は、それぞれの配線基板から接続できるように、
交互にたがい違いに加工されている。Next, the present invention will be explained with reference to the drawings. FIG. 1 shows an embodiment of the present invention, with FIG. 1(a) being a plan view and FIG. 11(b) being a side view. Two islands 3 of the lead frame are arranged at an interval of 3cm,
A circuit wiring board] is glued to each. The terminal leads 2 are connected to each wiring board.
They are processed in different ways.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、回路配線基板を接着する
リードフレームのアイランドを２つ設けることによって
、２枚の回路配線基板で構成することができ、素子搭載
及び配線引き回しの許容面積を２倍にすることができ、
高密度化、高集積化できる効果がある。As explained above, the present invention can be configured with two circuit wiring boards by providing two islands of the lead frame to which the circuit wiring boards are bonded, doubling the allowable area for mounting elements and wiring. can be,
This has the effect of increasing density and integration.

【図面の簡単な説明】 第１図（ａ＞は本発明の一実施例の平面図、第１図（ｂ
）はその側面図、第２図（ａ）は従来例の平面図、第２
図（ｂ）はその側面図である。 １・・・回路配線基板、２・・・端子用リード、３・・
・アイランド。[Brief Description of the Drawings] Figure 1 (a) is a plan view of an embodiment of the present invention, Figure 1 (b) is a plan view of an embodiment of the present invention;
) is its side view, Fig. 2(a) is a plan view of the conventional example, and Fig. 2(a) is a plan view of the conventional example.
Figure (b) is its side view. 1...Circuit wiring board, 2...Terminal lead, 3...
・Island.

Claims (1)

【特許請求の範囲】[Claims] 　金属製リードフレームのアイランド上に回路配線基板
を接着し、能動及び受動素子等を搭載して電気的に接続
した混成集積回路において、金属製リードフレームのア
イランドをある一定の間隔をおいて２個配置し、両アイ
ランドに回路配線基板を接着したことを特徴とする混成
集積回路。In a hybrid integrated circuit in which a circuit wiring board is glued onto the island of a metal lead frame, active and passive elements are mounted, and electrically connected, two islands of the metal lead frame are placed at a certain interval. A hybrid integrated circuit characterized by having circuit wiring boards bonded to both islands.
JP63269693A 1988-10-25 1988-10-25 Hybrid integrated circuit Pending JPH02117075A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63269693A JPH02117075A (en) 1988-10-25 1988-10-25 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63269693A JPH02117075A (en) 1988-10-25 1988-10-25 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPH02117075A true JPH02117075A (en) 1990-05-01

Family

ID=17475875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63269693A Pending JPH02117075A (en) 1988-10-25 1988-10-25 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPH02117075A (en)

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