JPH02116129A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02116129A JPH02116129A JP26980788A JP26980788A JPH02116129A JP H02116129 A JPH02116129 A JP H02116129A JP 26980788 A JP26980788 A JP 26980788A JP 26980788 A JP26980788 A JP 26980788A JP H02116129 A JPH02116129 A JP H02116129A
- Authority
- JP
- Japan
- Prior art keywords
- film
- dry etching
- hole
- isotropic dry
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 238000000034 method Methods 0.000 claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000001312 dry etching Methods 0.000 abstract description 13
- 229910052782 aluminium Inorganic materials 0.000 abstract description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 8
- 150000004767 nitrides Chemical class 0.000 abstract description 7
- 239000011229 interlayer Substances 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 abstract 3
- 238000007796 conventional method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に絶縁膜にス
ルーホールを形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming through holes in an insulating film.
従来アルミ配線を有する半導体装置において、絶縁膜、
例えばプラズマ窒化膜に形成するスルーホールは、一般
にフォトレジストをマスクとしてプラズマ窒化膜を等方
性ドライエッチで半分程度エツチングし、残りを異方性
ドライエッチでエツチングして形成していた。Conventionally, in semiconductor devices with aluminum wiring, insulating films,
For example, through holes formed in a plasma nitride film are generally formed by etching about half of the plasma nitride film by isotropic dry etching using a photoresist as a mask, and etching the remaining part by anisotropic dry etching.
上述した従来のスルーホール形成方法では、第３図に断
面構造を示すように、プラズマ窒化膜２に形成されたス
ルーホール５の形状はＡ部分のスロープが急峻でかつＢ
部分が角ぼっているため、その後にスパッタ等により形
成されるアルミニウム膜のステップカバレッジが悪く、
バイポーラＩＣなどの大電流が流れる場合や、微細なパ
ターンの場合において、エレクトロマイグレーション、
断線などの問題を引きおこし、信頼性上およびプロセス
上の欠点がある。また、ステップカバレッジの悪化はス
ルーホール径が小さくなるに従って急激に進行するため
、今後の微細化プロセスに対応する上で重大な欠点とな
る。このなめ、スルーホールの端部がなめらかで配線の
ステップカバレッジが良いスルーホールを形成する技術
が要請されている。In the conventional through-hole forming method described above, as shown in the cross-sectional structure in FIG.
Because the part is rounded, the step coverage of the aluminum film that is subsequently formed by sputtering etc. is poor.
Electromigration,
This causes problems such as wire breakage, and has reliability and process drawbacks. Further, since the step coverage deteriorates rapidly as the through-hole diameter becomes smaller, this becomes a serious drawback in dealing with future miniaturization processes. For this reason, there is a need for a technology for forming through holes with smooth ends and good wiring step coverage.
本発明は絶縁股上にパターン化された開口を有するフォ
トレジスト膜を形成した後、このフォトレジスト膜をマ
スクとして等方性ドライエツチングにより絶縁膜を一部
エッチングし、次いで異方性ドライエツチングにより先
にエツチングした部分をさらにエツチングしてスルーホ
ールを開口したのち、フォトレジスト膜を剥離し、さら
に短時間の等方性ドライエッチをスルーホールに追加し
、ラウンドテーパー処理を行う構成になっている。In the present invention, after forming a photoresist film having patterned openings on the insulation crotch, a part of the insulation film is etched by isotropic dry etching using this photoresist film as a mask, and then anisotropic dry etching is performed first. The etched portion is further etched to open a through hole, the photoresist film is peeled off, and a short period of isotropic dry etching is added to the through hole to perform a round taper process.
本発明について図面を参照して説明する。第１図は本発
明の一実施例の各製造工程における半導体装置の一部断
面図である。まず、アルミ配線１の上にプラズマ窒化膜
の層間膜２を形成した後、眉間膜上にフォトレジスト３
を塗布、パターニングし、等方性ドライエッチにて層間
膜２を半分程度エツチングするく第１図（ａ））。次い
で異方性ドライエッチにて残りの層間Ｈ２をエツチング
してスルーホールを形成する（第１図（ｂ））。The present invention will be explained with reference to the drawings. FIG. 1 is a partial sectional view of a semiconductor device in each manufacturing process according to an embodiment of the present invention. First, after forming an interlayer film 2 of a plasma nitride film on the aluminum wiring 1, a photoresist 3 is applied on the glabellar film.
The interlayer film 2 is coated and patterned, and approximately half of the interlayer film 2 is etched by isotropic dry etching (FIG. 1(a)). Next, the remaining interlayer H2 is etched by anisotropic dry etching to form a through hole (FIG. 1(b)).
ここでフォトレジスト３を除去したのち、さらにラウン
ドテーパー処理のために短時間の等方性ドライエツチン
グをスルーホール部に行なう。この際、プラズマ窒化膜
の膜厚は数百オングストローム程度の膜べりを示す程度
で上下配線間の耐圧の低下はほとんど無い。しかしスル
ーホール開口端部のプラズマ窒化膜はエツチングレイト
が早いため、第１図（ｂ）のＡ部のスロープが第１図（
ｃ）のＡ′部のようになだらかになり、同じく第１図（
ｂ）のＢ部が第１図（ｃ）のＢ′部のようにまるくなり
次にアルミニウム等の金属スパッタ等により形成した場
合、ステップカバレッジが向上する。After removing the photoresist 3, short-time isotropic dry etching is performed on the through-hole portion for round taper processing. At this time, the thickness of the plasma nitride film exhibits a film loss of about several hundred angstroms, and there is almost no drop in breakdown voltage between the upper and lower wirings. However, since the etching rate of the plasma nitride film at the end of the through-hole opening is fast, the slope of section A in FIG.
It becomes gentle like part A' in c), and it also looks like part A' in Figure 1 (
If part B in b) is rounded like part B' in FIG. 1(c) and then formed by sputtering a metal such as aluminum, the step coverage will be improved.
以上説明したように本発明は、スルーホール形成後、フ
ォトレジストを剥離し、短時間の等方性ドライエッチに
よりラウンドテーパー処理を行うことにより、次に形成
する配線金属のステップカバレッジを向上し、半導体装
置の信頼性が向上する効果がある。また、第２図に示す
ように、ステップカバレッジは本発明による方法では従
来技術と比敦して、スルーホール径が縮小していくに従
ってその効果が顕著に表われており、効果が相対的に高
くなってくる。よって今後の微細化プロセスに対応する
上で重大な意味を持ってくる。As explained above, the present invention improves the step coverage of the wiring metal to be formed next by peeling off the photoresist after forming the through hole and performing a round taper process by short-time isotropic dry etching. This has the effect of improving the reliability of the semiconductor device. Furthermore, as shown in Fig. 2, the step coverage effect of the method according to the present invention is comparable to that of the conventional technique, and as the through-hole diameter decreases, the effect becomes more pronounced. It's getting expensive. Therefore, it will have a significant meaning in responding to future miniaturization processes.
尚、実施例ではアルミ配線上に形成した絶縁膜にスルー
ホールを形成した例を示したが、本発明はアルミ配線上
の絶縁膜に限らず半導体基板上に直に形成されている絶
縁膜等どのようなものにも適用できる。Although the example shows an example in which a through hole is formed in an insulating film formed on an aluminum wiring, the present invention is not limited to an insulating film on an aluminum wiring, but can also be applied to an insulating film formed directly on a semiconductor substrate, etc. It can be applied to anything.
成したスルーホールと従来の方法により形成したスルー
ホルのスルーホール径に対するステップカバレッジの値
を示した図である。第３図は従来の方法により形成した
スルーホール形状を示す図である。FIG. 3 is a diagram showing the step coverage values with respect to the through-hole diameters of the through-holes formed by the conventional method and the through-holes formed by the conventional method. FIG. 3 is a diagram showing the shape of a through hole formed by a conventional method.
１・・アルミ配線、２・・・プラズマ窒化膜。1. Aluminum wiring, 2. Plasma nitride film.
代理人 弁理士 内 原 晋Agent Patent Attorney Susumu Uchihara
第１図は本発明のスルーホール形成方法により形成され
るスルーホール形状を時系列順に示した縦断面図である
。第２図は本発明の方法により形（α）
（ｂ）
（Ｃ）
ヌ
図
１ ア１しミ内已彩良
一１４′
スル−ホー１し径（−−）
第２図
葛３図FIG. 1 is a longitudinal cross-sectional view showing in chronological order the shapes of through holes formed by the through hole forming method of the present invention. Fig. 2 shows the shape (α) (b) (C) formed by the method of the present invention.
Claims (1)
口を有するフォトレジストを形成する工程と、このフォ
トレジストをマスクとして前記絶縁膜を等方性エッチン
グにより半分程度エッチングし、次いで残りの半分を異
方性エッチングによりエッチングして開口を形成する工
程と、前記フォトレジストを剥離し、前記開口部に等方
性エッチングを施す工程とを少くとも具備していること
を特徴とする半導体装置の製造方法。A step of forming a photoresist having patterned openings on an insulating film constituting a semiconductor device, etching about half of the insulating film by isotropic etching using this photoresist as a mask, and then etching the remaining half anisotropically. 1. A method for manufacturing a semiconductor device, comprising at least the steps of: forming an opening by etching the photoresist, and peeling off the photoresist and subjecting the opening to isotropic etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26980788A JPH02116129A (en) | 1988-10-25 | 1988-10-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26980788A JPH02116129A (en) | 1988-10-25 | 1988-10-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02116129A true JPH02116129A (en) | 1990-04-27 |
Family
ID=17477448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26980788A Pending JPH02116129A (en) | 1988-10-25 | 1988-10-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02116129A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004356521A (en) * | 2003-05-30 | 2004-12-16 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
-
1988
- 1988-10-25 JP JP26980788A patent/JPH02116129A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004356521A (en) * | 2003-05-30 | 2004-12-16 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
| US7807567B2 (en) | 2003-05-30 | 2010-10-05 | Nec Electronics Corporation | Semiconductor device with interconnection structure for reducing stress migration |
| JP4571785B2 (en) * | 2003-05-30 | 2010-10-27 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
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