JPH0211598U - - Google Patents
Info
- Publication number
- JPH0211598U JPH0211598U JP8565588U JP8565588U JPH0211598U JP H0211598 U JPH0211598 U JP H0211598U JP 8565588 U JP8565588 U JP 8565588U JP 8565588 U JP8565588 U JP 8565588U JP H0211598 U JPH0211598 U JP H0211598U
- Authority
- JP
- Japan
- Prior art keywords
- serial
- dual port
- access memory
- memory section
- selector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000009977 dual effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 1
Description
第１図は本考案を実施したデユアル・ポート・
メモリの要部ブロツク図であり、第２図はその動
作のタイムチヤート図である。
１……シリアル・アクセス・メモリ部、２……
データ用セレクタ、５……アツプカウンタ、８…
…分周器、９……シリアルクロツク用セレクタ、
１３……制御回路。ＣＫ１，ＣＫ２，ＣＫ３，Ｃ
Ｋ４……シリアルクロツク。
Figure 1 shows a dual port system implementing this invention.
This is a block diagram of the main parts of the memory, and FIG. 2 is a time chart of its operation. 1... Serial access memory section, 2...
Data selector, 5... Up counter, 8...
...Frequency divider, 9...Serial clock selector,
13...Control circuit. CK 1 , CK 2 , CK 3 , C
K4 ...Serial clock.
Claims (1)
ツクによるデータの入出力が可能なシリアル・ア
クセス・メモリ部から構成されるデユアル・ポー
ト・メモリにおいて、外部からのシリアルクロツ
クを分周する分周手段を含み前記シリアルクロツ
クを周期の異なる複数のシリアルクロツクに成す
手段と、前記複数のシリアルクロツクのいずれか
１つを外部からの設定により選択できるセレクタ
と、前記セレクタの出力をシリアルアドレスを作
成するための原信号として前記シリアル・アクセ
ス・メモリ部の出力データをシリアルに出力する
手段とを備えたことを特徴とするデユアル・ポー
ト・メモリ。 A dual port memory consisting of a random access memory section and a serial access memory section capable of inputting and outputting data using a serial clock, which includes frequency dividing means for dividing the frequency of an external serial clock. means for forming the serial clock into a plurality of serial clocks with different cycles; a selector for selecting any one of the plurality of serial clocks by external setting; and generating a serial address from the output of the selector. A dual port memory comprising means for serially outputting the output data of the serial access memory section as an original signal for the dual port memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8565588U JPH0211598U (en) | 1988-06-28 | 1988-06-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8565588U JPH0211598U (en) | 1988-06-28 | 1988-06-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0211598U true JPH0211598U (en) | 1990-01-24 |
Family
ID=31310308
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8565588U Pending JPH0211598U (en) | 1988-06-28 | 1988-06-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0211598U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6072020A (en) * | 1983-09-29 | 1985-04-24 | Nec Corp | Dual port memory circuit |
| JPS61290488A (en) * | 1985-06-18 | 1986-12-20 | 日本電気株式会社 | Display controller |
-
1988
- 1988-06-28 JP JP8565588U patent/JPH0211598U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6072020A (en) * | 1983-09-29 | 1985-04-24 | Nec Corp | Dual port memory circuit |
| JPS61290488A (en) * | 1985-06-18 | 1986-12-20 | 日本電気株式会社 | Display controller |
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