JPH02114323A - Memory device with speed converting function - Google Patents

Abstract

PURPOSE:To reduce the area of constitution by writing outputted data from a parallel/serial(P/S) converter in a position specified by a write address outputted from an address generator in response to a write signal from a write signal generator synchronously with a clock with frequency (b). CONSTITUTION:At the time of inputting an operation control signal indicating the set state of a flag 4, the write signal generator 5 generates a write signal synchronizing with a clock with frequency (b). A synchronizing type memory 3 writes n-bit serial data outputted from m P/S converters 2-1 to 2-m synchronously with the clock with the frequency (b) in the positions specified by write addresses generated from the address generator 6 so as to be arrayed by (m) bits in parallel. Thus, the title memory device can be constituted with a small area on an integrated circuit.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a storage device with a speed conversion function, and particularly to a storage device with a speed conversion function, which is a synchronous memory that converts and stores data input at different frequencies. Regarding equipment.

[Conventional technology]

Conventional storage devices with speed conversion function can write and read at different speeds, and can also write and read at different speeds.
A technique is known that performs a first-in, first-out operation using an asynchronous dual-port memory or register file that can be read simultaneously.

In other words, a conventional storage device with a speed conversion function writes data input at a certain frequency a to a dual port memory or register file using a write signal synchronized with that frequency, and writes the written data at a frequency different from frequency a. By reading with a synchronized read signal, the data transfer rate can be converted to perform a first-in, first-out operation.

[Problem to be solved by the invention]

However, since the above-mentioned conventional storage device with speed conversion function uses asynchronous dual-port memory or register files, it requires a much larger area than synchronous memory when implemented on an integrated circuit. There is a drawback that it does.

The purpose of this paper is to create a storage device with a speed conversion function that uses synchronous memory and can be constructed in a smaller area on an integrated circuit than an asynchronous dual-port memory or register file. It is about providing.

[Means to solve the problem]

The first storage device with a speed conversion function: (A) receives m bits of digital signal data input in parallel at a constant frequency a, and reads n bits of data serially into each of m parallel lines; m serial-to-parallel converters that output read n-bit data in parallel; (B) corresponding to each of the m serial-to-parallel converters; (C) m parallel-to-serial converters that read n-bit data in parallel and then output the read n-bit data in series in synchronization with a frequency clock; The operation control signal is set when the serial-to-parallel converter reads all n-bit data, and is reset when the m parallel-to-serial converters output all n-bit data. (D) a write signal generator that generates a write signal synchronized with the frequency clock by inputting an operation control signal of the flag; ) an address generator that receives a write signal from the write signal generator and generates a write address in synchronization with the write signal; (F) writes from the address generator in synchronization with the write signal of the write signal generator; a synchronous memory that writes m-bit parallel and n-bit serial data output from the m parallel-to-serial converters in synchronization with the frequency clock at a position specified by an address; It is configured.

4. The storage device with a speed conversion function of the second invention has the following features: (A) Receiving data of digital signals of constant frequency a'''Cm'Cm bits parallel, n bits each for each m parallel lines. (B) m serial-to-parallel converters that read n-bit data in series and then output the read n-bit data in parallel; (B) corresponding to each of the m serial-to-parallel converters; , m registers that output the read n-bit data in parallel after reading the n-bit data output from each in parallel; (C) the m serial-to-parallel converters are It is set when all bit data is read, and is later reset upon receiving a reset signal, so that operation #
a flag that generates a control signal; (D) a write signal generator that generates a write signal synchronized with the frequency clock and also generates the reset signal of the flag by inputting an operation control signal of the flag; , (E) receiving a write signal from the write signal generator;
(F) an address generator that generates a write address in synchronization with the write signal; A synchronous memory into which m×n bit parallel data outputted by is written.

[Effect]

Next, the operation of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a storage device with a speed conversion function according to the first invention.

As shown in FIG. 1, m serial/parallel converters 1-1.1-2.1-3. ---1-m receives digital and digital signal data input in parallel with constant frequency a'cm bits, reads n bits of data serially for each m parallel lines, and then Each read n
Bit data is output in parallel.

In addition, m parallel/serial converters 2-1.2-
2.2-3.・Old...2-m means m serial/parallel converters 1 1.1 2゜1-3.・・・・・・１
-m, and after reading the n-bit data output from each in parallel, the n-bit data read from each is serially output to the memory 3 in synchronization with the clock of the frequency. are doing.

On the other hand, flag 4 is the serial/parallel converter gl-m
is set when all n-bit data is read, and reset when the parallel-to-serial converter 2-m outputs all n-bit data, so that
Generates an operation control signal and converts the operation control signal to parallel-to-serial converters E 2-1 , 2-2 , 2-3 ,
--2- It is sent to the controller and the write signal generator for control.

Therefore, the write signal generating device 5 generates a write signal synchronized with the clock of frequency S by inputting an operation control signal indicating that the flag 4 is set.

Further, the address generator 6 receives a write signal from the write signal generator 5 and generates a write address in synchronization with the write signal.

For this reason, the synchronous memory 3 uses the write signal generator 5.
m parallel-to-serial converters 2-1 in synchronization with the clock of frequency 1 at the position specified by the write address from the address generator 6 according to the write signal of
．． 2-2゜2-3. ...2-m is writing m-bit parallel and n-bit serial data output.

As a result, data written in the memory 3 in response to m-bit parallel input digital signal data at a constant frequency a can be read out m bits at a time in synchronization with the clock at a frequency a.

Note that the frequency of the clock supplied to the memory 3 is set to 2b,
Thus, the memory 3 can alternately perform frequency write operations and frequency read operations.

Next, the temporal relationship in the operation of the storage device with speed conversion function shown in FIG. 1 will be explained.

The time for n bits to input m bits in parallel at a constant frequency a is n/a, and the time for n bits to output m bits in parallel at a constant frequency is n/b.

Frequency S is set to a higher value than frequency a, so a
<b, and n/a>n/b.

Therefore, the time n/b for outputting n bits is shorter than E n/a when n bits are input.

Furthermore, considering a margin of 1 bit for bit deviations at input and output, n/a - n/
If b > 1 / a + 1 / b, then n >
(b+a)/(ba-a).

Therefore, if n is selected so that n> (b+a)/(ba-a), m serial/parallel converters 1-1
．． 1-2.1-3. ......1-m to m parallel-to-serial converters 2-1゜2-2.2-3.・
・・・・・・ Before the next data is read into 2-m, m
parallel to serial converter 2-1.2-2.2-
3. . . . All data of 2-m will be reliably output.

Note that the writing to the memory 3 described above is performed only when the flag 4 is in the set state in synchronization with the clock with a frequency of 1, so that only n bits are written.

Further, FIG. 2 is a block diagram showing a storage device with a speed conversion function according to the second invention.

As shown in FIG. 2, m serial-parallel converters 21-1.21-2.21-3.・・・・・・21-
m receives digital signal data input in parallel with m bits at a constant frequency a, serially reads n bits of data for each of m parallel lines, and then calculates the read n bits of data in series. Data is output in parallel.

Also, m registers 22-1, 22-2°22-. 3
．． ...22-m is m serial-parallel converters 21-1.21-2.21-3゜...
21-m, and after reading n bits of data output from each in parallel, the n bits of data read from each are output in parallel.

On the other hand, the flag 24 indicates that the serial/parallel converter 21
-m is set when all n bits of data are read, and is later reset upon receiving a reset signal from the write signal generator 25, thereby generating an operation control signal and sending it to the write signal generator 25. It's in control.

Therefore, by inputting the operation #n signal indicating that the flag 2-4 is in the set state, the write signal generator 25 generates a write signal synchronized with the clock of the frequency S, and also generates a reset signal for the flag 24. is occurring.

Further, the address generator 26 includes the write signal generator 2
Upon receiving the write signal No. 5, a write address synchronized with the write signal No. 5 is generated.

Therefore, the memory 23 of the same type 1 is operated by the address generator 26 in accordance with the write signal of the write signal generator 25.
m registers 22-1, 22-2, 22-3.・・・・・・22
The m'X n-bit parallel data output by -m is being written.

Therefore, m×n bit parallel data can be read out from the memory 23 in synchronization with the clock of the same frequency.

Furthermore, by inserting an m×n-n selector into the readout output of the memory 23 and controlling it with the output of a counting device synchronized with the frequency clock, n-bit parallel data synchronized with the frequency clock can be obtained. You can also do it.

Furthermore, in the storage device with a speed conversion function shown in FIG. 2, the frequency for writing m×n bit parallel data into the memory 23 is b/
Since n, if n≧2, the frequency supplied to the memory 23 is b, and writing and deleting to the memory 23 can be performed alternately.

In this way, in the present invention, the data transfer speed can be converted by providing a serial/parallel converter and a parallel/serial converter, or a serial/parallel converter and a register to absorb the difference in data transfer speed. It can be carried out.

Further, by sequentially increasing the memory write and read addresses, first-in, first-out processing can be performed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of a storage device with a speed conversion function according to the first invention.

4 is a time chart showing the operation of the storage device with speed conversion function of the first invention.

The serial-to-parallel conversion device in FIG.
It is composed of.

The 8-stage shift register 31-1.31-2゜31-3 is
Receives digital signal data that is input in parallel with 3 bits at a constant frequency of 6 MHz, reads 8 bits of data serially into each of the 3 parallel lines, and then reads each of the 8 bits of data read in parallel. It is output to.

On the other hand, as shown in FIG. 4, the octal counter 31C counts clocks with a constant frequency of 6 MHz and outputs a carry signal to the gates 31G-1, 31G-2, and 31G.
-3 respectively.

Therefore, gates 31G-1, 31G-2゜31G-3
are 8-stage shift registers 31-1, 31-2, respectively.
The output of the counter 31-3 is gated by the carry signal of the octal counter 31C and sent to the next stage.

In addition, the parallel-to-serial converter shown in FIG.
C and 8-1 selector 32S-1, 323-2, 32S
-3.

After the three registers 32-1.32-2.32-3 read in parallel the 8-bit data output from each of the gates 31G-1, 31G-2, and 31G-3,
Each read 8-bit data is output in series in synchronization with a clock with a frequency of 8 MHz.

On the other hand, as shown in FIG. 4, the octal counter 32C counts clocks with a constant frequency of 8 MHz, and sends the octal counter 32C to the 8-1 selectors 32S-1, 32S-2, and 323-3, respectively. It sends a selection signal that is the content of.

Therefore, the 8-1 selector 32S-1゜323-2.3
28-3 is selected by this selection signal and sends 3-bit parallel and 8-bit serial data to the memory 3.

On the other hand, the flag is composed of a 5R-FF flip-flop 34 and a D-FF flip-flop 34D.

The flip-flop 34 is set by the carry signal of the octal counter 31C and reset by the carry signal of the octal counter 32C to generate an operation control signal, and this operation control signal is time-adjusted by the flip-flop 34D. The signal is then sent to an octal counter 32C and a gate 35 which is a write signal generator.

Therefore, by inputting this operation control signal, the gate 35 generates a write signal synchronized with a clock having a frequency of 8 MHz.

Further, the address counter 36, which is an address generating device, receives a write signal from the gate 35 and generates a write address in synchronization with the write signal.

Therefore, in accordance with the write signal from the gate 35, the synchronous memory 33 sends three 8-1 selectors to the position specified by the write address from the address counter 36, in synchronization with a clock with a frequency of 8 MHz. 32S-1,3
The 3-bit parallel and 8-bit serial data output by the 28-2°32S-3 is written.

Note that the memory 33 is a RAM with 3 bits per word;
Since it operates in synchronization with a 16 MHz clock, a write operation at a frequency of 8 MHz and a read operation at a frequency of 8 MHz can be performed alternately.

Further, FIG. 5 is a block diagram showing an embodiment of a storage device with a speed conversion function according to the second invention.

The serial-to-parallel converter shown in FIG. 5 consists of an 8-stage shift register 51-1.
Advance counter 51C, gates 51G-1, 51G-2,
It is composed of 51G-3, 51G-4.

8-stage shift register 51-1.51-2゜51 3.5
14 receives 4 bits of digital signal data input in parallel at a constant frequency of 6 MHz, reads 8 bits of data serially into each of the 4 parallel lines, and then reads the 8 bits of data that were read in each of the 4 parallel lines. data is output in parallel.

On the other hand, the octal counter 51C counts the clock with a constant frequency of 6 MHz and outputs the carry signal.
51G-1, 51G-2, 51G-3, and 51G-4, respectively.

Therefore, gates 51G-1, 51G-2゜51G-3
, 51G-4 are 8-stage shift registers 51-1, respectively.
．． The output of 51-2, 51-3 and 51-4 is gated by the carry signal of the octal counter 31C and sent to the next stage.

In addition, four registers 52-1, 52-2, 52-3.
52-4 is the gate 51G-1゜51G-2, 51G-
After reading the 8-bit data output from each of the 3 and 51G-4 in parallel, the 8-bit data read from each is output in parallel.

On the other hand, the flag in FIG. 5 is composed of a 5R-FF flip-flop 54 and a D-FF flip-flop 54D.

The flip-flop 54 is set by the carry signal of the octal counter 51C to generate an operation control signal, and this operation control signal is time-adjusted by the flip-flop 54D and sent to the gate 55 of the write signal generator. It is being

15, the write signal generator shown in FIG.
and a D-FF flip-flop 55D.

By inputting this operation control signal, the gate 55 generates a write signal synchronized with a clock having a frequency of 8 MHz.

On the other hand, the flip-flop 55D is the flip-flop 5
4 and flip-flop 54D.
I'm resetting these.

Further, the address counter 56, which is an address generating device, receives a write signal from the gate 55 and generates a write address in synchronization with the write signal.

Therefore, in accordance with the write signal from the gate 55, the synchronous memory 53 stores the four registers 52-- at the position specified by the write address from the address counter 56.
1.52-2.52-3゜52-4 outputs 4X8=
32-bit parallel data is written.

Note that the memory 53 is a RAM of 32 bits per word and operates in synchronization with an 8 MHz clock, so that write operations at a frequency of 8 MHz and read operations at a frequency of 8 MHz can be sufficiently alternately performed.

As described above, the storage device with the speed conversion function of this embodiment uses a synchronous memory and requires a smaller area on an integrated circuit than an asynchronous dual-port memory or a register file. can do.

〔Effect of the invention〕

As explained above, the storage device with a speed conversion function of the present invention uses a synchronous memory, and can be configured in a smaller area on an integrated circuit than an asynchronous dual-port memory or a register file. It has the effect of being able to

[Brief explanation of the drawing]

FIG. 1 shows a storage device with a speed conversion function according to the first invention,
2 is a block diagram showing a storage device with a speed conversion function according to the second invention, FIG. 3 is a block diagram showing an embodiment of the storage device with a speed conversion function according to the first invention, and FIG. The figure is a time chart showing the operation of the storage device with speed conversion function of the first invention, and FIG. 5 is a block diagram showing an embodiment of the storage device with speed conversion function of the second invention. 1-1.1-2.1-3. ~1-m... Serial/parallel converter, 2-1.2-2゜2-3. ~2
-m...Parallel/serial converter, 3...
...Memory, 4...Flag, 5...
-Write signal generator, 6...Address generator, 21-1.21-2.21-3. ~21-m...
...Serial-to-parallel converter, 22-1゜22-
2.22-3. ~22-m...Register, 23
...Memory, 24...Flag, 25.
...Write signal generator, 26...Address generator, 31-1.31-2.31-3...
...8-stage shift register, 31C...octal counter, 31G-1゜31G-2, 31G-3...
・Gate, 32-1゜32-2.32-3...
Register, 32C... Octal counter, 32S-
1,323-2゜323-3...Selector, 3
3...Memory, 34.34D...Flip-flop, 35...Gate, 36...
・Address counter, 51-1゜51-2.51-3
．． 51-4...8-stage shift register, 51C.
...octal counter, 51G-1゜51G-2,5
1G-3, 51G-4...Gate, 52-1.
52-2.52-3.52-4...Register,
53...Memory, 54.54D. 55D...Flip-flop, 55...
・Gate, 56...Address counter. N Dependency NゝSoftness 1: e. (1 to drink)

Claims (1)

[Claims] 1. (A) Receiving data of a digital signal input in parallel with m bits at a constant frequency a, for each m parallel lines,
m serial/parallel converters each reading n bits of data in series and then outputting the read n bits of data in parallel; (B) each of the m serial/parallel converters; Correspondingly, after reading the n-bit data outputted from each in parallel, m parallel-to-serial converters output the read n-bit data serially in synchronization with a clock of frequency b. , (C) is set when the m serial-parallel converters have read all n-bit data, and is reset when the m parallel-serial converters have output all n-bit data. a flag that generates an operation control signal to control the parallel-to-serial converter; (D) generates a write signal synchronized with the clock of frequency b by inputting the operation control signal of the flag; a write signal generator; (E) receiving a write signal from the write signal generator;
an address generator that generates a write address in synchronization with the write signal; A storage device with a speed conversion function, comprising: a synchronous memory for writing m-bit parallel and n-bit serial data output from the m parallel-to-serial converters in synchronization with the above. 2. (A) Receive m-bit digital signal data input in parallel at a constant frequency a, and for each m parallel line,
m serial/parallel converters each reading n bits of data in series and then outputting the read n bits of data in parallel; (B) each of the m serial/parallel converters; Correspondingly, after reading the n-bit data outputted from each in parallel, m registers output the read n-bit data in parallel; (C) the m serial-to-parallel converters; A flag that is set when the device reads all n-bit data and is reset later upon receiving a reset signal to generate an operation control signal; (D) By inputting the operation control signal of the flag; , a write signal generating device that generates a write signal synchronized with the clock of the frequency b and also generates the reset signal of the flag; (E) receiving a write signal from the write signal generating device;
an address generator that generates a write address in synchronization with the write signal; 1. A storage device with a speed conversion function, comprising: a synchronous memory for writing m×n bit parallel data output by a memory device.