JPH02112275A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To assure the title device with stable and low IDDS characteristic by providing one or more of grounded conductor layers through an insulating film insulating film under a high resistance polycrystalline silicon resistor. CONSTITUTION:MOSFETs Q1-Q4, a word line, WL, and a ground line SL are formed, on which an interlayer insulating film 12 is formed, and thereafter a polycrystalline silicon film 18 is formed. With diffusion of an impurity, the polycrystalline silicon 18 is made conductive. Then, it is patterned into a given shape, over the entire surface of which an interlayer insulating film 14 is formed and a contact hole 19 is formed. Further, a thin intrinsic polycrystalline silicon film 20 is formed on the interlayer insulating film 14. Then, a resist mask layer is provided at a portion of the intrinsic polycrystalline silicon film 20 corresponding to a high resistance polycrystalline silicon resistor of the same, and with diffusion of phosphorus and ion-implantation the polycrystalline silicon film not covered with the resist mask layer is given low resistance. Further, after removal of the resist mask layer, the polycrystalline silicon layer 20 is patterned into a given shape to form a wiring layer 15 and high resistance polycrystalline silicon resistors R1, R2. Further, an interlayer insulating film 17, a contact hole 21, and data lines DL, DL' are formed. Hereby, IDDS is stably reduced and made fine.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention is directed to static RAM (Random Acce...
The present invention relates to technology that is particularly effective when applied to high-resistance polycrystalline silicon resistors.

[Conventional technology]

High-resistance polycrystalline silicon load type memory cells are mainly used as memory cells of conventional static RAMs (for example, Japanese Patent Laid-Open No. 130461/1983).

As shown in FIG. 4, this high-resistance polycrystalline silicon load type memory cell includes an inverter consisting of MO3FETQ and high-resistance polycrystalline silicon resistor R1, and MO5FETQ2.
and an inverter consisting of a high-resistance polycrystalline silicon resistor R2, and an information storage flip-flop configured by connecting one output of two imparks to the input of the other, and connecting this flip-flop with the outside of the cell. It has a configuration in which MO3FETs Q3 and Q4 for switching are combined for exchanging information. One end of each of the high-resistance polycrystalline silicon resistors R1 and R2 is connected to a power supply ■. 0 is also connected,
Further, the sources of each of the MO3FETQ, Q2 are grounded. Furthermore, MO5FETQ for the switch
A word line WL is connected to the gates of the transistors 3 and Q, and data lines DL and DL are connected to the drains thereof, respectively.

The present invention relates to the so-called standby current (standby current) consumption current 1, D, in a static RAM having a high-resistance polycrystalline silicon load type memory cell as described above. We investigated ways to reduce the amount of current flowing.

Although the following is not a publicly known technique, it is a technique considered in accordance with the present invention, and its outline is as follows.

The above-mentioned high resistance polycrystalline silicon resistors R1 and R2 are
For example, it was formed as follows.

In other words, the M
OS F E T Q + and Q2 and Q3 and Q.

is formed on a semiconductor substrate, and then an interlayer insulating film is formed, and then a non-doped, i.e., intrinsic (
A polycrystalline silicon film (intrinsic) is formed.

Next, the surface of the region of this intrinsic polycrystalline silicon film that includes a portion that will later become a high-resistance polycrystalline silicon resistor is covered with a mask, and this mask layer is used to diffuse phosphorus and implant ions into the polycrystalline silicon film. By doing the following, the resistance can be lowered. Next, after removing the mask layer, the polycrystalline silicon film is patterned into a predetermined shape to form wiring made of an N° type polycrystalline silicon film whose resistance has been lowered by introducing phosphorus, and an intrinsic polycrystalline silicon film. High resistance polycrystalline silicon resistors R+ and R2 are formed.

[Problems to be Solved by the Invention] However, the above-mentioned prior art has the following problems.

Io. In order to reduce S, the film thicknesses of the high-resistance polycrystalline silicon resistors R1+ and R2 may be made thinner. This is because the resistance values of the high resistance polycrystalline silicon resistors R1 and R2 increase. However, as the film becomes thinner, it becomes more susceptible to the effects of the electric field of the elements below. It becomes a so-called polycrystalline silicon thin film transistor structure in which the wiring layer is used as a source and drain, the high resistance polycrystalline silicon resistors R3 and R2 are used as a substrate, and the lower element is used as a gate electrode,
The resistance values of the high-resistance polycrystalline silicon resistors R1 and R2 change depending on the state of the electric field of the element below (TPT effect). This means that Hayashi, Noguchi, Taiyo, Jpn, J, Ap
pl, Phys, 23 (1984) L819&24
(1985) L4345.

Therefore, with conventional technology, it is difficult to create a high-resistance polycrystalline silicon resistor with a stable and high resistance value, and it is difficult to create a high-resistance polycrystalline silicon loaded static RAM with a stable and low 1009 characteristic. The problem is that it is difficult to make.

The present invention is intended to solve these problems, and its purpose is to provide a stable static RAM technology with low IDf13.

[Means for Solving the Problems] A semiconductor memory device of the present invention includes (1) a high-resistance polycrystalline silicon load type memory cell in which a high-resistance polycrystalline silicon resistor made of an intrinsic polycrystalline silicon film is connected to a wiring layer; The static RAM has at least one grounded conductor layer below the high-resistance polycrystalline silicon resistor via an insulating film.

(2) The conductor layer is characterized in that it is made of a polycrystalline silicon film into which impurities are implanted at a high concentration.

(3) The conductor layer is characterized by being made of a polycide film.

(4) The conductor layer also serves as a ground line for the high-resistance polycrystalline silicon load type memory cell.

[Example 1] FIG. 1(a) is a plan view of an embodiment of the present invention, and FIG. 1(b) is a sectional view of the embodiment of the present invention.

Incidentally, in all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted. Further, the memory cell of the static RAM according to this embodiment has a circuit configuration similar to that shown in FIG.

In the static RAM according to this embodiment, for example, P
For example, 5
A field insulating film 2 such as an in2 film is provided, and element isolation is performed by this field insulating film 2.

A P-type channel stopper region 3 is provided below the field insulating film to prevent the generation of a parasitic channel.

A gate insulating film 4, such as a 5102 film, is provided on the surface of each active region surrounded by the field insulating film 2. On the gate insulating film 4 and the field insulating film 2, for example, a polycrystalline silicon film 5 and a MOIT
A word line WL, a gate electrode 7.8, and a ground line (source line) SL each having a predetermined shape are made of a double-layer film of i, W, etc. and a high melting point metal silicide film 6 containing Si, that is, a polycide film. It is provided. Further, in each of the active regions surrounded by the field insulating film 2, the word #
N-type source region 9 and drain region IO are formed in self-alignment with JiWL, the gate electrode 7.8, and the ground line SL. The word line WL, the source region 9, and the drain region 10 cause the switch MO3FETs Q, , Q, to connect to the gate voltage 1i1i.
i7, M by the drain region 10 and source region 9
O5FETQ, with the gate electrode 8, the source region 9 and the drain region IO, MO5FETQ,
are each configured. Note that the MO5FETQ,
The drain region 10 of the MO5FETQ and the source region 9 of the MO5FETQ are common. Furthermore, these MO3FETs Q, ~Q4 are all so-called LDD (L
has an extremely Doped Drain) structure,
The sos region 9 and the drain region 10 are formed with, for example, 5iO− on the side surfaces of the word line WL and the gate electrode 7.8.
The semiconductor substrate 1 is formed by introducing impurities into the semiconductor substrate 1 in two steps, before and after forming the sidewall 11 consisting of the semiconductor substrate 1.

Moreover, on these MO3FETQ, ~Q4, for example, S
An interlayer insulating film 12 such as an iO2 film is provided. Furthermore, a polycrystalline silicon film 13 which is grounded and into which impurities are implanted at a high concentration is provided in order to shield the electric field of the gate electrodes 7 and 8. Further, on the polycrystalline silicon 13, a second interlayer insulating film 14 such as a 5i02 film is provided. Furthermore, this second
On the interlayer insulating film 14, there is a wiring layer 15 made of an N'' type polycrystalline silicon film having a predetermined shape, and a high resistance polycrystalline silicon resistor R made of an intrinsic polycrystalline silicon film connected to this wiring layer 15. , R2 are provided.The wiring layer 1
5 is the interlayer insulating film 12 and the second interlayer insulating film 14;
and contact holes 16 provided in the gate insulating film 4 to the sos regions 9 of the MO3FETs Q3 and Q, respectively.

By forming the highly doped polycrystalline silicon film 13 under the high-resistance polycrystalline silicon resistors R0 and R2 through the second interlayer insulating film 14 in this manner, MO5FETQ and Q2 can be It is no longer affected by the electric field from the gate electrodes 7 and 8. Therefore, even if the film thickness of the high-resistance polycrystalline silicon resistors R1 and R2 is reduced, the SOI effect does not occur, so a stable high resistance value can be obtained, and I. Leads to o3 low acupuncture.

Furthermore, in order to obtain a sufficient resistance value, the lengths of the high-resistance polycrystalline silicon resistors R1 and R2 have been set to 4 to 5 μm.
However, according to this embodiment, due to the increase in the resistance value due to the thinning of the high resistance polycrystalline silicon resistors R and R2, the lengths of these high resistance polycrystalline silicon resistors R1 and R2 are The thickness can be reduced to, for example, 2 to 4 μm. Therefore, since the area of the memory cell can be reduced by this amount, the integration density can be increased.

Further, in the static RAM according to this embodiment, a third interlayer insulating film 17 such as a PSG film is provided to cover the wiring layer 15 and the high resistance polycrystalline silicon resistors R1 and R2. Data lines DL, DL made of an AL film are provided on the interlayer insulating film 17.

Next, a method of manufacturing the static RAM according to the above embodiment will be explained. First, as shown in FIG. 1(a) and FIG. 1(b), MO5FETQ, ~04, word line WL, ground line SL (diffusion layer of the substrate in this example), etc. are formed, and on these, an interlayer After forming the insulating film 12, a polycrystalline silicon film 18 is formed by, for example, about 1000 people. The polycrystalline silicon 18 is then made into a conductor by diffusing impurities such as phosphorus and boron and performing high-concentration ion implantation (FIG. 2(a)).

Next, it is patterned into a predetermined shape as shown in FIG. 2(b). It is assumed that the polycrystalline silicon 18 is wired so as to be grounded.

Then, a second interlayer insulating film 14 is formed over the entire surface, and a contact hole 19 is formed. Then, a relatively thin intrinsic polycrystalline silicon film 20 is formed on the second inter-FJ insulating film 14 to a thickness of about 500, for example.

Next, as shown in FIG. 2(c), a resist mask layer is provided on a portion of the intrinsic polycrystalline silicon film 20 corresponding to a high-resistance polycrystalline silicon resistor to be formed later, and phosphorus is diffused. , ion implantation, etc., to lower the resistance of the polycrystalline silicon film in the portions not covered with the resist mask layer.

Next, after removing this resist mask layer.

By patterning these polycrystalline silicon layers 20 into a predetermined shape, the wiring layer 15 and high resistance polycrystalline silicon resistors R3 and R2 (only R2 is shown in FIG. 2(c)) are formed. After this, Fig. 1(a) and Fig. 1(b)
), a third interlayer insulating film 17, contact holes 21, and data lines DL, DL are formed to complete the intended static RAM.

According to the manufacturing method described above, a static RAM with a small I ODI+ and stable can be manufactured by a simple process.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, it is also possible to provide the wiring layer 15 with a refractory metal silicide film instead of polycrystalline silicon to lower the resistance and make it conductive.

Alternatively, as shown in FIG. 3, the sources of MO5FETs Q+ and Q2 may be connected to the polycrystalline silicon 15 into which impurities have been implanted at a high concentration via a contact 22 to serve as a ground line for the memory cell.

In this case, the memory cell ground line formed on the substrate becomes unnecessary, so the memory cell size is reduced and miniaturization is possible.

Note that the conductor layer is formed below the high-resistance polycrystalline silicon resistors R1 and R2 via the second interlayer insulating film 14, but the high-resistance polycrystalline silicon resistors R5 and R,
It doesn't have to be all below.

[Effects of the Invention] Among the discoveries disclosed by the present invention, the effects obtained by typical ones are briefly explained below.

That is, I oos can be stably reduced,
Can be miniaturized.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are a main plan view and a BB sectional view thereof, respectively, showing an embodiment of the present invention. Figure 2(a) to Figure 2(c) are the same as Figure 1(a) and Figure 1.
FIG. 4 is a main cross-sectional view for explaining an example of the manufacturing method of the present invention shown in FIG. 3B in order of steps. FIG. 3 is a main plan view showing a modification of the present invention. FIG. 4 is a circuit diagram showing the circuit configuration of a high resistance polycrystalline silicon load type memory cell. Ql ~Q4 R1, R2 V55・・・・WL・・・DL・・・・DL・■・・・・2・3・・・・4・5・・・・6・・・・7・8・・・・・MOS FET High Resistor, power word line, data line, data line, semiconductor substrate, field insulating film, channel stopper, gate insulating film, polycrystalline silicon film, high melting point silicide film, gate electrode, gate electrode 9 ・ ・ l O・ l 1 ・ ・ 12・ ・ l 3 ・ l 4 ・ ・ 15 ・ l 6 ・ 17 ・ 18 ・ 19 ・ 20 ・ 21 ・ 22 ・ 23 ・ ・Source region/drain region side wall/interlayer insulating film/polycrystalline silicon film/second interlayer insulating film・Wiring layer ・Contact hole ・Third interlayer insulating film ・Polycrystalline silicon film ・Contact hole ・Intrinsic polycrystalline silicon film ・Contact hole ・Contact hole ・・Contact hole connecting gate electrode and drain region and above Applicant: Seiko Epson Corporation company

Claims (4)

[Claims] (1) In a semiconductor memory device having a high-resistance polycrystalline silicon load type memory cell in which a high-resistance polycrystalline silicon resistor made of a polycrystalline silicon film is connected to a wiring layer, below the high-resistance polycrystalline silicon resistor: A semiconductor memory device comprising at least one grounded conductor layer with an insulating film interposed therebetween. (2) The semiconductor memory device according to claim 1, wherein the conductor layer is made of a polycrystalline silicon film into which impurities are implanted at a high concentration. (3) The conductor layer includes a polycrystalline silicon film, Mo, Ti,
2. The semiconductor memory device according to claim 1, comprising a polycide film having a two-layer structure with a silicide film of a high melting point metal such as W. (4) The semiconductor device according to claim 1, wherein the conductor layer also serves as a ground line for the high-resistance polycrystalline silicon load type memory cell.