JPH0211181B2 - - Google Patents

Description

TECHNICAL FIELD The present invention relates to an input circuit device, and more particularly, to an input circuit device capable of reducing power consumption at an input section of a digital circuit device such as a timer or a counter.

(Background of the Invention) Conventionally, when inputting a signal to a digital circuit device such as a timer or a counter, a configuration as shown in FIG. 1 has been used. That is, as shown in the figure, a pull-up resistor 2 was connected to the input terminal IN of the digital circuit device, and the input terminal IN was short-circuited or opened by a switch 3 constituted by a mechanical contact or a transistor. .
In this case, the digital circuit device 1 is configured by C-MOSIC, and the output circuit 4 connected to the output terminal OUT also has a circuit configuration including MOSFET, thereby reducing power consumption. It was made up of batteries. With such a configuration, the digital circuit device is made smaller and lighter, making it more convenient to use.

However, in the conventional type, when the input terminal IN is short-circuited by the switch 3, a current I _R flows into the input circuit section via the pull-up resistor 2.
This had the disadvantage of shortening the battery life. As an example, by configuring the digital circuit device 1 using C-MOSLSI, the voltage is 3V and the current is 5μA.
However, even if the input circuit section has a pull-up resistor 2 of, for example, 100KΩ, I _R =
3V/100KΩ = 30μA, and a fairly large current is consumed in the input circuit. In order to reduce current consumption in the input circuit section, a method is used to increase the resistance value of the pull-up resistor 2 as much as possible, but increasing the pull-up resistor 2, that is, the input resistance, has the disadvantage that the noise resistance of the input section deteriorates. Ta. Particularly when a digital circuit device is used as a control device in a control panel or the like, the input signal is applied through a relatively long input signal line, so noise resistance in the input section is required.

(Object of the Invention) In view of the problems with the conventional type described above, an object of the present invention is to reduce power consumption and strengthen noise resistance in an input circuit device for applying input signals to a digital circuit device. It is in.

(Structure of the Invention) The present invention provides a first input signal that is input by opening and closing a DC power supply and a switch connected in series to an input terminal and connected between the input terminal and one electrode of the DC power supply. a gate circuit that samples and pulses a clock signal; a pulse filter circuit that is connected between the gate circuit and the digital circuit device and operates using a second clock signal having a phase different from that of the first clock signal; A pull-up or pull-down resistor is provided, one end of which is connected between the circuit and the pulse filter circuit, and the other end of which is connected to the other electrode of the DC power supply, and the pulse filter circuit is pulsed by the gate circuit. The present invention is characterized in that the output signal corresponding to the input signal is input to the digital circuit device only when the data of the input signal is the same for a predetermined number of consecutive times.

(Effects of the Invention) According to the present invention, current flows through the pull-up or pull-down resistor only during the period when the signal input switch is closed (turned on) and the gate circuit is conductive. Therefore, if the period during which the gate circuit is conductive is t and the period is T, the current flowing through the pull-up or pull-down resistor is reduced to t/T of the conventional type. That is, power consumption at the input section of the digital circuit device can be reduced.

In addition, the input signal is sampled and pulsed, and only when the data of the pulsed input signal is the same for a predetermined number of consecutive times, an output signal corresponding to the input signal is generated and sent to the digital circuit device. I am trying to input it. Therefore, even if the level (data) of the input signal momentarily fluctuates due to noise mixed into the input signal, this fluctuation is not input to the digital circuit device. That is,
Noise resistance can be strengthened.

(Embodiments of the invention) Examples of the invention will be described below with reference to the drawings. FIG. 2 shows the configuration of an input circuit device according to an embodiment of the present invention. In the device shown in the figure, a signal is supplied from an external input terminal (point A) to an input terminal IN (point C) of a digital circuit device 8 via a gate circuit 6 such as a transfer gate and a digital pulse filter 7. It is connected to the. Also,
A resistor 10 is connected between the input terminal D of the digital pulse filter 7 and the negative voltage terminal of the DC power supply 9. The control input of the gate circuit 6 and the clock input terminal CK of the digital pulse filter 7 are supplied with clock signals φ1 and φ2 having a phase difference from each other from the digital circuit device 8, respectively. Further, a switch 11 constituted by a mechanical contact, a transistor, or the like is connected between the external input terminal and a common external terminal D connected to the positive voltage terminal of the DC power supply 9.

The operation of the apparatus shown in FIG. 2 will be explained with reference to the waveform diagram shown in FIG. The level of external input terminal A becomes high level when switch 11 is short-circuited, and switch 1
When 1 is open, the level becomes low. When the voltage at external input terminal A changes as shown in FIG.
It is assumed that the gate circuit 6 is turned on and off.
As a result, the level at the input terminal D of the digital pulse filter 7, that is, the level at the point B, is changed to the level at the external input terminal A.
The signal becomes high level only when the level of the clock signal φ1 is high and the clock signal φ1 is high level. When the pulse width of the clock signal φ1 is t and the period is T, the input current I _R is pulsed and reduced to t/T compared to the conventional case. Next, the thus pulsed input signal (point B) is input to a digital pulse filter 7 operated by a clock signal φ2 whose phase is delayed by, for example, t/2 from the clock signal φ1. This digital pulse filter 7 outputs the input data to the output terminal if, for example, the data at the input terminal D at the rising edge of the clock signal φ2 is the same a predetermined number of times, for example three times in a row. Therefore, as shown in FIG. 3, the level at point C changes to high level at the rising edge of the third clock signal φ2. Further, after the input signal at point A becomes low level, it changes from high level to low level at the third rise of clock signal φ2. Therefore, the output does not change unless external noise is inputted a predetermined number of times or more in synchronization with the clock signal φ2, making it possible to sufficiently increase the noise resistance at the input terminal.

FIG. 4 shows a detailed configuration example of the digital pulse filter 7 in FIG. 2. As shown in the figure, the digital pulse filter consists of, for example, three D-type flip-flops 31, 3 connected in series.
2, 33, each D type flip-flop 31, 32,
AND gate 37 and NOR gate 38 to which the output of 33 is input, and RS flip-flop 3
It is composed of 9 etc. In Figure 4, the input signal applied to input terminal D is clock terminal CK.
The data is sequentially shifted to each D-type flip-flop 31, 32, and 33 by a clock applied to the D flip-flop. Therefore, if the input signal is at a high level for more than three clock signals, the outputs of all D-type flip-flops 31, 32, and 33 will be at a high level, and the output of the AND gate 37 will be at a high level. Then, the RS flip-flop 39 is set and the output Q becomes high level. On the other hand, if the input signal is at a low level for a period of three or more clocks, all D-type flip-flops 31,
Since the outputs of 32 and 33 become low level and the output of NOR gate 38 becomes high level, the output Q of RS flip-flop 39 becomes low level.

FIG. 5 shows operating waveforms of the circuit of FIG. 4. As is clear from the figure, the circuit in Figure 4 has input terminal D.
An output signal having the same level as the input signal is outputted to the output terminal Q only when the input signal at the clock terminal CK remains at the same level for three or more consecutive clock signals at the clock terminal CK.

[Brief explanation of drawings]

1 is a block circuit diagram showing the configuration of a conventional input circuit device, FIG. 2 is a block circuit diagram showing the configuration of an input circuit device according to an embodiment of the present invention, and FIG. 3 is a block circuit diagram showing the configuration of a conventional input circuit device. 4 is a block circuit diagram showing the detailed configuration of the digital pulse filter used in the device shown in FIG. 2, and FIG. 5 is the circuit shown in FIG. 4. FIG. 2 is a waveform diagram for explaining the operation of FIG. DESCRIPTION OF SYMBOLS 1...Digital circuit device, 2...Pull-up resistor, 3...Switch, 4...Output circuit, 5...DC power supply, 6...Gate circuit, 7...Digital pulse filter, 8...Digital circuit device, 9...DC power supply, 10...Resistor, 11...Switch, 3
1, 32, 33...D-type flip-flop, 37
...And Gate, 38...Noah Gate, 39...
...RS flipflop.

Claims (1)

[Claims] 1. A gate circuit that uses a first clock signal to sample and pulse an input signal input by a DC power supply and a switch that is connected in series to an input terminal and opens and closes between the input terminal and one electrode of the DC power supply. a pulse filter circuit connected between the gate circuit and the digital circuit device and operated by a second clock signal having a phase different from the first clock signal; and one end between the gate circuit and the pulse filter circuit. and a pull-up or pull-down resistor whose other end is connected to the other electrode of the DC power source; An input circuit device characterized in that an output signal corresponding to the input signal is input to the digital circuit device only when the input signals are the same.