JPH02111115A - Digital picture filter - Google Patents

Abstract

PURPOSE:To reduce the scale of the circuit by forming a group comprising one or plural picture elements so that the picture elements are symmetrical in the center column and providing a coefficient transmission circuit sending the same coefficient to a multiplier corresponding to each picture element included in each group. CONSTITUTION:An output side of a multiplier M11 is connected to an adder 5a1 to which an output of a multiplier M12 is connected, and the adder 5a1 is adds an output signal of the multiplier M11 and the result of operation of the multiplier M11. The output of the adder 5a1 is connected to the adder 5a2 to which the output of a multiplier M13 is connected via a register 4a2 and the adder 5a2 adds the result of sum up to the pre-stage and the result of calculation of the multiplier M13. Through the constitution above, the multipliers M2a-M2d multiply supplied picture element data A-E and coefficient data sent from coefficient registers 3a-3d. Then the result of multiplication of the multipliers provided to each row is summed and the result is sent from final stage adders 5a4, 5b4, 5c4, 5d4, 5e4 provided to each row and each picture element is subject to picture processing according to the result of operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital image filter that can quickly rewrite the coefficients of a multiplier included in a digital image filter used in a copying machine or the like.

[Prior art and its problems] In a multiplier used in a digital image filter that is necessary for image processing in a copying machine, for example, multiplication is required to perform image processing on image data read by a scanner or the like. This is done by multiplying the image data by the data held by the multiplier in the multiplier. There are two methods for fixing the coefficients held by the multiplier to one type, and a method for writing the coefficients using software. If the coefficients are fixed, image processing that involves the coefficients held by the multiplier, such as edge enhancement or smoothing of objects displayed on the screen, cannot be performed. On the other hand, in the conventional method of writing coefficients, for example, in the case of a 5×5 multiplier, reading coefficient data into the multiplier is
There is a problem that it takes time to rewrite the coefficients of the multiplier. Furthermore, 25 coefficient rewriting circuits are required to rewrite the coefficients of the multiplier, and there is a drawback that the circuit scale becomes large.

The present invention was made to solve the above-mentioned problems, and it is possible to quickly rewrite the coefficients held by the multiplier.
Furthermore, it is an object of the present invention to provide a digital image filter that can reduce the circuit scale.

[Means for Solving the Problems] The present invention provides a multiplier that is provided in one-to-one correspondence with pixels arranged in rows and columns and sends out a signal for performing image processing on each pixel; a coefficient sending circuit that forms groups of one or more pixels so as to be symmetrical in the columns, and sends the same coefficient to a multiplier corresponding to each pixel included in each group. It is characterized by

[Operation Pixels constituting an image are arranged in rows and columns, and are divided into groups each consisting of one or more pixels.

The groups divided in this manner are arranged symmetrically with respect to the center column that equally divides the total number of columns in which pixels are arranged, thereby speeding up the image processing time.

The number of coefficient sending circuits that send the same coefficient to the multiplier corresponding to the group is the same as the number of groups, and the number of coefficient sending circuits is reduced by integrating the pixels in the group, and the number of coefficient sending circuits is reduced by integrating the pixels. The circuit scale is reduced.

[Example] For example, 5×5 pixels each having 5 pixels in each row and column
The digital image filter corresponds one-to-one to each pixel l arranged as shown in FIG.
As shown in the figure, a total of 25 multipliers 2 corresponding to 25 pixels 1 are provided. If the pixels are arranged as shown in Figure 2, the axis of symmetry is column A at the center of all columns, and the same coefficients are sent to the multipliers so that symmetrical pixel filter processing is performed. There are already known circuits that can speed up image processing. In this embodiment, the multipliers 2 are further integrated into, for example, four groups, and the same coefficients are sent from the coefficient register to the multipliers belonging to each group.

The pixel grouping in this embodiment is, for example, the third grouping.
As shown in the figure, it is divided into four groups 1 to 4, group 1 has a total of +6p1 pixels located in the 1st row, 5th row, −th column, and 5th column, and group 2 has Second
There are a total of four pixels 1 located in row 3, row 2, column 4, row 4, column 2, and row 4, column 4, and group 3 is the second row and column 4,
A total of 4 located in the 3rd row, 2nd column, the 3rd row, 4th column, and the 4th hitting ball column.
pixels! , and group 4 is pixel 1 located in the third hit ball row. Note that the arrangement of each multiplier (indicated by M in the figure) indicated by numbers 1, 12, etc. in FIG. 1 is the same as that indicated by numbers 11, 12, etc. in FIG. 3. The Q terminal of each multiplier 2a corresponding to a total of 16 pixels belonging to group l among the pixels l shown in FIG.
Each Q terminal of the multiplier 2b is connected to the output side of the coefficient register 3b and corresponds to a total of four pixels belonging to group 2, and is connected to the output side of the coefficient register 3b, corresponding to a total of four pixels belonging to group 3. Each Q terminal of the multiplier 2c is connected to the output side of the coefficient register 3c, and the Q terminal of the multiplier 33 (multiplier 2d) corresponding to one pixel 33 belonging to group 4 is connected to the output side of the coefficient register 3d. be done.

Multiplier 1 corresponding to the pixels in the first row. or multiplier,
are supplied with pixel data A, respectively, and pixel data B is supplied to each of the multipliers 1 to 25 corresponding to the pixels in the second row. Data C is supplied to the multiplier. , or the multiplier 45 are supplied with the pixel data D, and the multiplier 1
The pixel data E is supplied to the multiplier 5.

The output side of the multiplier 1 is connected to an adder 5a to which the output side of the multiplier 2 is connected via a register (represented by R in the figure) 4a. ．．
The output signal of the multiplier 2 is added to the calculation result of the multiplier 2.

The output side of the adder 5al is connected to the adder 5az, to which the output side of the multiplier 3 is connected via the register 4at. Perform the addition of . Similarly, the calculation results of multiplier 2 and multiplier 5 are sequentially added, and the final result is added to adder 5a.
Be sent out from 4. Also, multiplier 3, multiplier. 2. Multiplier. , and multiplier, , are also connected to registers and adders as described above, and the final results are sent to adders 5b, 5c, 5d, 5e, respectively.
It is sent from 4.

With this configuration, the multipliers 2a to 2d multiply the supplied pixel data A to E by the coefficient data sent out by the coefficient renostars 3a to 3d. Then, the multiplication results of the multipliers provided in each row are added, and the final stage adders 5a4.5b, 5c4.5d, provided in each row
, 5ea, and each pixel undergoes image processing according to the calculation result.

Furthermore, by changing the coefficient data sent out by the four coefficient registers 3a to 3d, it is possible to change the coefficient data supplied to all 25 multipliers 2a to 2d in this embodiment. Therefore, if the time required to rewrite the coefficient data of one multiplier is 25× in the conventional example, it takes 4× in the present embodiment.
It takes only t time, and the time required for the rewriting can be shortened.

Furthermore, since the multipliers 2 are integrated into four groups corresponding to each pixel, there is no need to provide a coefficient register for each pixel as in the conventional example, and four coefficient registers 3a to 3d are sufficient. Therefore, the circuit scale of the digital image filter as a whole can be reduced.

In this embodiment, the number of arrays of pixels and the number of arrays of multipliers corresponding thereto are set to 5×5, but the number is not limited to this and may be set to a plurality of N×multipliers.

Furthermore, although the number of divided groups of pixels is set to four, it is not limited to this.

[Effects of the Invention] As detailed above, according to the present invention, image processing time can be sped up by arranging integrated groups of arranged pixels in a symmetrical arrangement with respect to the center column. can.

Furthermore, since it is sufficient to provide one set of coefficient sending circuits for each group, the number of coefficient sending circuits is reduced, and the circuit scale of the digital image filter can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the array of multipliers used in the digital image filter of the present invention, and FIG. 3 is a diagram showing the pixel arrangement of the digital image filter. It is a diagram. ■...Pixels, 2 a, 2 b, 2 c and 2 d
...multiplier, 3a, 3b, 3c and 3d・
... Coefficient register, D a 415 b 4 ; 5
C4+ 5 d a + J e 4 ”・Adder. Figure 2

Claims (1)

[Claims] (1) A multiplier that is provided in one-to-one correspondence with pixels arranged in rows and columns and sends out a signal for image processing of each pixel; 1. A digital image filter comprising: a coefficient sending circuit that forms groups of one or more pixels and sends the same coefficient to a multiplier corresponding to each pixel included in each group.