JPS62266794A - Memory device - Google Patents

Abstract

PURPOSE:To obtain a simple device suitable for the spatial filtering of an image, etc., by accessing a memory cell array by selectively outputting consecutive addresses from an address decoder in response to an address information. CONSTITUTION:The row address decoder 6 generates consecutive three row addresses in response to a row address information, and similarly, the column address decoder 9 generates consecutive three addresses. With these consecutive addresses, the memory cell array 1 is accessed, and the information in nine pieces of memory cells adjacent to each other with three vertically and three horizontally is read out and outputted in parallel via a demultiplexer 9 and an output buffer in an order determined by a counter 11. In such a way, the memory device of a simple constitution which is suitable for the spatial filtering of an image, etc., is produced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a storage device, and more particularly to a storage device suitable for inputting image data to a circuit that performs processing such as spatial filtering of an image.

[Prior art]

Processing such as image noise removal, edge enhancement, and contour extraction is generally performed by spatial filtering. In this spatial filtering, for example, when the kernel size is 3×3, as shown in FIG. 3, by weighting the data of the pixel of interest A and its surrounding pixels B to I, and adding the results, A processing value for the pixel of interest A is determined.

Now, image data to be processed is input directly to such a circuit for spatial filtering from a scanner or the like, or indirectly via a storage device. However, in any case, image data has conventionally been input serially to a spatial filtering circuit.

Conventionally, a circuit that performs spatial filtering with a kernel size of 3 x 3, for example, has a line buffer configured as a shift register for three lines, and on the line buffer,
A configuration in which serially inputted image data is sequentially shifted, data for a total of 9 pixels (the pixel of interest and surrounding pixels) is extracted, inputted to a constant multiplier for weighting, and the result is inputted to an adder and added. It has become. However, there is a problem in that a large capacity line buffer is required and one circuit becomes large in scale.

〔the purpose〕

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a novel storage device that is suitable as an image data input means for a circuit for spatial filtering of images and can contribute to the simplification of such a circuit. .

〔composition〕

To achieve this objective, the storage device according to the invention comprises:
A memory cell array consisting of a plurality of memory cells, a row address decoder that responds to row address information and sequentially selects m consecutive rows of the memory cell array corresponding to the address information one by one, and a row address decoder that responds to column address information. and a column address decoder that sequentially selects n consecutive columns of the memory cells corresponding to the column address information one column at a time, and the total amount of the selected rows and columns is x n memory cells. The configuration is such that data is read out.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram showing a simplified configuration of an embodiment of a storage device according to the present invention.

In this figure, 1 is a memory cell array formed by arranging a large number of memory cells (not shown) in a matrix. This memory cell array 1 has a large number of row selection lines 2 and color 11 selection lines 3 for matching and selecting individual memory cells, as well as data output lines 4, data input lines 5, and the like.

Row selection line 2 is selectively driven by a row address decoder, and column selection line 3 is selectively driven by column address decoder 8.

A memory cell connected to the driven row select line and column select line is accessed, and the data stored in the memory cell is read out onto the data output line 4, or.

The data on data input line 5 is written into that memory cell.

A demultiplexer 9 is provided to distribute data input from the data output line 4 to a plurality of (nine in this embodiment) signal lines 10. A counter 11 is used to control the distribution, and is counted up by a clock signal 12. The output signal of this counter 11 is given to the demultiplexer 9 as a control signal.

The output signal of this counter 11 is also input to the 1-row address decoder 6 and the column address decoder 8.

The row address decoder 6 and column address decoder 8 will be explained. When this storage device is in the write mode, the one-row address decoder 6 and the column address decoder 8 operate in the same manner as a general address decoder, and the one-row address decoder 6 and the column address decoder 8 operate in the same way as a general address decoder, and the one-row address decoder 6 and the column address decoder 8 operate in the same way as a general address decoder, and the one-row address decoder 6 and the column address decoder 8 operate in the same way as a general address decoder, and the one-row address decoder 6 and the column address decoder 8 operate in the same way as a general address decoder, and the one-row address decoder 6 and the column address decoder 8 operate in the same way as a general address decoder. The row selection line 2 and column selection line 3 of one row and one column are selected and driven.

On the other hand, in the read mode of this storage device.

Each address decoder 6.8 has a characteristic operation.

Assume that row address information 13 specifying a certain row (i) of the memory cell array 1 and column address information 14 specifying a certain column (j) are each input.

The row address decoder 6 first drives the row selection line 2 of row (i-1). During this driving, the column address decoder 8 sequentially drives the column selection lines 3 of columns (j-1)e (J)v(j+1).

Next, the row address decoder 6 drives the row selection line 2 of row (i), and during this driving, the column address decoder 8 again selects the column (J 1) * (J) t (j+1)
The column selection lines 3 of are sequentially driven.

Next, the row address decoder 6 drives the row selection line 2 of row (i+1), and during this driving, the column address decoder 8 again drives the row selection line 2 of column (j 1).

Column selection lines 3 (j) and (j+1) are sequentially driven.

In this way, in the read mode, the row address information 13
and by column address information 14.

When a certain row (i) and column (j) are specified.

3 out of a large number of memory cells constituting the memory cell array 3
X3 memory cells are accessed in sequence.

The stored data is sequentially read out to the data output line 4. The access order of the 3×3 memory cells is determined by the counter 11.
controlled by the output signal of

The data sequentially read out from the nine memory cells to the data output line 4 in this manner is sequentially distributed to the nine signal lines 10 by the demultiplexer 9. The order of this distribution is controlled by the output signal of the counter 11. That is, the counter 11 synchronizes the data distribution by the demultiplexer 9 and the driving of each selection line 2.about.3 by each address decoder 6.8.

The data serially read out from the nine memory cells in this way is sent to the output buffer 15 via the demultiplexer 9, and output from there in parallel to nine external data output terminals.

18 is an input buffer. Write data input from the outside to the external data input terminal 17 is transferred to the data input line 5 via the cover sofa 18 . # In the write mode, this write data includes each address information 13.
14 is written to one memory cell in the row and column designated by .

The storage device described above is optimal as an image data input means for, for example, a circuit for spatial filtering of images, and the circuit can be significantly simplified compared to the conventional one, and an improvement in processing speed can be expected.

An example of such an application will be explained with reference to FIG.

In this figure, reference numeral 20 denotes the storage device, in which image data to be processed is stored in advance.

30 is a 3×3 kernel size spatial filtering circuit. As shown in Figure 1, this spatial filtering circuit 30 is composed of nine constant multipliers 31 for weighting and an adder 32 for adding the output values, and the conventional line buffer is Each constant multiplier 31 is directly connected to a corresponding one of the nine external data output terminals 10 of the storage bag [20].

Refer back to Figure 3 at the knee. Assume that pixel A is a pixel of interest to be processed, and that data of pixel A of interest is stored in memory cells in row (i) and column (j) of memory cell array 1 (FIG. 1). At the time of processing this pixel of interest A.

Row address information 13 specifying row (i) and column (j)
The column address information 14 specifying the pixel A is input to the memory bag w20 (the mode at this time is naturally the read mode). Then, the memory cell corresponding to the pixel A of interest in the storage device 20 and the surrounding pixels The data of those pixels are sequentially read out from the eight memory cells corresponding to B to ■.
The data are distributed and output to the corresponding external data output terminals 10 (output in parallel).

The data of pixels A to ■ inputted in parallel from the storage device 20 to the spatial filtering circuit 30 in this way is
After being weighted by a constant multiplier 31, an adder 32
The processed value of the pixel of interest A is output from the adder 32.

Therefore, by sequentially updating the 1-row address information 13 and the column address information 14 and sequentially moving the pixel of interest, it is possible to perform spatial filtering of an image similar to the conventional method.

In this way, by using the storage device of the present invention as an image data input means, the spatial filtering circuit can be greatly simplified. Furthermore, simply by addressing the pixel of interest, data of pixels in its vicinity can be input from the storage device to the spatial filtering circuit at the same time, thereby increasing processing speed.

One embodiment of the present invention has been described above.

The present invention is not limited thereto, and may be implemented in various modifications without departing from the spirit thereof.

For example, in the embodiment described above, a demultiplexer was used to parallelize data sequentially read from a plurality of memory cells, but a serial input/parallel output shift register or the like may be used instead. .

Also, without performing such serial/parallel conversion, the data sequentially read from multiple memory cells may be outputted externally as N serial data. Since serial/parallel conversion is possible simply by providing a conversion means externally, the effects described in connection with the spatial filtering circuit are hardly lost.

Furthermore, it goes without saying that the storage device of the present invention can be applied only to uses other than those described above.

〔effect〕

As is clear from the above description, the present invention is suitable as an image data input means for a circuit for spatial filtering of an image, etc., and contributes to the simplification of such a circuit. An excellent storage device can be realized.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram showing a simplified configuration of an embodiment of the storage device according to the present invention, FIG. 2 is a simplified block diagram showing an application example of the storage device, and FIG. 3 is a functional block diagram showing an example of the application of the storage device. FIG. 3 is a pixel array diagram for explanation. 1...Memory cell array, 2...Row selection line, 3
...Column selection line, 4...Data output line. 6... Row address decoder, 8... Column address decoder, 9... Demultiplexer. 11... Counter, 13... Row address information. 14... Column address information, 15... Cover sofa.

Claims (2)

[Claims] (1) A memory cell array consisting of a plurality of memory cells,
a row address decoder that responds to row address information and sequentially selects m consecutive rows of the memory cell array corresponding to the address information, row by row; and a column address decoder that sequentially selects consecutive n columns of the corresponding memory cells one column at a time, and data stored in a total of m×n memory cells in the selected rows and columns is read out. storage device. (2) The data read from the m×n memory cells selected according to the row address information and the column address information is outputted to the outside in parallel. Storage device.