JPH05233679A - Parallel data processor - Google Patents

Abstract

PURPOSE:To decrease input registers to half without varying a throughput of an operation by providing a register for holding a result of addition between each processor element(PE), and inputting input data at every PE by shifting a bit timewise. CONSTITUTION:Plural PEs (101-10N) consisting of a full adder in which one input is connected to an input data register 111, the other input is connected to an input terminal of an arithmetic operation unit(ALU), and a carry output is connected to a carry input through a register 131 of one bit are arranged. Subsequently, between the adjacent PEs, an addition output terminal of the full adder of one PE and an input terminal of the other PE are connected through registers 171-17N of one bit, and input data is inputted successively to the adjacent PEs by each time slot. According to this constitution, the input registers can be decreased to half, but since it becomes a pipeline processing of every bit, the whole throughput is not varied so much, compared with a conventional one.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel data processor, and more particularly to a parallel processor for performing summation addition with high throughput when a bit serial processor is used.

[0002]

2. Description of the Related Art Generally, in the field of image processing, when high-speed processing is performed, a processor (processor array section) is prepared for each pixel of one screen and arithmetic processing of all pixels is performed simultaneously, as shown in FIG. Sometimes. In the figure, 2
0 is an input terminal, 21 is an input interface unit, 22 is a processor array unit, 23 is an output interface unit, 24
Is an output terminal.

Filtering, matrix calculation, etc. are often used as arithmetic operations in such a configuration.
In that case, the summation addition of each processor element (hereinafter referred to as PE) is performed.

Conventionally, such total sum addition has been performed with a configuration as shown in FIG. Here, it is assumed that addition for one row of the processor array of FIG. 3 is performed as total addition. In the figure, 101 to 10N each represent PE, and 111
.About.11N are registers holding the value of each PE that sums up, and 121 to 12N are ALUs (arithmetic operation units), which function as full adders here. Reference numerals 131 to 13N are registers for holding a carry value, 141 to 14N are carry output terminals, and 151 to 15N are carry input terminals. Each P
The data held in E is set to a ₀ a _{1 to} a _n , b ₀ b ₁
... b _n , ..., d ₀ d ₁ ... d _n . Subscript 0 of each value
~ N corresponds to LSB to MSB.

Next, the operation of this circuit will be described. The registers 111 to 11N shift every operation clock, and the data is input to the ALUs 121 to 12N. First data a ₀ in the first round of the _{clock, b 0, c 0, ...} , d 0
Is input to the ALU 121 to 12N of each PE, and is added to the output of the adjacent ALU (the value of the same digit of the addition result).

The inputs of PE 101 are 0 and a ₀ because there is no adjacent PE. The PE 102 adds the addition result of the PE 101 and b ₀ , and the PE 103 adds the addition result of the PE 102 and C ₀ . The same operation is performed in all PEs, and the LSB of the sum addition is output as the output of the ALU of PE 10N.
Is output. At this time, the registers 131 to 13N of each PE
Holds a value corresponding to the digit of the LSB + 1st bit as a carry value.

Next, at the second clock, the data a ₁ , b
₁ , c ₁ , ..., D ₁ are input to the ALU of each PE, and the addition of the output of the adjacent ALU and the carry value held in the registers 131 to 13N is performed. As a result, PE1
As the 0N ALU output, the value of the LSB + 1th bit of the sum addition is output. Registers 131 to 13N of each PE
Holds a value corresponding to the digit of LSB + 2nd bit as a carry value.

The above operation is repeatedly executed, the data a _n , b _n , c _n , ..., D _n are added at the n-th clock, and the addition result of the n-th bit is output from the PE 10N to the register 16. To be done. Register 1 of each PE at this point
The values of the (n + 1) th bits are held in 31 to 13N, and the input register 111 is held at the (n + 1) th and subsequent clocks.
The value from ~ 11N sends 0, and registers 131 ~ 13N
The value of is added in N-1 clock periods. Therefore, the sum addition is completed in n + N-1 clock periods.

[0009]

In the summation addition by the conventional bit serial type parallel processor, the value of each digit can be calculated at a high speed because it can be calculated in one clock period, but the register of each PE can be calculated. You cannot enter a value for the next calculation during the period. Alternatively, it is necessary to have an extra register for the next calculation.

On the other hand, in real-time image processing,
Since the input image data is input without endurance, the previous processing cannot be waited for. Therefore, this method requires the buffer registers 31 to 3N for holding the next calculation data during the calculation period, which has a drawback of increasing the hardware scale.

The object of the present invention is to eliminate these drawbacks.
It is an object of the present invention to provide a parallel data processing device in which the buffer register is halved and the hardware is downsized.

[0012]

The parallel data processor of the present invention has a structure in which one input is connected to an input data register, the other input is connected to an input terminal, and a carry output is a 1-bit register. A plurality of processor elements each of which is composed of a full adder connected to a carry input via the processor are provided, and between adjacent processor elements among these processor elements, an addition output terminal of the full adder of one processor element is provided. ,
It is characterized in that the input terminal of the other processor element is connected via a 1-bit register so that input data is sequentially input to the adjacent processor element in each time slot.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a bit serial type parallel processor according to an embodiment of the present invention for obtaining the sum addition. Blocks having the same functions as those in the conventional example shown in FIG. 4 are indicated by the same symbols. In this embodiment, each PE1 is different from the conventional example.
Registers 171 and 17 for holding output values of 01 to 10N
By adding 2, ..., Register 3 in the conventional example
It is characterized in that 1 to 3 N are unnecessary.

To explain the operation of this embodiment, the contents of the registers of each PE when the number of data is "4" and the number of bits is "6" are shown in FIG. First, at clock 1, input data is input to the register 111 of the PE 101.
Next, at clock 2, the input data is input to the register 112 of the PE 102. A in the ALU121
₀ (LSB) and 0 are added, and the result is held in the register 171. At the same time, the value of the register 171 at clock 2 and b ₀ (LSB) are added in the ALU 122, the result is held in the register 172, and the carry value is held in the register 132.

Next, at clock 4, the input data is input to the register 114 of the PE 104. ALU12
A ₂ (LSB + ₂ bit) and 0 is added in 1, at the same time the result is held in the register 171 ALU
At 122, the value of the register 171 at clock 3 and b ₁ (LSB + 1st bit) are added, the result is held in the register 172, and the carry value is held in the register 132. At the same time, in the ALU 123, the value of the register 172 at clock 3 and c ₀ (LSB) are added,
The result is held in the register 173, and the carry value is held in the register 133. The same operation is repeated for clock 4, clock 5 ...

At clock 5, LS of four data
The addition result of Ba ₀ , b ₀ , c ₀ , d ₀ is output from the ALU 124, the LSB + 1st bit is output at the clock 6, and the addition result is output LSB in sequence. At clock 7, the data in the register 111 is lost, the next input data is input, and the operation returns from clock 1. In the case of this example, since the number of bits is larger than the number of data, the data cannot be input at the clock 5 and the clock 6, so it is necessary to provide a buffer. Is not necessary.

From the above description, the absolute time until the addition result of the input data is obtained is longer than that of the conventional example, but since the pipeline processing is performed for each bit, the overall throughput is the same as that of the conventional example. ..

[0018]

As described above, according to the present invention, when a bit-serial type parallel processor is used to calculate the sum addition, a register for holding the addition result is provided between each PE, and the input data is temporally set for each PE. The bit-shifted input has an effect that the number of input registers can be reduced to half without changing the throughput of the operation as compared with the conventional case where data is input to all PEs simultaneously in terms of time.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a data flow diagram illustrating the operation of the embodiment of FIG.

FIG. 3 is a block diagram illustrating a device configuration of a conventional example.

FIG. 4 is a block diagram in the case of performing summation addition of FIG.

[Explanation of symbols]

 101 to 10N Processor element 111 to 11N Input data register 121 to 12N ALU 131 to 13N Carry hold register 141 to 14N Carry output terminal 151 to 15N Carry input terminal 16 Output data register 171 to 17 (N-1) Addition output Holding register 20 Data input terminal 21 Input interface 22 Processor array 23 Output interface 24 Data output terminal 31 to 3N Second input data register

Claims (1)

[Claims] 1. A processor comprising a full adder having one input connected to an input data register, the other input connected to an input terminal, and a carry output connected to a carry input through a 1-bit register. A plurality of elements are provided, and between the adjacent processor elements among these processor elements, an addition output terminal of the full adder of one processor element,
Bit serial parallel data processing characterized in that input data is sequentially input to adjacent processor elements in each time slot by a configuration in which the input terminal of the other processor element is connected via a 1-bit register. apparatus.