JPH02111084A - Magneto-electric conversion element - Google Patents

Magneto-electric conversion element

Info

Publication number
JPH02111084A
JPH02111084A JP63262809A JP26280988A JPH02111084A JP H02111084 A JPH02111084 A JP H02111084A JP 63262809 A JP63262809 A JP 63262809A JP 26280988 A JP26280988 A JP 26280988A JP H02111084 A JPH02111084 A JP H02111084A
Authority
JP
Japan
Prior art keywords
resin
compound semiconductor
gaas
thin film
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63262809A
Other languages
Japanese (ja)
Other versions
JP2713744B2 (en
Inventor
Ryoichi Mitsui
三井 良一
Akira Kitai
稀代 昌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Chemical Industry Co Ltd
Original Assignee
Asahi Chemical Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Chemical Industry Co Ltd filed Critical Asahi Chemical Industry Co Ltd
Priority to JP63262809A priority Critical patent/JP2713744B2/en
Publication of JPH02111084A publication Critical patent/JPH02111084A/en
Application granted granted Critical
Publication of JP2713744B2 publication Critical patent/JP2713744B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To improve stability and reliability at high temperature by forming a III-V compound semiconductor where a Hole element is formed on a supporter with an organic insulation layer consisting of heat-curing resin whose glass transfer temperature exceeds 230 deg.C on the surface. CONSTITUTION:In a compound semiconductor layer used, a compound semiconductor thin film such as InAs, InSb, and GaAs is formed on a mica film, passivation layers 13 and 16 are further formed on it, the mica film is eliminated from a thin film, and a compound semiconductor thin film 14 of a semiconductor such as InAs, InSb, and GaAs is formed on a substrate 11 such as GaAs, sapphire, and silicon. A heat-curing resin with a glass transfer point of 230 deg.C which is an organic insulation layer 12 is used. Preferably, the minimum viscosity on heat curing should be 1 poise or less. Heat-curing resin should be polyimide resin, imide-modified epoxy resin, etc. It improves stability and reliability at high temperature.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明は磁界を検出して信号を出力する磁電変1^素子
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a magnetoelectric variable element that detects a magnetic field and outputs a signal.

[従来の技術] +!I −V族化合物半導体を用いたホール素子はいく
つかの構造が知られている。例えば、i) GaAs等
のIII −V族化合物半導体単結晶基板上に直接Si
等の元素をイオン注入法で打ち込み、感哄部を形成して
素子化した構造、 GaAs等のIII −V族化合物
単結晶基板またはサファイヤのような単結晶、あるいは
ガラス、セラミックス等の基板上にMBEまたは真空蒸
着によってIII −V族化合物半導体薄膜の感Fli
i部を形成し、その上に電極を形成し、素子化した構造
がある。また、1f)−旦マイカのような平滑な表面上
にIII −V族化合物半導体を碁石して形成した薄膜
をフェライトやアルミナ等の支持体の上に有機絶縁層で
ある接着剤で接着し、表面のマイカを除去した後、素子
化した構造や、上記i)の半導体層をフェライト等の上
にはりつけホール出力を大きく取るようにした構造等が
ある。特にii)の構造は、支持体の材質を適当に選択
することによりすぐれた性能(例えはフェライト等を使
用するとホール出力を大きく取ることができる。)を容
易に発揮できる利点があり、広く用いられている。しか
し、これらホール素子は最近これまて用いられてきた家
庭用電器の範囲を超え、自動車分野をはじめいろいろな
分野で使用されようとしている。これらの新しい分野は
耐熱性が要求される等使用条件が厳しくなってきている
[Conventional technology] +! Several structures of Hall elements using IV group compound semiconductors are known. For example, i) directly deposit Si on a III-V group compound semiconductor single crystal substrate such as GaAs;
A structure in which elements such as the following are implanted by ion implantation to form a sensitive part to form a device, a single crystal substrate of a III-V group compound such as GaAs, a single crystal such as sapphire, or a substrate of glass, ceramics, etc. Sensitivity of III-V compound semiconductor thin films by MBE or vacuum evaporation
There is a structure in which an i part is formed, an electrode is formed on it, and an element is formed. In addition, 1f) - A thin film formed by cross-plating a III-V compound semiconductor on a smooth surface such as mica is adhered to a support such as ferrite or alumina with an adhesive that is an organic insulating layer, There are structures in which the mica on the surface is removed and then turned into elements, and structures in which the semiconductor layer of (i) above is bonded onto a ferrite or the like to increase the hole output. In particular, structure ii) has the advantage of being able to easily exhibit excellent performance (for example, by using ferrite, etc., a large Hall output can be obtained) by appropriately selecting the material of the support, and is widely used. It is being However, these Hall elements have recently gone beyond the scope of home appliances in which they have been used up until now, and are beginning to be used in various fields including the automobile field. In these new fields, the usage conditions are becoming stricter, such as heat resistance being required.

上記ii)の化合物半導体層と支持体とを有機絶縁層で
接着するタイプのホール素子は、高感度等の特徴を有す
るため高温領域での使用も望まれているが、まだ接着剤
の選定や、接着剤の使用方法等、接着剤と化合物半導体
層の総合的配慮が不足しており、通常の温度範囲では問
題がないが、素子か過大に加熱されると、不平衡電圧や
抵抗が大きく変動する現象も見られ、高温時の安定性、
信頼性が十分でない。
The Hall element of the type ii) above, in which the compound semiconductor layer and the support are bonded with an organic insulating layer, has features such as high sensitivity and is desired to be used in high temperature ranges. , there is a lack of comprehensive consideration of the adhesive and the compound semiconductor layer, such as how to use the adhesive, and although there is no problem in the normal temperature range, if the element is heated excessively, the unbalanced voltage and resistance will increase. Fluctuation phenomena were also observed, and stability at high temperatures,
Not reliable enough.

[発明か解決しようとする課題] これまでホール素子の接着に使用され有機絶縁層として
の熱硬化性樹脂接着剤は、樹脂の接着強度2耐湿性、取
扱い性等が重要視され、その化学構造から、ガラス転移
点が150℃〜180 ’C程度の樹脂が広く用いられ
ている。しかし、これらの樹脂ではガラス転移点より2
0〜30℃低い温度から、弾性率が低下し、130℃〜
150℃の温度にさらされると、不平衡電圧変化や抵抗
の変動する現象も見られている。さらに接着剤はガラス
転移点を越えると、熱膨張係数が数倍犬ぎくなるため、
このような高温になると上述した問題が一層大きく現わ
れてくる。従ってガラス転移温度の低い接着剤を使用す
ると、素子の組立(ワイヤーボンディング)時において
素子を加熱するため、キャピラリーによる衝撃加重、あ
るいは超音波による水平方向の大きな振動が加わると、
もろくなっている樹脂表面に大ぎな変位を発生させるこ
とになり、樹脂上部のチップにクラックが発生しやすく
、許容される操作条件の幅が狭くなっており、量産時に
大ぎな問題をなっているのか現状である。
[Problem to be solved by the invention] Until now, thermosetting resin adhesives used to bond Hall elements and as organic insulating layers have focused on the adhesive strength, moisture resistance, and handling properties of the resin, and their chemical structure Therefore, resins having a glass transition point of about 150°C to 180'C are widely used. However, for these resins, the temperature is 2 below the glass transition point.
The elastic modulus decreases from 0 to 30℃ lower temperature, and from 130℃ to
When exposed to temperatures of 150°C, unbalanced voltage changes and resistance fluctuation phenomena have also been observed. Furthermore, when the adhesive exceeds its glass transition point, the coefficient of thermal expansion becomes several times as large.
At such high temperatures, the above-mentioned problems become even more serious. Therefore, if an adhesive with a low glass transition temperature is used, the device will be heated during device assembly (wire bonding), so if impact load from the capillary or large horizontal vibrations due to ultrasonic waves are applied,
This causes a large displacement on the brittle resin surface, which tends to cause cracks in the chip on the top of the resin, and the range of allowable operating conditions is narrowed, which is a major problem during mass production. This is the current situation.

本発明の目的はホール素子が形成された化合物半導体チ
ップを支持体の上に有機絶縁層である接着剤で接着して
いる構造のポール素子において、高温〔1、?における
安定性および信頼性を向上させると共に、工業的に量産
性の極めて犬なるホール素子を提供することにある。
The object of the present invention is to provide a pole element having a structure in which a compound semiconductor chip on which a Hall element is formed is adhered to a support with an adhesive, which is an organic insulating layer, at a high temperature [1, ? It is an object of the present invention to provide an extremely suitable Hall element which can be industrially mass-produced and which improves the stability and reliability of the device.

[課題を解決するための手段] ;t;発明者らは、上記欠点を解消するため鋭意努力し
た結果本発明の到達した。
[Means for Solving the Problems] ;t; The present invention was achieved as a result of the inventors' earnest efforts to eliminate the above-mentioned drawbacks.

すなわち本発明は、表面に有機物絶縁層を有する支持体
上に、ホール素子が形成されたIII −V族化合物半
導体層が形成されており、有機物絶縁層かガラス転移温
度が230℃以上である熱硬化性樹脂であることを特徴
とする。
That is, in the present invention, a III-V group compound semiconductor layer with a Hall element formed thereon is formed on a support having an organic insulating layer on the surface, and the organic insulating layer is heated to a temperature with a glass transition temperature of 230° C. or higher. It is characterized by being a curable resin.

化合物半導体層は、マイカ上にMBE法あるいは蒸着法
等でInAs、InSb、GaAs等の化合物半導体層
1模を形成し、さらにその上にパッシベーション層を形
成し、マイカを取り除いた薄119や、GaAs、サフ
ァイヤ、シリコン等の基板上にInAs 、 InSb
 、GaAs等の化合物半導体をMBE法、LPE法、
CVD法JIOCVD法または蒸着法により薄膜を形成
したもの、さらには、Ga八へ基板上にイオン注入した
ものが用いられる。
The compound semiconductor layer is made by forming a compound semiconductor layer of InAs, InSb, GaAs, etc. on mica by MBE method or vapor deposition method, and then forming a passivation layer on top of it, and then forming a thin layer of 119 or GaAs with mica removed. , InAs, InSb on substrates such as sapphire, silicon, etc.
, compound semiconductors such as GaAs, MBE method, LPE method,
A thin film formed by a CVD method, a JIOCVD method, or an evaporation method, or a film formed by ion implantation of Ga onto a substrate is used.

半ぶ体層を乗せる支持体としては、特に制限はないが、
例えば、Mn4nフエライト、 Ni−Znフェライト
などの磁性酸化物、あるいはパーマロイなどの高透磁率
金属材料、あるいはアルミナ、チッ化アルミニウム、シ
リカ等のセラミックス材料。
There are no particular restrictions on the support on which the hemibody layer is placed, but
For example, magnetic oxides such as Mn4n ferrite and Ni-Zn ferrite, high magnetic permeability metal materials such as permalloy, or ceramic materials such as alumina, aluminum nitride, and silica.

あるいはガラスのようなアモルファス材料、サファイヤ
のような単結晶等が用いられる。
Alternatively, an amorphous material such as glass or a single crystal such as sapphire may be used.

本発明の有機絶縁層である熱硬化性樹脂は、ガラス転移
点が230℃以上のものが用いられるが、さらに好まし
くは熱硬化時の最小粘度が1ボイズ以下のものである。
The thermosetting resin used as the organic insulating layer of the present invention has a glass transition point of 230° C. or higher, and more preferably has a minimum viscosity of 1 void or less during thermosetting.

有機絶縁層の膜淳は特に制限はないか、60μm以下で
あり、好ましくは204zm以下である。熱硬化性樹脂
の構造については特に制限はないが、好ましくは、ポリ
イミド系樹脂。
The thickness of the organic insulating layer is not particularly limited and is 60 μm or less, preferably 204 μm or less. There are no particular restrictions on the structure of the thermosetting resin, but polyimide resin is preferred.

イミド変性エポキシ樹脂、脂理式エポキシ樹脂。Imide-modified epoxy resin, lipophilic epoxy resin.

グリシジルアミン系エポキシ樹脂等がある。パッシベー
ション層としては、外部よりの水分や、へロケン等の浸
入を防ぐ効果のあるものであればよいが、好ましくは、
 Al2O2、SiO,、Si3N4等の無機薄膜が用
いられるが、場合によっては、ポリイミド等の有機ポリ
マーが用いられることもある。
Examples include glycidylamine-based epoxy resins. The passivation layer may be any material as long as it has the effect of preventing moisture from entering from the outside, herroken, etc., but preferably,
Inorganic thin films such as Al2O2, SiO, and Si3N4 are used, but in some cases, organic polymers such as polyimide may be used.

[作 用コ 本発明によれば、化合物半導体チップと化合物半導体が
乗せられている支持体の間の有機物絶縁層である接着樹
脂として、ガラス転移温度が230℃以上で、・さらに
好ましくは熱硬化時の最小粘度か1ボイズ以下の樹脂を
用いることにより、市熱性のある薄い接着層が可能とな
り、耐熱性の要求される高温で使用しても、不平衡電圧
や抵抗値の変化も少ない、安定でかつ高信頼性のホール
素子を製造することができる。さらに、上記特性を有す
る樹脂を用いることにより、ワイヤーボンディング時の
温度を樹脂のガラス転移点以下で操作が可能で工業的に
量産した素子の信頼性も一層高めることかでとる。また
、ポール素子が形成された化合物半導体層か化合物半導
体薄膜である場合、簿Db?の下部にパッシベーション
膜を施すことにより、上記特性を有する樹脂か耐湿性が
劣るものであっても、高温、高温での使用を可能にする
ことがてきる。以下に実施例を示すが、本発明がこれら
実施例に限定されるものではない。
[Function] According to the present invention, the adhesive resin serving as the organic insulating layer between the compound semiconductor chip and the support on which the compound semiconductor is mounted has a glass transition temperature of 230°C or higher, and is preferably thermoset. By using a resin with a minimum viscosity of 1 void or less, it is possible to create a thin adhesive layer that is heat resistant, and even when used at high temperatures where heat resistance is required, unbalanced voltage and resistance changes are small. A stable and highly reliable Hall element can be manufactured. Furthermore, by using a resin having the above-mentioned characteristics, the temperature during wire bonding can be controlled to be below the glass transition point of the resin, thereby further increasing the reliability of industrially mass-produced devices. In addition, when the pole element is formed in a compound semiconductor layer or a compound semiconductor thin film, Db? By applying a passivation film to the lower part of the resin, it is possible to use the resin at high temperatures even if the resin has the above-mentioned characteristics or has poor moisture resistance. Examples are shown below, but the present invention is not limited to these Examples.

[実施例] 以下、図面を参照して本発明の実施例を詳細に説明する
[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

実施例1 第1図に本発明の一実施例の断面を示す。Example 1 FIG. 1 shows a cross section of an embodiment of the present invention.

表面が平滑なマイカ上にM8E蒸着法によりInAsの
薄膜を形成し、半導体11U14を作成した。さらにそ
の上ヘバッシベーション層としてAJ2203(厚さ0
.3 μm)薄膜13を真空蒸着法により形成した。こ
のAJ2203薄n莫表面へガラス転移温度が250℃
であるポリイミド樹脂12(東芝ケミカルCT430)
を塗イbし、厚さ0.3mm、 1辺が50.8mmの
正方形をしたフェライト基板11に接着し、ついで前記
のマイカを除去した。その後、フォトレジストを使用し
、通常行われている方法により電極15を形成し、感磁
部のパターンを形成した。その梼、感磁部を保護するパ
ッシベーション層16としてAn203(厚さ03μm
)薄膜を真空蒸着法により形成し、さらにシリコン樹脂
を塗布し、フェライトチップ42を乗仕ホール素子ウェ
ハを作成した。次にこのウェハをグイシングカッターで
切断してチップを作成した。チップをリードフレーム2
2上にダイボンド樹脂50て接着し、ベレットの電磁部
15とリードフレーム22をワイヤーボンディングによ
り接合した。ついて樹脂23によりモールドを行いホー
ル素子を作成した。このホール素子の半田耐熱テスト前
後の不平衡電圧Vuの変化(平均)および偏差を第1表
に示す。ここでいう半田耐熱テストとは、素子4端子を
各温度の半固相に10秒間浸漬した前後における特性の
変動を見るものである。また、半田耐熱テスト時の素子
の不良率を第2表に示す。
A thin film of InAs was formed on mica having a smooth surface by the M8E vapor deposition method to produce a semiconductor 11U14. Furthermore, AJ2203 (thickness 0
.. 3 μm) thin film 13 was formed by vacuum evaporation. The glass transition temperature of this AJ2203 thin n-surface is 250℃.
Polyimide resin 12 (Toshiba Chemical CT430)
It was coated with a ferrite substrate 11 having a thickness of 0.3 mm and a square shape of 50.8 mm on each side, and then the mica was removed. Thereafter, an electrode 15 was formed using a photoresist by a commonly used method, and a pattern of a magnetically sensitive part was formed. The passivation layer 16 that protects the magnetically sensitive part is made of An203 (thickness: 03 μm).
) A thin film was formed by a vacuum evaporation method, silicone resin was further applied, and a ferrite chip 42 was mounted on it to create a Hall element wafer. Next, this wafer was cut with a guissing cutter to create chips. Chip lead frame 2
The electromagnetic part 15 of the pellet and the lead frame 22 were bonded by wire bonding. Then, molding was performed using resin 23 to create a Hall element. Table 1 shows the change (average) and deviation in the unbalanced voltage Vu before and after the solder heat resistance test of this Hall element. The solder heat resistance test herein refers to changes in characteristics before and after immersing four terminals of an element in a semi-solid phase at various temperatures for 10 seconds. Furthermore, Table 2 shows the failure rate of the elements during the solder heat resistance test.

第1表 手口]耐熱テスト(不平衡電圧変化) 単位mV73V [νυ変化(平均1士偏差] 第2表 素子不良率 不良率とは1Vu(初期値−ラス)・後)1≧5 、’
OmVの割合比較例1 実施例1における接着樹脂12をポリイミド系樹脂(東
芝ケミカルTVB2703A ニガラス転移温度172
℃)に変更し、それ以外は実施例1と同様にして素子を
作成した。耐熱テスト結果を第1.第2表に示す。
Table 1 Technique] Heat resistance test (unbalanced voltage change) Unit mV73V [νυ change (average 1-dimensional deviation) Table 2 Element defective rate Defective rate is 1Vu (initial value - ras)・after) 1≧5,'
OmV ratio comparative example 1 Adhesive resin 12 in Example 1 was replaced with polyimide resin (Toshiba Chemical TVB2703A glass transition temperature 172
℃), and otherwise produced a device in the same manner as in Example 1. The heat resistance test results are the first. Shown in Table 2.

第1表および第2表に示すように、本発明による素子は
、耐熱テスト後の不平衡電圧変化および不良率がいずれ
も小さい。
As shown in Tables 1 and 2, the device according to the present invention has a small unbalanced voltage change and a small defective rate after the heat resistance test.

実施例2 実施例1におけるフェライト基板をアルミナ基板へ変更
し、さらに、フェライトチップ42を乗せない以外は実
施例1と同様な方法でホール素子を作成した。このホー
ル素子の半田耐熱テストの前後の不平衡電圧の変化およ
び偏差を第3表に示す。
Example 2 A Hall element was produced in the same manner as in Example 1 except that the ferrite substrate in Example 1 was replaced with an alumina substrate and the ferrite chip 42 was not mounted. Table 3 shows the changes and deviations in unbalanced voltage before and after the solder heat resistance test of this Hall element.

比較例2 実施例2と同様な作成方法で比較例1と同一の接着樹脂
を用い素子を作成した。耐熱テストの結果を第3表に示
す。
Comparative Example 2 An element was manufactured in the same manner as in Example 2 using the same adhesive resin as in Comparative Example 1. The results of the heat resistance test are shown in Table 3.

第 3 表  半田耐熱テスト 単位mV/:IV 実施例3 実施例1におけるパッシベーション層としてアルミナを
SiOx (厚さ0.5 μm)に変更する以外は実施
例1と同様な方法により素子を作成した。このホール素
子の半田耐熱テストの結果を第4表に、素子不良率を第
5表に示す。
Table 3 Solder Heat Resistance Test Unit mV/:IV Example 3 A device was produced in the same manner as in Example 1 except that the passivation layer in Example 1 was replaced with SiOx (thickness: 0.5 μm). Table 4 shows the results of the solder heat resistance test for this Hall element, and Table 5 shows the element failure rate.

比較例3〜5 実施例3と同様な作成方法でガラス転移点の異なる接着
樹脂を用い素子を作成した。このホール素子の半田耐熱
テスト結果を第4表に、素子不良率を第5表に示す。
Comparative Examples 3 to 5 Elements were fabricated using the same fabrication method as in Example 3 using adhesive resins having different glass transition points. Table 4 shows the solder heat resistance test results of this Hall element, and Table 5 shows the element failure rate.

ガラス転移点  樹 脂 名 第4表 半田耐熱テスト 単位mV/3V 第5表 素子不良率 ΔVul≧5mVのものを不良とした。Glass transition point Resin name Table 4 Solder heat resistance test Unit mV/3V Table 5 Element defect rate Those with ΔVul≧5mV were judged as defective.

第3表〜第5表に示すように、本発明素子は磁気北東用
フェライトを用いない場合でも、またバッシヘーション
膜の種類によらず、比較例よりすぐれた耐熱性を示す。
As shown in Tables 3 to 5, the device of the present invention exhibits superior heat resistance to the comparative example even when no magnetic northeast ferrite is used and regardless of the type of bashing film.

実施例4 表面が鏡面であるG a A s−n/L結晶基板上(
−辺が50.8mmの正方形)に、厚さ1μm、電子啓
動度10.000cm2/Vsecの[nAs薄膜をM
BE法によりヘテロエピタキシャル成長させて、半導体
it摸を作った。次に、GaAs基板面にガラス転移温
度が250℃であるポリイミド樹脂を塗布し、厚さ0.
3mm、−辺が50.8mmの正方形をしたフェライト
基板に接着した。これ以降は実施例2と同様な作成方法
によりTnAsホール素子を作成した。このホール素子
の半田耐熱テストの結果300℃において不平衡電圧の
差(平均)士偏差は0.51+ 0.43mV/3Vで
あった。
Example 4 On a GaAsn/L crystal substrate with a mirror surface (
- A [nAs thin film with a thickness of 1 μm and an electron excitation of 10.000 cm2/Vsec] was
A semiconductor IT model was fabricated by heteroepitaxial growth using the BE method. Next, a polyimide resin having a glass transition temperature of 250°C is applied to the surface of the GaAs substrate to a thickness of 0.
It was adhered to a square ferrite substrate with a diameter of 3 mm and a side of 50.8 mm. From this point on, a TnAs Hall element was fabricated using the same fabrication method as in Example 2. As a result of a solder heat resistance test of this Hall element, the difference (average) deviation in unbalanced voltage at 300° C. was 0.51+0.43 mV/3V.

実施例5 実施例1でマイカ上に形成させる半導体膜をInSbに
変更し、それ以降は実施例1と同様な作成方法により、
InSbホール素子を作成した。この素子を用いた半田
耐熱テストの結果は、3[10℃において不平衡電圧変
化(平均)士偏差は0.91±0.48mV/3Vであ
った。
Example 5 The semiconductor film to be formed on mica in Example 1 was changed to InSb, and from then on, the same manufacturing method as in Example 1 was used.
An InSb Hall element was created. The result of a solder heat resistance test using this element was that the unbalanced voltage change (average) deviation was 0.91±0.48 mV/3V at 10°C.

実施例6 実施例1におけるパッシベーション層16としてSi3
N4を厚さ0.5 p mPCVD法により形成し、そ
れ以外は実施例1と同様な作成方法によりInAsホー
ル素子を作成した。この素子を用いた半田耐熱テストの
結果は、300℃において不平衡電圧変化(平均)士偏
差は0.60±0.25mV/3Vであった。
Example 6 Si3 as the passivation layer 16 in Example 1
An InAs Hall element was fabricated using the same fabrication method as in Example 1 except that N4 was formed to a thickness of 0.5 pm by the PCVD method. As a result of a soldering heat resistance test using this element, the unbalanced voltage change (average) deviation was 0.60±0.25 mV/3V at 300°C.

実71λ例7 実施例1におけるパッシベーション層1δとしてAj2
203 (0,3μm)およびSin□(0,3μm)
薄膜を真空蒸着法により形成し、それ以外は実施例1と
同様な作成方法でInAsホール素子を作成した。この
素子を用いて高温通電テスト(150℃、20mA、 
500時間)を行った。結果を第6表に示す。
Actual 71λ Example 7 Aj2 as passivation layer 1δ in Example 1
203 (0,3μm) and Sin□ (0,3μm)
An InAs Hall element was fabricated using the same fabrication method as in Example 1 except that a thin film was formed by vacuum evaporation. Using this element, we conducted a high-temperature current test (150°C, 20mA,
500 hours). The results are shown in Table 6.

比較例6 実施例7における接着樹脂をポリイミド系樹脂(東芝ケ
ミカル、 TVn2703八、硬化剤ペルキュアHV1
06.ガラス転移温度172℃)に変更し、それ以外は
実施例7と同様にして素子を作成した。この素子を用い
て高温通電テストを行った。結果を第6表に示す。
Comparative Example 6 The adhesive resin in Example 7 was replaced with polyimide resin (Toshiba Chemical, TVn27038, curing agent Percure HV1).
06. A device was produced in the same manner as in Example 7 except that the glass transition temperature was changed to 172° C.). A high temperature energization test was conducted using this element. The results are shown in Table 6.

第6表 高温通電テスト ΔRjn   テスト前後の入力抵抗の変化率上偏差Δ
Rout   テスト前後の出力抵抗の変化率上偏差Δ
Vul  テスト前後の不平衡電圧の変化率の絶対値上
偏差実施例8 一辺が50.8mmの正方形で表面が鏡面であるGaA
s単結晶基板にイオン注入法によりStイオンを打ち込
んだ半導体層を形成した。次にGaAs基板裏面にガラ
ス転移温度が250℃のポリイミド樹脂を塗布し、厚さ
0.3mm、−辺が5(1,8mmの正方形をしたフェ
ライト基板に接着した。これ以降は実施例2と同様な作
成方法によりGaAsホール素子を作成した。
Table 6 High temperature energization test ΔRjn Deviation Δ in rate of change of input resistance before and after test
Rout Deviation Δ in rate of change of output resistance before and after test
Deviation in absolute value of rate of change of unbalanced voltage before and after Vul test Example 8 GaA with a square with one side of 50.8 mm and a mirror surface
A semiconductor layer was formed by implanting St ions into an S single crystal substrate by an ion implantation method. Next, a polyimide resin with a glass transition temperature of 250°C was applied to the back surface of the GaAs substrate, and it was adhered to a square ferrite substrate with a thickness of 0.3 mm and a side of 5 (1.8 mm). A GaAs Hall element was fabricated using a similar fabrication method.

このホール素子の半田耐熱テストの結果は300℃jこ
おいて不平ゆj電圧の差(平均)士偏差は0.45±0
.41m1//:IVであった。
The result of the solder heat resistance test of this Hall element is that the difference (average) in voltage at 300℃ is 0.45±0.
.. It was 41m1//:IV.

[発明の効果] 以上説明したように、本発明によれば、化合物半導体の
秤類、パッシベーション膜の種類および基板の種類によ
らず、さらに磁気集束用フェライトチップの有無によら
ず、すぐれた耐熱性を示し、高温における使用が可能で
ある。
[Effects of the Invention] As explained above, according to the present invention, excellent heat resistance can be achieved regardless of the type of compound semiconductor scale, the type of passivation film, the type of substrate, and regardless of the presence or absence of a ferrite chip for magnetic focusing. It can be used at high temperatures.

15・・・電極、 16・・・上部パッシベーション層、 22・・・リードフレーム、 23・・・モールド樹脂、 =+1・・・シリコン樹脂(接若剤)、・12・・・フ
ェライトチッフ、 50・・・タイボンド接着樹脂層。
15... Electrode, 16... Upper passivation layer, 22... Lead frame, 23... Mold resin, =+1... Silicone resin (adulent), 12... Ferrite chip, 50...Tie bond adhesive resin layer.

【図面の簡単な説明】[Brief explanation of the drawing]

’f、1図は本発明の一実施例の断面図である。 11・・・基板、 12・・・有機絶縁層(接看剤)、 13・・・下部パッシベーション層、 14・・・半導体装置 1 is a sectional view of an embodiment of the present invention. 11... board, 12...Organic insulating layer (contact agent), 13... lower passivation layer, 14...Semiconductor device

Claims (1)

【特許請求の範囲】[Claims] (1)表面に有機物絶縁層を有する支持体上に、ホール
素子が形成されたIII−V族化合物半導体層が形成され
ており、前記有機物絶縁層がガラス転移温度が230℃
以上である熱硬化性樹脂であることを特徴とする磁電変
換素子。
(1) A III-V compound semiconductor layer on which a Hall element is formed is formed on a support having an organic insulating layer on the surface, and the organic insulating layer has a glass transition temperature of 230°C.
A magnetoelectric conversion element characterized by being made of the above thermosetting resin.
JP63262809A 1988-10-20 1988-10-20 Magnetoelectric conversion element Expired - Lifetime JP2713744B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63262809A JP2713744B2 (en) 1988-10-20 1988-10-20 Magnetoelectric conversion element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63262809A JP2713744B2 (en) 1988-10-20 1988-10-20 Magnetoelectric conversion element

Publications (2)

Publication Number Publication Date
JPH02111084A true JPH02111084A (en) 1990-04-24
JP2713744B2 JP2713744B2 (en) 1998-02-16

Family

ID=17380911

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2713744B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011009756A (en) * 2010-07-12 2011-01-13 Asahi Kasei Electronics Co Ltd Method of manufacturing magnetoelectric converting element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011009756A (en) * 2010-07-12 2011-01-13 Asahi Kasei Electronics Co Ltd Method of manufacturing magnetoelectric converting element

Also Published As

Publication number Publication date
JP2713744B2 (en) 1998-02-16

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