JPH02110944U - - Google Patents
Info
- Publication number
- JPH02110944U JPH02110944U JP1770489U JP1770489U JPH02110944U JP H02110944 U JPH02110944 U JP H02110944U JP 1770489 U JP1770489 U JP 1770489U JP 1770489 U JP1770489 U JP 1770489U JP H02110944 U JPH02110944 U JP H02110944U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power source
- high voltage
- impedance
- dividing resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001934 delay Effects 0.000 claims 1
- 230000001629 suppression Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Description
第１図は本考案の一実施例の回路図、第２図は
第１図の回路の出力端子の電圧波形及び装置入力
電流波形図、第３図は従来の回路図、第４図は第
３図の回路の出力端子の電圧波形及び装置入力電
流波形図である。
１……直流高圧電源、２〜７……分圧用抵抗、
８，９……高電圧出力端子、１０……切替スイツ
チ、１１……トランジスタ、１２……ソフトバイ
アス回路、１３……開閉スイツチ。
Fig. 1 is a circuit diagram of one embodiment of the present invention, Fig. 2 is a diagram of the voltage waveform of the output terminal of the circuit of Fig. 1 and the device input current waveform, Fig. 3 is a conventional circuit diagram, and Fig. 4 is a diagram of the device input current waveform. 4 is a voltage waveform of the output terminal of the circuit of FIG. 3 and a diagram of the device input current waveform. FIG. 1...DC high voltage power supply, 2 to 7...Voltage dividing resistor,
8, 9... High voltage output terminal, 10... Selector switch, 11... Transistor, 12... Soft bias circuit, 13... Open/close switch.
Claims (1)
高圧電源を分圧して出力電圧を得る回路において
、前記分圧抵抗の一部に該分圧抵抗のインピーダ
ンスを低下させる素子を接続し、かつこの素子の
インピーダンス低下動作を遅延させる回路を接続
したことを特徴とする突入電流抑制回路。 In a circuit that includes a plurality of resistors that divide a high voltage power source and obtains an output voltage by dividing the high voltage power source, an element that lowers the impedance of the voltage dividing resistor is connected to a part of the voltage dividing resistor; An inrush current suppression circuit characterized by connecting a circuit that delays the impedance lowering operation of an element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1770489U JPH02110944U (en) | 1989-02-17 | 1989-02-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1770489U JPH02110944U (en) | 1989-02-17 | 1989-02-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02110944U true JPH02110944U (en) | 1990-09-05 |
Family
ID=31231724
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1770489U Pending JPH02110944U (en) | 1989-02-17 | 1989-02-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02110944U (en) |
-
1989
- 1989-02-17 JP JP1770489U patent/JPH02110944U/ja active Pending
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