JPH02110722A - Oscillation control system - Google Patents

Oscillation control system

Info

Publication number
JPH02110722A
JPH02110722A JP63265398A JP26539888A JPH02110722A JP H02110722 A JPH02110722 A JP H02110722A JP 63265398 A JP63265398 A JP 63265398A JP 26539888 A JP26539888 A JP 26539888A JP H02110722 A JPH02110722 A JP H02110722A
Authority
JP
Japan
Prior art keywords
voltage
oscillation
system reset
circuit
oscillation circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63265398A
Other languages
Japanese (ja)
Inventor
Norihiko Iida
飯田 則彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63265398A priority Critical patent/JPH02110722A/en
Publication of JPH02110722A publication Critical patent/JPH02110722A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To advance an oscillation starting time by applying a system reset except an oscillation circuit by the deciding result of a power source voltage deciding circuit. CONSTITUTION:When a power source voltage 11 rises, a system reset signal is generated until it reaches a voltage value set beforehand by a voltage detecting circuit built in a system reset generating circuit 3, and after that, when the voltage rises above it, the system reset is canceled and a controller starts a normal operation. Here, the reset is not inputted to the oscillation circuit and therefore, it starts to oscillate the the voltage lower than a voltage detection level. Thus, the oscillation starting time when the power source rises can be advanced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は発振制御方式に関し、特に電源立ち上げ時の制
御方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an oscillation control method, and particularly to a control method at power-on.

〔従来の技術〕[Conventional technology]

従来、データ処理を実行するコントローラ等のLSI(
大規模集積回路)では、電源投入時に一時的にシステム
リセット信号を発生させている。
Conventionally, LSIs such as controllers that execute data processing (
(large-scale integrated circuits), a system reset signal is temporarily generated when the power is turned on.

システムリセット発生回路はLSIに内蔵することも可
能で内蔵化が進んでいる。
A system reset generation circuit can also be built into an LSI, and this is becoming more and more common.

ところで、システムリセット発生回路は電圧が低下して
もリセットがでるものが一般的である。
By the way, system reset generation circuits are generally capable of generating a reset even when the voltage drops.

なぜなら、まず電源立ち上げ時にある電圧を検出しその
電圧以上でリセットが解除されるようになっている場合
に逆に電圧が下がった場合でもその電圧を判定すること
ができる為である。
This is because, if a certain voltage is first detected when the power is turned on and the reset is canceled when the voltage exceeds that voltage, the voltage can be determined even if the voltage drops.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところで、マイクロコントローラ等の基本周波数源とし
ては水晶発振回路が使用されるが電源立ち上げ時の発振
開始時間はできるだけ早い方が望ましい。ところが発振
回路もシステムリセットされるようになっており電源立
ち上げ時の発振開始が遅れる要因になっていると共に電
源が一時的に下がった場合発振回路にリセットがかかっ
てしまうと再発振に時間を要するという欠点がある。
Incidentally, although a crystal oscillation circuit is used as a basic frequency source for a microcontroller or the like, it is desirable that the oscillation start time when the power is turned on be as early as possible. However, the oscillation circuit is also reset by the system, which causes a delay in the start of oscillation when the power is turned on.If the oscillation circuit is reset when the power is temporarily turned off, it takes time to re-oscillate. There is a drawback that it requires

〔課題を解決するための手段〕[Means to solve the problem]

本発明は発振制御方式は少なくとも発振回路と電源電圧
判定回路を備えたシステムに於いて該判定結果により発
振回路を除いた部分にシステムリ1’)7− セットをかけるようにしている。
In the oscillation control method of the present invention, in a system equipped with at least an oscillation circuit and a power supply voltage determination circuit, a system reset is applied to the parts other than the oscillation circuit based on the determination result.

すなわち、本発明では発振回路にはリセットをかげない
ようにしている。
That is, in the present invention, the oscillation circuit is not reset.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の第1の実施例であり、図中1は発振回
路、2はコントローラ、3はシステムリセット発生回路
である。第2図は本発明を説明する為のタイムチャート
であり、1oは電源電圧、11はGND、12は電圧検
出レベル、13はシステムリセット信号を又22は本発
明の発振開始波形を表わす。
FIG. 1 shows a first embodiment of the present invention, in which 1 is an oscillation circuit, 2 is a controller, and 3 is a system reset generation circuit. FIG. 2 is a time chart for explaining the present invention, in which 1o represents the power supply voltage, 11 represents the GND, 12 represents the voltage detection level, 13 represents the system reset signal, and 22 represents the oscillation start waveform of the present invention.

第2図に於いて電源電圧11が立ち上がるとシステムリ
セット発生回路3に内蔵された電圧検出回路により予め
設定された電圧値になるまでシステムリセット信号が発
生される。この後それ以上電圧が上がればシステムリセ
ットは解除されコントローラ2は正常動作に入る。本発
明の発振制御方式では発振回路にはリセットを入れてい
ない為電圧検出レベルより低い電圧で発振を開始する。
In FIG. 2, when the power supply voltage 11 rises, a system reset signal is generated by the voltage detection circuit built in the system reset generation circuit 3 until the voltage reaches a preset voltage value. If the voltage increases further after this, the system reset is canceled and the controller 2 enters normal operation. In the oscillation control method of the present invention, since the oscillation circuit is not reset, oscillation is started at a voltage lower than the voltage detection level.

又正常動作時に期間T電圧が低下した場合、その電圧値
が発振可能電圧であればシステムリセットに関係なく発
振を継続し電源電圧復帰時の動作の正常化がスムーズに
行なわれる。水晶発振回路では一般に発振開始電圧より
発振停止電圧の方が低い為、発振回路がリセットされな
いことは発振継続上有効である。一方、従来は、21で
示すように、期間Tで発振が停止し、このため、復帰に
時間がかかる。
Furthermore, when the period T voltage decreases during normal operation, if the voltage value is a voltage that allows oscillation, oscillation continues regardless of system reset, and normalization of operation is performed smoothly when the power supply voltage is restored. In a crystal oscillation circuit, the oscillation stop voltage is generally lower than the oscillation start voltage, so not resetting the oscillation circuit is effective for continuing oscillation. On the other hand, conventionally, as shown at 21, oscillation stops during period T, and therefore it takes time to recover.

第3図は本発明の第2の実施例を示すブ四ツクダイアダ
ラムである。図中、■は発振回路、2はコントローラ、
3はシステムリセット発振回路、31は第1のシステム
リセット信号、32は第2のシステムリセット信号を表
わす。31のシステムリセット信号は第1の実施例で述
べた機能と同一であるが、電源電圧がさらに低下すると
第2のシステムリセット信号32が発生され発振回路1
を含めてリセットをかげるようにしている。発振回路に
セルフバイアスがかかっているような場合スタンバイ電
流をおさえる為に必要である。又発振回路1へのリセッ
トはコントローラ2から発効される命令によって行なっ
ても差し支えない。
FIG. 3 is a block diagram showing a second embodiment of the present invention. In the figure, ■ is an oscillation circuit, 2 is a controller,
3 represents a system reset oscillation circuit, 31 represents a first system reset signal, and 32 represents a second system reset signal. The system reset signal 31 has the same function as described in the first embodiment, but when the power supply voltage further decreases, a second system reset signal 32 is generated and the oscillation circuit 1
I am trying to hide the reset by including this. This is necessary to suppress standby current when the oscillation circuit is self-biased. Further, the oscillation circuit 1 may be reset by a command issued from the controller 2.

〔発明の効果〕〔Effect of the invention〕

以上詳述したように本発明は少なくとも発振回路と電源
電圧判定回路を備えたシステムに於いて、この判定結果
により発振回路を除いてシステムリセットをかけること
により発振開始時間を早くすると共に電圧の低下に対し
ても安定した発振を継続させることができる効果がある
As described in detail above, in a system equipped with at least an oscillation circuit and a power supply voltage determination circuit, the present invention can speed up the oscillation start time and reduce the voltage drop by resetting the system excluding the oscillation circuit based on the determination result. This has the effect of allowing stable oscillation to continue even for

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例図、第2図その動作を説明す
る為のタイムチャート、第3図は第2の実施例図である
。図中1は発振回路、2はコントローラ、3はシステム
リセット発生回路を示す。 代理人 弁理士  内 原   晋 一
FIG. 1 is a diagram showing one embodiment of the present invention, FIG. 2 is a time chart for explaining its operation, and FIG. 3 is a diagram of a second embodiment. In the figure, 1 is an oscillation circuit, 2 is a controller, and 3 is a system reset generation circuit. Agent Patent Attorney Shinichi Uchihara

Claims (1)

【特許請求の範囲】[Claims] 少なくとも発振回路と電源電圧判定回路とを備え、誤判
定回路からの判定結果により発振回路を除いた部分にシ
ステムリセットをかけるようにしたことを特徴とする発
振制御方式。
An oscillation control method comprising at least an oscillation circuit and a power supply voltage determination circuit, and a system reset is applied to a portion other than the oscillation circuit based on a determination result from an erroneous determination circuit.
JP63265398A 1988-10-20 1988-10-20 Oscillation control system Pending JPH02110722A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63265398A JPH02110722A (en) 1988-10-20 1988-10-20 Oscillation control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63265398A JPH02110722A (en) 1988-10-20 1988-10-20 Oscillation control system

Publications (1)

Publication Number Publication Date
JPH02110722A true JPH02110722A (en) 1990-04-23

Family

ID=17416616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63265398A Pending JPH02110722A (en) 1988-10-20 1988-10-20 Oscillation control system

Country Status (1)

Country Link
JP (1) JPH02110722A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62174836A (en) * 1986-01-28 1987-07-31 Fujitsu Ten Ltd Malfunction preventing method for microcomputer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62174836A (en) * 1986-01-28 1987-07-31 Fujitsu Ten Ltd Malfunction preventing method for microcomputer

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