JPH02110650A - Interruption control system - Google Patents

Abstract

PURPOSE:To change the priorities of respective interruption signals by preparing plural types of pattern coding tables for a priority encoder and selecting a coding table by a pattern selecting signal. CONSTITUTION:When a transmission/reception completion interruption INT occurs, an interruption signal 11a is inputted through an interruption register 11 to the low-order address of a priority encoder 12, and simultaneously, a pattern selecting signal 10a, which is stored through an internal bus 4 into a pattern register 10 by a host processor, is inputted to the priority encoder 12. Thus, interruption codes are respectively outputted as outputs D1, D2, and D3 of the priority encoder 12 and stored in a buffer 13, a storage instruction STRE is outputted to the buffer 13 by a line interruption D0 to be inputted to the host device simultaneously with the interruption codes D1, D2, and D3, the interruption codes are read, and, for example, when a three-bit signal is assigned to the pattern selecting signal 10a, the priorities of either patterns can be changed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an interrupt control method used in a line control unit or the like in a communication control device.

(Prior Art) A communication control device is required to accept and appropriately process a large number of interrupt signals input from a line or from various circuits connected to the line.

FIG. 2 shows a block diagram of a line control section of such a conventional communication control device.

In the figure, line 1 is driver receiver CD/R) 2
It is connected to the communication control LSI 3 through. Further, a line interrupt circuit 5 and a timer 6 are connected to the communication control LSI 3 via an internal bus 4. The communication control LSI 3 controls signals input from or output to the driver receiver 2. This is a well-known integrated circuit for communication control. Further, the timer 6 is a circuit that counts a certain amount of time when executing a well-known communication protocol.

Interrupt signals 3a and 6a are input from the communication control LSI 3 and the timer 6 to the line interrupt circuit 5. The line interrupt circuit 5 receives these interrupt signals 3.
A, 6a, or other interrupt signal is accepted and the line interrupt 5 is sent to the upper processor connected to this communication control device.
This circuit is configured to output an interrupt code indicating an interrupt signal (interrupt destination) to the internal bus 4.

FIG. 3 shows a block diagram of such a conventional line interrupt circuit.

This circuit includes a register 51, a priority encoder 52, a buffer 53, and an OR gate 54.

The register 51 is a circuit that accepts several types of interrupt signals and stores them at - time, and operates to store the interrupt signals at the timing when the sample clock CL is input. This register contains the transmission/reception completion interrupt INT,
A receive data read request IN TF, a transmit data write request 011T TF, a modem signal interrupt MDM, and a timer interrupt TM are input. These are all 1-bit digital signals, and after being stored in the register 51,
The signal is wired to become a 5-bit parallel interrupt signal 51a and input to the priority encoder 52 and the OR gate 54.

The OR gate 54 is a circuit that takes the logical sum of the interrupt signals 51a and outputs the result as a line interrupt 5a. The priority encoder 52 is a circuit that collectively encodes the 5-bit parallel interrupt signals 51a into a 3-bit interrupt code 52a, and is a memory circuit that has an internal encoding table for conversion.

Note that this interrupt code 52a displays which one of the 5-bit input signals will be allowed to interrupt first, based on the priority set in advance for each interrupt signal. It is set to do so.

The interrupt code 52a output from the priority encoder 52 is temporarily stored in the buffer 53. This storage instruction is performed by storage instruction signal 5TRE. When the interrupt code 52a is stored in the buffer 53, its signal is taken into the internal bus 4 and read by a host processor (not shown).

The above device specifically operates as follows.

For example, when a message is received from the line l shown in FIG.
A TF interrupt occurs. When this is sampled in the register 51, a line interrupt 5a is outputted to the upper processor through the OR gate 54. As is clear from the circuit shown in FIG. 3, this line interrupt 5a is a signal that is always output when any interrupt occurs.

Meanwhile, at the same time, the interrupt signal 51a is input to the priority encoder 52 and encoded into an interrupt code 52a. When the host processor accepts the line interrupt 5a from the OR gate 54, it outputs a storage instruction 5TRE to the buffer 53, stores the interrupt code 52a in the buffer 53, and reads it through the internal bus 4. When the interrupt processing is completed, the received data read request IN TF is cleared and the line interrupt 5a disappears.

Further, for example, when two interrupts occur, the line interrupt 5a is output, and the priority encoder 52
generates an interrupt code 52a that displays one of the interrupt signals, and outputs it to the buffer 53 so that only the interrupt with a high priority is processed.

That is, the higher-level processor that reads this via the buffer 53 performs interrupt processing for the interrupt destination. As a result, the highest priority interrupt signal is cleared, and the remaining low priority interrupt is inputted to the register 51 again, so that the line interrupt 5a occurs again. Next, for that low priority interrupt, priority encoder 5
2 generates an interrupt code 52a, and interrupt processing for it is executed.

In this way, in the conventional device, when two or more interrupts occur simultaneously, the priority encoder 52
It automatically accepts only high-priority interrupt requests using a coding table prepared therein, and outputs an interrupt code 52a. In this way, the interrupt signals were processed in the proper order.

(Problem to be Solved by the Invention) By the way, in the above system, a table for other codes is prepared inside the priority encoder 52, and this is used to generate an interrupt code. If there is a conflict, the priority will be uniquely determined in a preset order.

Therefore, if there is a request to change the priority,
The problem was that the hardware itself had to be changed.

For example, when a low-speed line is supported by this communication control device, the received data read request IN from the communication control LSI
When there is a TF or transmit data write request 01lT TF, the interrupt interval is long, and there is relatively little problem even if the interrupt processing is made to wait. Therefore, the transmission/reception completion interrupt IN
It is common practice to give high priority to T and modem signal interrupts MDM to perform efficient interrupt processing.

However, if such a device is configured to support a high-speed line as is, the interrupt interval for received data read request IN TF and transmitted data write request OUT TF will be short in proportion to the communication speed. Become. That is, for example, if the communication speed doubles, the interrupt interval will be halved.

However, if the device remains the same as before, there is a high possibility that the interrupt processing will have to wait because received data read requests and the like have a lower priority than transmission/reception completion interrupts and the like. If such an interrupt is made to wait for a certain period of time, an overrun error or an underrun error will occur inside the communication control LSI 3. Therefore, when trying to connect a high-speed line, receive data read request IN TF
It is not possible to respond appropriately unless the priority of the transmission data write request OUT TF is made higher. However, as explained above, this requires hardware changes.

Conventionally, there has been a problem in that each communication control device has restrictions on the line speed that it can support, resulting in poor usage efficiency of the device itself.

The present invention has been made with attention to the above points, and provides an interrupt control method for a highly versatile communication control device that facilitates changing priority settings, can flexibly respond to changes in line communication speed, and is highly versatile. The purpose is to provide

(Means for Solving the Problems) The interrupt control method of the present invention accepts a plurality of interrupt signals, and determines which interrupt is granted first based on the priority set for each interrupt signal. A priority encoder is provided that selects one of the interrupt signals, determines and outputs an interrupt code for displaying the interrupt signal using a table for other codes, and changes the priority order in this priority encoder. The present invention is characterized in that two or more types of code/other patterns are prepared, and the code/other table is selected by a pattern selection signal.

(Function) In the above device, the priority encoder is provided with tables for codes of two or more patterns. Then, a pattern selection signal is inputted simultaneously with the plurality of interrupt signals inputted here. As a result, one type of pattern is selected from two or more types of patterns, and an interrupt code is generated using the table for other codes. This makes it possible to variously change the priority order of each interrupt signal depending on the communication line to be connected or as necessary.

(Example) Hereinafter, the present invention will be explained in detail using embodiments shown in the drawings.

FIG. 1 is a block diagram of main parts of a communication control device implementing the method of the present invention. The circuit shown in the figure is incorporated into the line interrupt circuit 5 of the line control section shown in FIG. 2, and has a configuration corresponding to the circuit shown in FIG. 3.

In the figure, this circuit includes a pattern register 10, an interrupt register 11, a priority encoder 12,
The device interrupt register 11, which is composed of a buffer 13, has a transmission/reception completion interrupt INT,
It is connected so that a received data read request IN TF, a transmitted data write request OUT TF, a modem signal interrupt MDM, and a timer interrupt TM are input. Furthermore, the interrupt register 11 is controlled by the sample clock CL to sample these five types of interrupt signals.

This interrupt register 11 operates almost the same as the register 51 already explained in FIG.

Further, the pattern register 10 is a register that stores a pattern selection signal inputted from the host processor via the internal bus 4, and the storage timing of this is also controlled by the sample clock CL.

Note that the interrupt register 11 outputs a 5-bit interrupt signal 11a, and the pattern register 10 outputs a 3-bit pattern selection signal 10a. Then, the pattern selection signal 10
a is the upper three bits of the priority encoder 12, that is, A. ,A.

The interrupt signal 11a is input to the address A2, and the interrupt signal 11a is connected to be input to the lower addresses A3 to At of the priority encoder 12. Furthermore, the priority encoder 12 is configured to accept 8-bit address signals 0-A7 and output a 1-bit line interrupt D0 and 3-bit interrupt codes D0-D. The priority encoder 12 is comprised of a memory in which a plurality of types of encoding tables are prepared for collectively encoding a plurality of interrupt signals, that is, 5-bit interrupt signals.

FIG. 4 shows a list of such interrupt codes.

As shown in this table, when the transmission/reception completion interrupt INT is input to the priority encoder, the interrupt code “111
" is output. Also, received data read request IN T
When F is input, an interrupt code "110" is output. Interrupt codes for the transmission data write request 011T TF, modem signal interrupt MDM, and timer interrupt TM are also output as shown in the table.

If there is no interrupt, the interrupt code is “010” or “
001" or "000". This code is reserved and is assigned to more interrupt types. In the method of the present invention, if one of the interrupt types is stored in the interrupt register 11. If only this interrupt signal is input, this exact interrupt signal is always output.

On the other hand, when two or more interrupts conflict, in the system of the present invention, several types of interrupt code encoding tables are prepared, and the priority order is selected by the pattern selection signal 10a (FIG. 1). .

For example, in FIG. 1, when a transmission/reception completion interrupt INT occurs, this interrupt signal 11a is sent to the lower address of the priority encoder 12 through the interrupt register 11. At the same time, the pattern selection signal 10a stored in the pattern register 10 by the host processor via the internal bus 4 is input to the priority encoder 12.

As a result, the outputs of the priority encoder 12, , D2. An interrupt code "111" is output to D3. This is stored in the buffer 13, and the internal bus 4
is read by the upper processor.

At the same time as these interrupt codes D+, D2, and D'l, a line interrupt D0 is input to the host device, and thereby a storage instruction 5TRE is output to the buffer 13, and the interrupt code is read. This procedure is similar to that described earlier using FIG.

Here, in this embodiment, the pattern selection signal 10
In order to allocate, for example, a 3-bit signal to a, it is possible to change the order of priorities in 8 patterns.

For example, the pattern selection signal 10a is Ao.

A1. When "000" is reached in the order of A2, this is set as pattern A. In that case, the priority is the interrupt signal TM,
MDM, OUT TF, IN TF, INT
shall increase in the order of In addition, pattern selection signal 1
Pattern B is when 0a becomes "001" in the order of Ao, A+, and Az. In this case, it is assumed that the priorities of the interrupt signal TNT and OUT TF in the case of pattern A are interchanged. Also, the pattern selection signal 10a is “0”.
In pattern C for 10'', the interrupt signal IN
It is assumed that TF is given top priority and TM comes second.

Eight types of patterns can be set in the manner described above.

If a priority pattern having all combinations of the five types of interrupt signals input to the interrupt register 11 is selected, the number of combinations will be 120. If these are arbitrarily selected using the pattern selection signal 10a, it is sufficient to set a 7-bit pattern selection signal.

Therefore, the maximum number of types of patterns can be determined by the number of bits other than the interrupt signal 11a input to the priority encoder 12.

Now, the circuit operations when various interrupt situations occur in the circuit of the type shown in FIG. 1 will be explained.

FIG. 5 is a signal list for explaining the specific operation of the system of the present invention.

First, in case (2) in FIG. 5, the pattern selection signals are set to "000" in the order of AI, A2, and A3, and pattern A is selected. Here, looking at the interrupt status, a received data read request IN TF has occurred, and an interrupt code "110" is output in response. At the same time, line interrupt D1 is also output with its content set to "1".

In this table, if there is an interrupt, it is "1", and if there is no interrupt, it is "0". In the 1-interrupt situation, the part marked with an "X" means invalid. That is, in the case of pattern A, the interrupt signal OUT TF
, MDM, and TM all have a lower priority than IN TF, so when an IN TF interrupt occurs, signals other than INT become invalid and ignored. Therefore, in this case, the interrupt signal becomes equivalent to "01"OOO", and the interrupt code "110" is output as shown in the table. As a result, the interrupt IN TF is accepted, It will be processed.

Also in case (2), the pattern selection signal selects pattern A. However, here, a transmission/reception completion interrupt INT occurs as an interrupt.

In this case, all other signals have low priority and are ignored. Therefore, the interrupt code "111" is output, the line interrupt becomes "1", and the interrupt INT is accepted and processed. That is, in this case, no matter which other interrupt occurs in competition, the result will not change.

Next, in case ■, the pattern selection signal is “°0
01", and pattern B is selected. Here,
When an interrupt IN TF occurs, 0, which has a higher priority than this,
Since there is no IJT TF interrupt, other low priority interrupts are ignored and an interrupt code "110" is output. Also, the line interrupt becomes "1". As a result, the interrupt IN T
F is accepted.

On the other hand, in case (3) where the same pattern B is selected by the pattern selection signal, the interrupt OUT with the highest priority
TF has occurred, and interrupt code “1” is generated in response to this.
01'' is output.Other interrupt signals have low priority and are ignored.

The contents of the line interruption are the same as the others.

Next, for cases ■ and ■, the pattern selection signal “0”
10" is output and pattern C is selected. For this pattern C, interrupt TM has the highest priority, followed by interrupt IN TF. Here, interrupt I
When N TF occurs (case ■), interrupt code “11”
0'' is output, and the process for that interrupt IN TF is accepted and executed. On the other hand, the interrupt TM with the highest priority
occurs, other signals are ignored and interrupt code “00
1'' is output and the interrupt TM is processed.

The table for other codes is completed by storing interrupt codes using the pattern selection signal and interrupt signal shown in FIG. 5 as addresses. The output of the part marked with an X may be the same whether it is "0" or "1".

In this way, by changing the pattern selection signal,
Each time, a different code table is selected and an interrupt code is generated.

Further, this pattern selection signal can be changed at any time during operation of the communication control device. Therefore, for example, if you change the communication speed of the line connected to the communication control device,
Outputs a new pattern selection signal from the host processor,
Settings can be changed immediately. Further, if a pattern for disabling all interrupts is provided as one of the patterns, an operation such as disabling all interrupts can be performed until the initial setting is completed.

Additionally, when supporting a special line, a pattern can be created to enable only certain interrupts, allowing for appropriate response. That is, it is also possible to dynamically change the priority level from a higher-level processor in accordance with changes in the state of the device.

Furthermore, instead of outputting and setting a pattern selection signal from the upper processor, output from a register specifying the line speed,
The output of a register for selecting the type of line may be used as a pattern selection signal. In this way, when the line speed is changed, the interrupt priority can be changed automatically without going through the host processor.

(Effects of the Invention) According to the interrupt control method of the present invention described above, it is possible to freely change the priority of each interrupt using a pattern selection signal for multiple interrupts generated in the line control unit. Since the optimum priority can be set, it is possible to improve the efficiency of interrupt processing.

Furthermore, since the priority order of each interrupt can be switched such as being disabled or enabled at any time, the time required for interrupt processing by the host processor can be shortened, and the efficiency of the processor can be expected to increase.

Further, since priorities and the like can be freely changed according to the line to be connected without changing the hardware, the versatility of the device can be increased.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a device implementing the method of the present invention, Fig. 2 is a block diagram of a conventional line control section, Fig. 3 is a block diagram of a conventional line interrupt circuit, and Fig. 4 is a block diagram of an interrupt code. Table 5 is a signal list for explaining the operation of the system of the present invention. 4... Internal bus, 10... Pattern register, 10
a... Pattern selection signal, 11... Interrupt register, lla... Interrupt signal, 12
...Priority encoder, 13...Buffer. Patent applicant Oki Electric Industry Co., Ltd.

Claims (1)

[Claims] Accepts a plurality of interrupt signals, selects one of the interrupt signals to be allowed to interrupt first, based on a priority set in advance for each interrupt signal, and A priority encoder is provided that determines and outputs an interrupt code for displaying an interrupt signal using a coding table, and the priority encoder is provided with a coding table of two or more patterns in which the priority order is changed. and selecting the encoding table according to a pattern selection signal.