JPH02110341U - - Google Patents
Info
- Publication number
- JPH02110341U JPH02110341U JP1989018828U JP1882889U JPH02110341U JP H02110341 U JPH02110341 U JP H02110341U JP 1989018828 U JP1989018828 U JP 1989018828U JP 1882889 U JP1882889 U JP 1882889U JP H02110341 U JPH02110341 U JP H02110341U
- Authority
- JP
- Japan
- Prior art keywords
- disconnects
- package
- view
- showing
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 claims 1
- 239000012212 insulator Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Switches Operated By Changes In Physical Conditions (AREA)
Description
第１図は本考案のＩＣパツケージを示す背面図
、第２図、第３図は第１図のＡ―Ａ′断面図、第
４図は絶縁体を示す平面図、第５図は同側面図、
第６図、第７図は本考案の実施例２を示す断面図
、第８図は絶縁体を示す平面図、第９図は同側面
図、第１０図は従来のＩＣパツケージを示す断面
図である。
１……絶縁体、２……ＩＣピン、３……リード
フレーム、４……ボンデイングワイヤー、５……
ＩＣチツプ、６……導体、７……バネ、８……封
入キヤツプ、１０……パツケージ。
Fig. 1 is a rear view showing the IC package of the present invention, Figs. 2 and 3 are sectional views taken along line AA' in Fig. 1, Fig. 4 is a plan view showing the insulator, and Fig. 5 is the same side view. figure,
6 and 7 are cross-sectional views showing a second embodiment of the present invention, FIG. 8 is a plan view showing an insulator, FIG. 9 is a side view of the same, and FIG. 10 is a cross-sectional view showing a conventional IC package. It is. 1... Insulator, 2... IC pin, 3... Lead frame, 4... Bonding wire, 5...
IC chip, 6...conductor, 7...spring, 8...enclosed cap, 10...package.
Claims (1)
ツチをパツケージに有することを特徴とするＩＣ
パツケージ。 An IC characterized in that the package has a switch that disconnects and disconnects the connection between the IC pin and the IC chip.
Packaging.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989018828U JPH02110341U (en) | 1989-02-20 | 1989-02-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989018828U JPH02110341U (en) | 1989-02-20 | 1989-02-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02110341U true JPH02110341U (en) | 1990-09-04 |
Family
ID=31233816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989018828U Pending JPH02110341U (en) | 1989-02-20 | 1989-02-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02110341U (en) |
-
1989
- 1989-02-20 JP JP1989018828U patent/JPH02110341U/ja active Pending