JPH02106926A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02106926A
JPH02106926A JP63261134A JP26113488A JPH02106926A JP H02106926 A JPH02106926 A JP H02106926A JP 63261134 A JP63261134 A JP 63261134A JP 26113488 A JP26113488 A JP 26113488A JP H02106926 A JPH02106926 A JP H02106926A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor
semiconductor substrate
well region
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63261134A
Other languages
Japanese (ja)
Inventor
Atsuo Yagi
八木 厚夫
Takeshi Matsushita
松下 孟史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP63261134A priority Critical patent/JPH02106926A/en
Publication of JPH02106926A publication Critical patent/JPH02106926A/en
Pending legal-status Critical Current

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  • Mechanical Treatment Of Semiconductor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To accurately control impurity doping even in low concentration by allowing a reinforcing board to adhere, and removing a semiconductor substrate from the opposite side to the reinforcing board adhering side by polishing to a predetermined thickness. CONSTITUTION:In an ion implanting step, since the ion implantation is conducted in a state that a semiconductor substrate 21 is sufficiently thick, the implantation having a peak at a relatively deep position can bs executed, and the depth peak position Rp from the surface can be set relatively accurately. Accordingly, implanting impurity concentration can be accurately controlled. Therefore, since the substrate 21 is removed by polishing to a thin film state after a reinforcing board 22 is applied, a P-well region and a N-well region can be formed in predetermined low concentration by applying, for example, to a C-MOS integrated circuit, and a MOS transistor is formed on the sufficiently thin substrate film. Thus, a semiconductor device having stable characteristics can be obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野] 本発明は、半導体装置例えば異なる導電型の半導体領域
例えばpウェル領域及びnウェル領域を有する半導体集
積回路装置に適用して好適な半導体装置の製造方法に関
わる。
Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device suitable for application to a semiconductor device, for example, a semiconductor integrated circuit device having semiconductor regions of different conductivity types, such as a p-well region and an n-well region. Related to manufacturing methods.

〔発明の概要〕[Summary of the invention]

本発明は、半導体基板に不純物をイオン注入して後にこ
の半導体基板に補強基板を貼合合体させ、この補強基板
の貼合側とは反対側より半導体基板を研磨除去して所定
の厚さとすることによって所要の不純物導入がなされた
薄膜半導体層を有する半導体装置を得るもので、このよ
うにして薄膜半導体層といえども低不純物濃度の半導体
領域を高い精度の不純物濃度をもって形成することがで
きるようにする。
The present invention involves ion-implanting impurities into a semiconductor substrate, then bonding a reinforcing substrate to the semiconductor substrate, and polishing and removing the semiconductor substrate from the side opposite to the bonding side of the reinforcing substrate to obtain a predetermined thickness. By doing this, a semiconductor device having a thin film semiconductor layer into which the required impurities have been introduced can be obtained, and in this way, a semiconductor region with a low impurity concentration can be formed with a highly accurate impurity concentration even in a thin film semiconductor layer. Make it.

〔従来の技術〕[Conventional technology]

各種半導体装置例えば相補型の絶縁ゲート型電界効果ト
ランジスタいわゆるC−MOSを有する半導体集積回路
を製造する場合においては、共通の基板にp型及びn型
の互いに異なる導電型の領域すなわちいわゆるpウェル
領域及びnウェル領域の形成が必要となる。そして、こ
れら各ウェル領域はその不純物濃度が比較的小に選定さ
れる必要がある。この不純物導入技術としてイオン注入
法は高い精度での不純物ドーピング制御を行うことがで
きるという上で広く用いられている。
When manufacturing various semiconductor devices, for example, semiconductor integrated circuits having complementary insulated gate field effect transistors, so-called C-MOS, regions of different conductivity types, p-type and n-type, or so-called p-well regions are formed on a common substrate. It is also necessary to form an n-well region. Each of these well regions must be selected to have a relatively low impurity concentration. Ion implantation is widely used as an impurity introduction technique because it allows highly accurate impurity doping control.

一方、単結晶半導体例えばシリコン単結晶層を1000
Å以下に薄膜化すると短チャンネル効果の抑制など昨今
のより微細化の要求に適した特性の例えば絶縁ゲート形
トランジスタ(MOS)等が得られることが知られてい
る。
On the other hand, a single crystal semiconductor such as a silicon single crystal layer is
It is known that when the film is made thinner than Å, it is possible to obtain, for example, an insulated gate transistor (MOS) with characteristics suitable for the recent demands for further miniaturization, such as suppression of short channel effects.

ところが、このような薄膜化された単結晶層中に不純物
をイオン注入する場合、特に低不純物濃度においての濃
度制御が低下して(る。第2図を参照して例えば5i0
2よりなる絶縁基+l)上に形成されたシリコン単結晶
薄膜(2)に対してイオン注入によって不純物ドーピン
グを行う場合と、第3図に示すように厚いシリコン半導
体基板(10に対して不純物のイオン注入を行う場合と
対比して考察する。第2図及び第3図においては、それ
ぞれ表面にSiO□ゲート絶縁膜(3)が形成され、こ
れら絶縁膜(3)を介してイオン注入を行う場合で、今
、濃度分布を横軸にとって実線aで示す目的とする濃度
プロファイルを有するイオン注入を行おうとする場合に
ついて説明する。この場合濃度プロファイルのピーク位
置Rpを浅く選定することは難しいため各図において破
線すで示すように、濃度分布に深い方向へのずれが生じ
易い。そしてこのずれが生じた場合をみると第3図の場
合は基板aD中の濃度分布のピーク位置は、実線aと破
線すとでは異るものの全体の不純量については差程変化
しない。
However, when impurity ions are implanted into such a thin single-crystal layer, concentration control deteriorates, especially at low impurity concentrations.
In the case of impurity doping by ion implantation to the silicon single crystal thin film (2) formed on the insulating base consisting of Consider this in comparison with the case of ion implantation. In Figures 2 and 3, a SiO□ gate insulating film (3) is formed on the surface, and ion implantation is performed through these insulating films (3). Now, we will explain the case where ion implantation is to be performed with the target concentration profile shown by the solid line a with the concentration distribution on the horizontal axis.In this case, it is difficult to select a shallow peak position Rp of the concentration profile, so each As already shown by the broken line in the figure, the concentration distribution tends to shift in the deeper direction.When this shift occurs, in the case of FIG. Although there is a difference between the curve and the dashed line, the overall amount of impurities does not change much.

これに比し、第2図の場合薄膜単結晶層(2)からその
ピーク値がずれるとこの単結晶シリコン層(2)中にお
ける不純物の実質的ドーピング量が激減する。
In contrast, in the case of FIG. 2, when the peak value deviates from the thin film single crystal layer (2), the substantial amount of impurity doped in the single crystal silicon layer (2) is drastically reduced.

したがってその後におけるアニール処理、すなわち不純
物の活性化、不純物の拡散処理を行った場合においてそ
の濃度が大きく相違してくるという不都合がある。すな
わち、今イオン注入のピーク位置の表面からの距離Rp
はイオン注入装置の限界により通常ボロンイオンB゛の
場合的900人程度であり、一方ゲート絶縁膜(3)の
厚さを100人とすれば第2図の場合半導体層(2)の
厚さを800Å以下とする場合、そのピーク位置が半導
体層(2)からはずれてしまうために実質的不純物濃度
が大きく相違して(る。
Therefore, when subsequent annealing treatment, ie, impurity activation and impurity diffusion treatment, is performed, there is a problem that the concentration will be greatly different. That is, the distance Rp from the surface of the current peak position of ion implantation
Due to the limitations of the ion implantation equipment, the number of implanters for boron ions B is normally around 900. On the other hand, if the thickness of the gate insulating film (3) is 100, the thickness of the semiconductor layer (2) in the case of Fig. 2 is approximately 900. When it is 800 Å or less, the peak position is shifted from the semiconductor layer (2), resulting in a large difference in the substantial impurity concentration.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

本発明においては、薄膜半導体層を有する半導体装置を
製造する場合に当ってイオン注入技術の適用をなして、
低濃度においても正確に不純物ドープの制御を行うこと
ができるようにして例えばC−MOS l−ランジスタ
の薄膜型集積回路を安定した特性をもって製造すること
ができるようにする。
In the present invention, when manufacturing a semiconductor device having a thin film semiconductor layer, ion implantation technology is applied,
It is possible to accurately control impurity doping even at low concentrations, so that thin film integrated circuits such as C-MOS l-transistors can be manufactured with stable characteristics.

〔課題を解決するための手段〕[Means to solve the problem]

本発明においては、第1図Aに示すように比較的厚い半
導体基板(21)に対して不純物導入をイオン注入する
工程と、第1図りに示すように補強基板(22)を貼合
合体させる工程と、第1図Eに示すように半導体基板(
21)を補強基板(22)の貼合側とは反対側より研磨
除去して所要の厚さとする工程とをとる。
In the present invention, as shown in FIG. 1A, there is a step of ion-implanting impurities into a relatively thick semiconductor substrate (21), and a step of laminating a reinforcing substrate (22) as shown in FIG. process, and as shown in Figure 1E, the semiconductor substrate (
21) from the side opposite to the bonding side of the reinforcing substrate (22) to obtain a desired thickness.

〔作用〕[Effect]

上述の本発明製法によれば、イオン注入の工程に当って
は半導体基板(21)すなわち充分厚さの大なる状態で
イオン注入が行われるので比較的深い位置にピークを有
するイオン注入を行うことができて、比較的高精度にそ
の表面からの深さピーク位置Rρの設定を行うことがで
きるので導入不純物濃度を高精度にコントロールするこ
とができ、最終的に補強基板(22)が貼合せられて後
に半導体基板(21)に対する研磨除去によって薄膜状
とされるので例えばC−MOS集積回路に適用してPウ
ェル領域及びnウェル領域をそれぞれ所要の低不純物濃
度をもって形成することができ、かつ充分薄い半導体薄
膜に対してMOS−)ランジスタの形成を行うので安定
した特性のよい半導体装置を得ることができる。
According to the manufacturing method of the present invention described above, in the ion implantation process, ions are implanted into the semiconductor substrate (21), that is, in a sufficiently thick state, so that ion implantation having a peak at a relatively deep position can be performed. Since the depth peak position Rρ from the surface can be set with relatively high precision, the concentration of introduced impurities can be controlled with high precision, and the reinforcing substrate (22) is finally bonded. The semiconductor substrate (21) is then removed by polishing to form a thin film, so it can be applied to, for example, a C-MOS integrated circuit to form a P-well region and an N-well region each with a required low impurity concentration, and Since the MOS transistor is formed on a sufficiently thin semiconductor film, a semiconductor device with stable and good characteristics can be obtained.

〔実施例〕〔Example〕

第1図を参照してさらに本発明によるpウェル領域とn
ウェル領域とを有し薄膜半導体層を有する半導体装置を
得る場合の一例を説明する。
Referring to FIG. 1, the p-well region and the n-well region according to the present invention
An example of obtaining a semiconductor device having a well region and a thin film semiconductor layer will be described.

まず、第1図Aに示すように例えば300〜600μm
の大なる厚さを有する半導体基板(21)例えばシリコ
ンウェファを用意し、その−主面(21a)上に必要に
応じて100−1000人の熱酸化によるイオン注入時
のイオン衝撃による表面ダメージを保護するだめの表面
保護膜(23)を熱酸化等によって形成する。そして、
この表面保護膜(23)上よりあるいは基板(21)の
−主面(21a)に直接的にp型の不純物例えばボロン
を選択的にイオン注入する工程とn型の不純物例えば砒
素イオンを例えば選択的にイオン注入する工程とを行っ
て半導体基板(21)の比較的深い位置にそれぞれ島状
の第1及び第2の不純物導入領域(24,)及び(24
□)を形成する。
First, as shown in FIG. 1A, for example, 300 to 600 μm
A semiconductor substrate (21), for example, a silicon wafer, having a large thickness of A protective surface protective film (23) is formed by thermal oxidation or the like. and,
A step of selectively ion-implanting p-type impurities, such as boron, onto the surface protective film (23) or directly into the main surface (21a) of the substrate (21), and selecting n-type impurities, such as arsenic ions, for example. island-shaped first and second impurity-introduced regions (24,) and (24,
□).

第1図Bに示すように、必要に応じて表面保護膜(23
)を除去し、選択的に半導体基板(21)の例えば主面
(21a)側からメサエッチングを施して各第1の不純
物領域(24,)及び第2の不純物領域(24□)を溝
(25)によって画成する。
As shown in Figure 1B, a surface protective film (23
) and selectively perform mesa etching from, for example, the main surface (21a) side of the semiconductor substrate (21) to form grooves ( 25).

そして、所要のアニール処理を施して第1及び第2の不
純物導入領域(24,)及び(24□)の不純物の再拡
散及び活性化処理を施して少くとも溝(25)によって
囲まれた各メサ部内にP型化あるいはn型化された各互
いに導電型を異にする第1及び第2のウェル領域(26
υ及び(26□)を形成する。
Then, a necessary annealing process is performed to re-diffuse and activate the impurities in the first and second impurity-introduced regions (24,) and (24□), so that each region surrounded by at least the groove (25) First and second well regions (26
Form υ and (26□).

次に第1図Cに示すように、溝(25)内を含んで半導
体基板(21)の主面(21a)側の表面上に例えば熱
酸化によるSin、絶縁膜(27)を形成し、更にこれ
の上にSin!を例えば1000Å以上の厚さ例えば1
μmに化学的気相成長法(CVD法)によって溝(25
)を埋め込むように被着形成して絶縁層(28)を形成
する。そして、この絶縁層(28)の表面を研磨して鏡
面(28a)を形成する。
Next, as shown in FIG. 1C, an insulating film (27) of, for example, Sin is formed by thermal oxidation on the main surface (21a) side surface of the semiconductor substrate (21) including the inside of the groove (25), Furthermore, on top of this, Sin! For example, if the thickness is 1000 Å or more, for example 1
Grooves (25 μm) are formed by chemical vapor deposition (CVD).
) to form an insulating layer (28). Then, the surface of this insulating layer (28) is polished to form a mirror surface (28a).

一方、第1図りに示すように、−主面(22a)に5i
n1等の絶縁層(29)が形成されその表面が鏡面(2
9a)とされた例えば厚さ300〜600μmのシリコ
ン基板あるいは石英基板等より成る補強基板(22)を
貼合せる。この貼合せは接着剤によって被着することも
できるが、鏡面(28a)及び(29a)の相互の合致
によるのみでその貼合が達成できる。
On the other hand, as shown in the first diagram, 5i on the main surface (22a)
An insulating layer (29) such as n1 is formed and its surface has a mirror surface (29).
A reinforcing substrate (22) made of, for example, a silicon substrate or a quartz substrate having a thickness of 300 to 600 μm as shown in FIG. 9a) is laminated. Although this bonding can be done by adhesive, it can be achieved only by the mutual matching of the mirror surfaces (28a) and (29a).

次に第1図Eに示すように、半導体基板(21)をその
補強基板(22)の貼合側とは反対側から化学的機械的
エツチング等によって研磨除去して各第1及び第2の不
純物導入ウェル領域(26,)及び(26りを互いに分
離する。この場合その研磨はそのエツチングが絶縁膜(
27)に達してエツチングの進行が低下することを利用
してこの位置でそのエツチングを停止すれば、確実に各
領域(26+) (26g)が分離されかつ薄膜半導体
層として所要の厚さに残すことができる。すなわち溝(
25)の深さを予め選定しておくことによって各領域(
26,) (26□)の厚さを所要の薄膜状に設定する
ことができる。
Next, as shown in FIG. 1E, the semiconductor substrate (21) is removed by chemical mechanical etching or the like from the side opposite to the side to which the reinforcing substrate (22) is bonded. The impurity-introduced well regions (26,) and (26) are separated from each other.
If etching is stopped at this position by taking advantage of the fact that the progress of etching slows down when the etching reaches 27), each region (26+) (26g) is reliably separated and left at the required thickness as a thin film semiconductor layer. be able to. In other words, the groove (
25) By pre-selecting the depth of each area (
26,) (26□) can be set to a desired thin film thickness.

その後において、このようにして形成された薄膜ウェル
領域(26,)及び(26g)に対してそれぞれ絶縁膜
の形成及びソース及びドレインの形成等を行えばC−M
OS等の互いにチャンネル導電型を異にするMOS−1
−ランジスタを回路素子とする半導体集積回路を得るこ
とができる。
After that, if an insulating film and a source and drain are formed on the thin film well regions (26,) and (26g) thus formed, respectively, C-M
MOS-1 with different channel conductivity types such as OS
- It is possible to obtain a semiconductor integrated circuit using transistors as circuit elements.

的厚い半導体基板に対しての深い位置にピーク位置を有
するイオン注入として行うことができるので、最終的に
高精度に不純物の濃度設定を行うことができ、特性の安
定した半導体装置を得ることができる。
Since ion implantation can be performed with a peak position deep into a thick semiconductor substrate, it is possible to ultimately set the impurity concentration with high precision, and it is possible to obtain a semiconductor device with stable characteristics. can.

【図面の簡単な説明】[Brief explanation of drawings]

第1図A−Eは本発明製法の一例の各工程の路線的断面
図、第2図及び第3図は不純物イオン注入の濃度分布の
説明図である。 (21)は半導体基板、(22)は補強基板、(26+
)及び(26□)は第1及び第2のウェル領域である。
FIGS. 1A to 1E are line sectional views of each step of an example of the manufacturing method of the present invention, and FIGS. 2 and 3 are explanatory views of the concentration distribution of impurity ion implantation. (21) is a semiconductor substrate, (22) is a reinforcement substrate, (26+
) and (26□) are the first and second well regions.

Claims (1)

【特許請求の範囲】 半導体基板に不純物を導入するイオン注入工程と、 上記半導体基板に補強基板を貼合合体させる工程と、 上記半導体基板を所要の厚さだけ残して上記補強基板の
貼合側とは反対側より研磨除去する工程とを有すること
を特徴とする半導体装置の製造方法。
[Claims] An ion implantation step for introducing impurities into a semiconductor substrate, a step for laminating a reinforcing substrate to the semiconductor substrate, and a side to which the reinforcing substrate is bonded, leaving a required thickness of the semiconductor substrate. A method of manufacturing a semiconductor device, comprising the step of polishing and removing from the opposite side.
JP63261134A 1988-10-17 1988-10-17 Manufacture of semiconductor device Pending JPH02106926A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63261134A JPH02106926A (en) 1988-10-17 1988-10-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63261134A JPH02106926A (en) 1988-10-17 1988-10-17 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02106926A true JPH02106926A (en) 1990-04-19

Family

ID=17357565

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63261134A Pending JPH02106926A (en) 1988-10-17 1988-10-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02106926A (en)

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