JPH0210677B2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a drive device for a DC motor.

[Conventional technology]

Conventionally, there has been a technique of this type as shown in FIG. In Figure 1, 1 is the detection signal i _d from the current command i ^* and the current actually supplied to the DC motor.
an adder that detects the difference between the two and outputs a signal ΔI;
is an amplifier that amplifies the signal ΔI, and 3 and 4 are amplifiers 2
The output of the amplifier is compared with the triangular wave carrier signal CRY, and the part where the amplifier output is large is output as a pulse, that is, a pulse width modulated signal PWM,
Comparators that output PWMN, 5 and 6 are comparators 3,
An inverter that inverts the 4 signals PWM and PWMN,
7 to 10 are on-delay circuits that delay the outputs of the comparators 3 and 4 and the outputs of the inverters 5 and 6 by a time Td.
Supply PWMd, PWMNd. 15
is the connection point C1 between transistor 11 and transistor 12, and the connection point _C1 between transistor 13 and transistor 14.
It is a (DC) motor connected between the connection point C and ₂ . Next, the operation will be explained. Figure 2 shows adder 1
The waveforms of each part are shown when the signal ΔI is 0. time t ₀
Until then, transistors 11 and 13 are on and transistors 12 and 14 are off, and the connection point C ₁
Since the voltage V ₁ at the node C ₂ and the voltage V ₂ at the connection point C 2 are both the power supply voltage, V ₁ −V ₂ is 0. During the time Td selected to be longer than the charge accumulation time Ts of the transistors 11 to 14, that is, from time t ₀ to _{t 1} in FIG. 2, the transistors 11 to 14 are all off, and the voltage V ₁ -V ₂ is undefined. becomes. At time t ₁ in FIG. 2, transistors 12 and 14 are turned on, and connection points C ₁ and C ₂ become 0 voltage. FIG. 3 shows waveforms at various parts when the signal ΔI reaches a voltage that fluctuates around 0 (when the difference between the command current i ^* and the detected current i _d fluctuates around 0). At time _t0 in FIG. 3, transistor 13 is turned off, and at time _t1 in FIG. 3, transistor 11 is turned off. Time from time t ₀ in Figure 3
At time _t2 after Td, transistor 14 is turned on, and further at time _t3 , which is a time Td after time t1 in FIG. ₃ , transistor 12 is turned on. Therefore, in FIG.
12 are both off, that is, the time shown in Figure 3.
From t ₁ to t ₃ , the voltage V ₁ at the connection point C ₁ is undefined (the voltage V ₁ is determined by the direction of the current flowing through the motor 15). Similarly, transistors 13,1
4 are both off, that is, time t ₀ in Figure 3.
During the period from t2 to _t2 , the voltage _V2 at the connection point _C2 is undefined (the voltage _V2 is determined by the direction of the current flowing through the motor 15). The reason why the period in which the transistors 11 and 12 and the transistors 13 and 14 are off is necessary is that when the transistor turns off later than the transistor turns on due to the charge accumulation period Ts of the transistor,
This is because there is a period in which the series-connected transistors 11 and 12 or the transistors 13 and 14 are both turned on, resulting in destruction of the transistors. The conventional DC motor drive device is configured as described above, and has a period in which the series-connected transistors 11 and 12 and transistors 13 and 14 are both off, so that the motor 15 during the off period is
Since the voltages V ₁ and V ₂ are determined by the current direction of
That is, the voltage V ₁ at the connection point C ₁ and the voltage V ₂ at the connection point C ₂
becomes unstable, and there is a control dead zone in which the voltage applied to the motor 15 does not appear as changed even if the signal ΔI, which is the command signal, changes in a region where the difference between the current command and the current signal detected from the DC motor is small. However, this dead zone cannot be removed simply by increasing the loop gain.

[Summary of the invention]

This invention has been made in view of the above points, and is the falling edge of the voltage signal PC indicating the voltage at the output terminal of a device that supplies drive current to a DC motor and the pulse width modulation signal that is input to the on-delay circuit. An object of the present invention is to provide a DC motor drive device that can eliminate a control dead zone and improve the response characteristics of the device by detecting a phase difference and compensating the phase of the rise of a pulse width modulated pulse signal using this phase difference. shall be.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 shows a block diagram according to the present invention, and the same reference numerals as those shown in FIG. 1 indicate the same parts. The command signal PWM of the comparator 3 is input to one side of the AND gate 16 and one side of the AND gate 17 via the inverter 29 . Furthermore, the detection signal PC detected from the output end of the device is inputted to the other side input of the AND gate 16 via the inverter 18, and is ANDed with the command signal PWM.
Output signal PDIF. Furthermore, and gate 1
The detection signal PC is inputted to the other side input of 7, ANDed with the inverted signal of the command signal PWM, and the signal is outputted via the inverter 19. Integrator 20
inputs the signal PDIF, integrates it, and calculates the signal
Output PINT. Comparator 21 includes a zero-cross detector, detects the zero-cross point of signal PINT, and outputs signal PWMC. The signal PWMC is input to the on-delay circuits 7 and 9 and the on-delay circuits 8 and 10 via the inverter 22. A photo coupler 23 serving as a voltage detector is connected to the connection point C ₁ between the transistors 11 and 12 and the connection point C ₂ between the transistors 13 and 14, respectively, and a detection signal indicating the voltage at the connection point C ₁ and the connection point C ₂ is connected.
Output PC. Note that the connection point C ₂ between transistors 13 and 14
The detection signal PC indicating the voltage at the connection point _C1 of the transistors 11 and 12 can be considered in the same way as the detection signal PC indicating the voltage at the connection point _C1 .
Only the side will be explained. The next operation will be explained with reference to FIG.
Now, when controlling the voltage V ₁ at the connection point C ₁ with the pulse width modulated command signal PWM as shown in Fig. 5, at time t ₀ , the previous command signal PWM and the detection signal
The difference with PC is stored as the voltage _V3 of the signal PINT shown in FIG. Therefore, even if the command signal PWM becomes high level, the signal PWMC remains at 0 until the signal PINT becomes 0. And time t ₀
When the AND gate 16 opens, the integrator 20 starts integrating the signal PDIF having a positive value, and the voltage increases. At time t ₁ , the signal
Since PINT crosses the 0 axis, the output of the signal PWMC from the comparator 21 changes, canceling out the above error. Then, the signal from the comparator 21
PWMC becomes high level and outputs an on signal, but the voltage V ₁ at connection point C ₁ does not change yet due to the delay of the base amplifier transistor, etc., and the command signal PWM
Since the correct voltage V ₁ cannot be obtained, the signal PINT in FIG. 5 continues to be added. After that, transistor 1 with charge storage time Ts
At time _t2 , after a sufficient time Td for PWMCd to turn off, the on-delay circuits 7 and 9 turn off the signal PWMCd.
is set high to turn on transistor 11.
When the transistor 11 is turned on, the voltage V ₁ at the connection point C ₁ becomes the power supply voltage, so the detection signal PC of the photocoupler 23 becomes high, and as a result, the AND gate 16 is blocked and the integrator 20 stops integrating. , hold its integral value. The signal PINT= _V4 at this time becomes the error. At time t ₃ , which is a time T ₁ after time t ₀ , the command signal PWM becomes low, so the AND gate 17 opens and the integrator 20 starts integrating a signal having a negative value via the inverter 19. . At time _t4 , the signal PINT crosses the 0 axis, so the comparator 21 makes the signal PWMC low, and the on-delay circuit 7 makes the signal PWMCd low. Therefore, the transistor 11 is turned off at time _t5 after the charge accumulation time Ts. Transistor 12 is the time
At time _t6 , which is a time Td after _t4 , it is turned on by the on-delay circuit 8, and thereafter the above-described operation is repeated in accordance with the command signal PWM. Detection signal every time like this
Since the correction is applied using a PC, the output voltage according to the command can be obtained in the end. FIG. 6 is a block diagram showing another embodiment of the present invention, in which only the portions corresponding to the portions within the dotted lines shown in FIG. 4 are shown. Signal from AND gate 16
The PDIF is led to the AND gate 24, ANDed with the clock signal CLK from the clock generator 25, and the result is input to the up-count input UP of the up-down counter 26 as an integration circuit. The signal from the AND gate 17 is guided to the AND gate 27, ANDed with the clock signal CLK, and the result is inputted to the up/down counter 26.
Enter the DN. The carry signal CR of the up-down counter 26 is input to the set input S of the flip-flop 28, and the borrow signal BR is input to the reset input R of the flip-flop 28. The Q output of the flip-flop 28 is supplied to the on-delay circuit 7, and the output is supplied to the on-delay circuit 8. Next, in operation, AND gate 16 or 17
When is open, the up-down counter 26 integrates the phase difference between the command signal PWM and the detection signal PC through up-counting or down-counting, and when the result becomes 0, it outputs a carry signal CR or a borrow signal BR. occurs, sets or resets flip-flop 28, and switches on-delay circuit 7 or 8.
energize.

【Effect of the invention】

As described above, according to the present invention, the difference between the voltage signal, that is, the detection signal, indicating the voltage at the output end of the device that supplies the drive current to the DC motor, and the pulse width modulated pulse signal, that is, the command signal, is detected by the integrating circuit. Count, and then when the command signal changes,
Since the difference is corrected and output as a transistor signal, the dead zone of control is narrowed, a signal in accordance with the command signal can be obtained as the output voltage, and the control characteristics of the device can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional DC motor drive device, FIGS. 2 and 3 are waveform diagrams of the operation of the device shown in FIG. 1, and FIG. 4 is a diagram of a DC motor drive device according to an embodiment of the present invention. FIG. 5 is a waveform diagram of the operation of the apparatus shown in FIG. 4, and FIG. 6 is a block diagram of another embodiment of the present invention. 1...Adder, 2...Amplifier, 3, 4, 21...
... Comparator, 7-10 ... On-delay circuit, 11
~14...transistor, 15...motor, 20
...integrator. In addition, in the figures, the same reference numerals indicate the same parts.

Claims (1)

[Claims] 1. A pair of series circuits in which two transistors are connected in series between DC power supply lines so that they are turned on alternately by pulse width modulated pulse signals, and a DC motor connected to each connection point of the series-connected transistors. In the DC motor drive device having the above-mentioned DC motor, two
a detector that detects the voltage at the connection point of the switching transistors; a gate circuit that detects the phase difference between the pulse width modulated pulse signal and the detection signal of the detector; a comparator that detects the zero voltage level of the output signal of this integrator and converts it into a pulse signal, and the pulse signal of this comparator is delayed by a delay time that is longer than the charge accumulation time of the above transistor. and an on-delay circuit that turns on the transistor.