JPH02103631A - Access device for program memory - Google Patents

Abstract

PURPOSE:To operate a microprocessor at high speed by updating the address of a program memory in parallel with the data fetching of the microprocessor and shortening reading time on a 2nd and subsequent bytes of an instruction composed of plural bytes. CONSTITUTION:When a microprocessor 1 reads the leading byte of an instruction in a program memory 2, the area of the same address as that of the leading byte in an instruction byte side memory 9 is also read simultaneously and the byte size 17 of the instruction and leading address of the instruction are respectively loaded into counters 6 and 7. Simultaneously, the program memory 2 is made accessed through the counter 7 which increments the byte size and address at the timing similar to the timing of the conventional system. Therefore, the reading time on the 2nd and subsequent bytes of an instruction composed of plural bytes can be shortened and the microprocessor 1 can be run at high speed.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a program memory access device in a microprocessor system, and particularly to an access device that can speed up read processing. Note that in the following figures, the same reference numerals indicate the same or corresponding parts.

[Conventional technology]

FIG. 4 is a block diagram when a microprocessor reads a program according to the conventional method, and FIG. 5 is a diagram showing the timing of each signal in FIG. 4. The program read procedure will be described below using FIGS. 4 and 5. (a) The microprocessor 1 outputs address 10 of the program memory 2 containing the next instruction to be executed onto the address bus AB (FIG. 5, ■). At the same time, an address strobe signal 11 indicating that the address 10 is valid is established (Fig. 5, time t, 1).
). (5) Address 10 and address strobe signal 11 are decoded via decoder 3, and program memory 2
A program memory select signal 12 is generated indicating that the program memory has been selected (FIG. 5). (C) Program memory 2 uses this select signal 12
Data 13 specified by and address 10 is output onto data bus DB. (Figure 5 ■). (d) After waiting for the data 13 output by the program memory 2 to become stable, the program memo 172 establishes the data strobe signal 14 indicating that the data 13 is valid (FIG. 5, time t2). (e) The microprocessor 1 receives the data 13 on the data bus DB using the data strobe signal 14. At the same time, the microprocessor 1 erases the address 10 and the address strobe signal 11, and the program read cycle ends (Fig. Knowing the end, data 13 and data strobe signal 5 disappear (fifth
Figures ■, ■). The above is a general microprocessor read cycle. Such a read cycle is performed every time the microprocessor reads a program or data. FIG. 6 shows how the programs are arranged on the memory 2. Unlike data, a program consists of a set of inseparable data blocks called instructions. For example, in the same figure, I al * I a2. ~I
c3 is a data block that constitutes the instruction a ``-' c, and each data block is arranged in address order.The instruction a is constituted by four data blocks Ial to Ia4, and similarly, Instructions and C each have two data blocks Ib1.
Ib2, and three data blocks Icl to Ic
It is composed of 3. In addition, below, I al, I a2. Each data block, such as .

[Problem to be solved by the invention]

As described above, each instruction making up a program is made up of a predetermined number of data blocks (bytes) determined by the type of instruction, so it is sometimes possible to predict in advance the address that the microprocessor will access next. In such a case, using read cycles similar to those in the unpredictable case is not effective in making the microprocessor run at high speed. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a program access device for reading programs at high speed.

[Means to solve the problem]

In order to solve the above problems, the device of the present invention includes a program memory (such as 2) in which each instruction constituting a t-program consists of one or more bytes, and the program is stored by sequentially assigning an address to each byte. and a microprocessor (such as 1) that operates while reading this program memory, the output data of the program memory (such as a data latch circuit (such as 5) that latches the data (such as 16) and provides it as data (such as 13) to the microprocessor; and a memory that is accessed simultaneously with the access of the first byte in each of the above instructions; an instruction byte size memory (9, etc.) that stores the byte size (17, etc.) of the instruction; and the instruction byte size read from the instruction byte size memory upon access of the first byte is initialized, and the instruction byte size read from the instruction byte size memory is initialized for subsequent instructions. An instruction byte size counter (such as 6) that is counted down each time each byte in the instruction is sequentially accessed; After the data is latched by the data latch circuit, the remaining count of the instruction byte size counter is controlled to access one byte of the address following this one byte before the microprocessor completes reading of at least one byte. It is assumed that j is provided with means (such as an address counter 7) for repeating until the numerical value becomes 1.

[For use]

In this invention, when the first address byte of the bytes constituting one instruction is read, the data of the remaining bytes of this instruction are prepared in advance before being read by the microprocessor, and when read, the data is We will use a method that allows us to import this data. This is intended to shorten the time required to read the data of the second and subsequent bytes in one instruction byte.

【Example】

The present invention will be described in detail below with reference to FIGS. 1 to 3. FIG. 1 is a block diagram when a microprocessor according to the present invention reads a program, and corresponds to FIG. 4. The address 10 and address strobe signal 11 output by the microprocessor 1 are entered into the program memory I72 as a program memory select signal 12 via the memory access controller 4. The output data 16 of the program memory 2 is temporarily held in the data latch circuit 5, and then sent from the data latch circuit 5 to the microprocessor as data 13 by a data strobe signal 14.
The structure is such that it is output along with the FIG. 2 shows program memory 2. Memory access controller 4. 5 is a diagram showing a detailed configuration of a data latch circuit 5. FIG. In the figure, 2 is a conventional program memory. Reference numeral 9 denotes an instruction data number memory within the memory access controller 4, which is another memory having an address corresponding to the program memory 2. In the address area of this memory 9 corresponding to the address of the first byte of each instruction in the program memory 2, the number of bytes constituting one instruction (referred to as instruction byte size) is stored. The instruction byte size 17 as the contents of the memory 9 is generated at the same time when the program is coded. 6 is an instruction byte size counter;
This is a counter for sequentially sending data after the byte. When it is not counting, that is, when the first byte of each instruction is read from microprocessor l, it loads the instruction byte size 17 into its own counter. Thereafter, each time reading of each byte is completed, the number of remaining bytes is decreased. Reference numeral 7 denotes an address counter, which is a counter for supplying the program memory address 15 to the program memory 2. When the instruction byte size counter 6 is not counting, the address 10 from the microprocessor 1 is output directly to the memories 2 and 9. At the same time, address 10 is loaded into its own address counter. When the instruction byte size counter 6 is counting, the address counter 7 is updated and the address 5 is independently output to the program memory 2. The timing to update the address counter 7 is the instruction byte size counter 6.
It is similar to 8 is an address decoder connected to the address bus AB from the microprocessor 1. Program memory 2
When it is confirmed that the program memory select signal 12 has been accessed, the program memory select signal 12 is output. When the instruction byte size counter 6 is counting, the select signal 12 remains established. The data latch circuit 5 has a function of holding data output from the program memory 2. The output data 16 of the program memory 2 is held at a stable timing and continues to be held while the address strobe signal 11 from the microprocessor 1 is established. When the microprocessor 1 reads the first byte of the instruction in the program memory 2, the area at the same address as the first byte in the instruction byte size memory 9 is also read, and the byte size 17 of that instruction is stored in the counter 6. The first address of the instruction is loaded into the address carantuff. At the same time, a read cycle for the first byte is executed at the same timing as in the conventional method. FIG. 3 mainly shows the timing of reading data starting from the second byte in one instruction. Program memory data 16 with program memory 2 as the first byte (■
) is output, and when it stabilizes, it is held in the latch circuit 5 and output as data 13 ([phase] in the figure). Next, after establishing the data strobe signal 14 (■ in the figure) for this first byte, immediately (that is, before the microprocessor 1 finishes taking in the data 13 latched as described above), the command byte size counter 6 and address counter 7 to update the address 15 (■ in the same figure) that enters the program memory 2. When the data for the updated address becomes stable, it is confirmed that the read cycle for the first byte is completed, and the latch circuit 5 holds the new data 16. Microprocessor l again uses address strobe signal 1
1 (■ in the same figure) and starts a read cycle for the second byte data. At this time, the data is already complete, and the data can be taken in and the read cycle completed in the minimum time. The above read cycle continues until the counter 6 finishes counting the byte size 17 of one instruction. In this way, the time required to read the second and subsequent bytes of a multi-byte instruction can be significantly reduced. When a microprocessor reads a program from memory, it is difficult to predict which instruction will be accessed next due to branching and subroutine calls. However, it is unthinkable to read and abort an instruction consisting of multiple bytes halfway, so
This method is effective.

【Effect of the invention】

According to the present invention, the byte size of each instruction is stored in a memory area accessed at the same address as the first byte of each instruction in the program memory.
This byte size is read at the same time as the byte is read, and the program memory is accessed via a counter that increments the address by this byte size, thereby updating the address of the program memory in parallel with data fetching by the microprocessor. This makes it possible to shorten the time required to read the second and subsequent bytes of an instruction consisting of multiple bytes, allowing the microprocessor to operate at high speed and improving the processing capacity of the system.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a program read of a microprocessor as an embodiment of the present invention, Fig. 2 is a detailed block diagram mainly consisting of a memory access controller, and Fig. 3 is a timing diagram showing the timing of a program read cycle. 4 is a conventional configuration diagram corresponding to FIG. 1, FIG. 5 is a time chart showing the timing of the program read cycle in FIG. 4, and FIG. 6 is an example of arrangement of instruction data strings on the program memory. FIG. 1: Microprocessor, 2 Niprogram memory, 4:
Memory access controller, 5: data latch circuit,
6: Instruction byte size counter, 7: Address counter, 8 near address decoder, 9: Instruction byte size memory. Figure Figure Figure

Claims (1)

[Claims] 1) Each instruction constituting a program is composed of one or more bytes, and a program memory stores the program by sequentially assigning addresses to each byte, and the program memory operates while reading this program memory. A system comprising a microprocessor, a data latch circuit that latches output data of the program memory every time an address strobe signal output from the microprocessor rises and provides the data to the microprocessor as data; an instruction byte size memory that is accessed at the same time as the first byte of the instruction is accessed, the instruction byte size memory storing the byte size of each relevant instruction; and the instruction read from the instruction byte size memory upon the access of the first byte. an instruction byte size counter whose byte size is initialized and counts down each time each byte in the instruction is subsequently accessed sequentially; After a byte is output and latched in the data latch circuit, the instruction causes an operation to access one byte of the address following this one byte before the microprocessor completes reading of at least one byte. A program memory access device comprising: means for repeating until the remaining count value of a byte size counter becomes 1.