JPH02102567A - Manufacture of electronic device - Google Patents

Manufacture of electronic device

Info

Publication number
JPH02102567A
JPH02102567A JP63256701A JP25670188A JPH02102567A JP H02102567 A JPH02102567 A JP H02102567A JP 63256701 A JP63256701 A JP 63256701A JP 25670188 A JP25670188 A JP 25670188A JP H02102567 A JPH02102567 A JP H02102567A
Authority
JP
Japan
Prior art keywords
electronic device
substrate
lead frame
organic
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63256701A
Other languages
Japanese (ja)
Other versions
JP2681167B2 (en
Inventor
Shunpei Yamazaki
舜平 山崎
Kazuo Urata
一男 浦田
Naoki Hirose
直樹 広瀬
Itaru Koyama
小山 到
Shinji Imato
今任 慎二
Kazuhisa Nakashita
中下 一寿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP63256701A priority Critical patent/JP2681167B2/en
Priority to EP89118909A priority patent/EP0363936B1/en
Priority to DE68926086T priority patent/DE68926086T2/en
Priority to CN89108372A priority patent/CN1023165C/en
Priority to KR1019890014618A priority patent/KR930007519B1/en
Publication of JPH02102567A publication Critical patent/JPH02102567A/en
Application granted granted Critical
Publication of JP2681167B2 publication Critical patent/JP2681167B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PURPOSE:To prevent the cracking and blistering by a method wherein a vacuum chamber is evacuated as an electronic device is kept in it so as to enable a vapor component contained in organic material to be evacuated, the vapor component adsorbed in a substrate or a lead frame is removed, a protective film of inorganic material is formed, and the electronic device is sealed up with organic resin. CONSTITUTION:After an electronic device has been wire-bonded 39, the whole device is kept in a vacuum chamber to enable the volatile component contained in organic material to be evacuated, and the organic material attached to the substrate or lead frames 35 and 35' due to the evaporation of the volatile organic component is removed through a plasma ashing method for instance. Protective films 27 and 27' are formed on the surface of the device cleaned and improved in adhesion, and then the device is sealed up through a plastic molding 41 treatment. By this setup, the cracking and blistering can be prevented.

Description

【発明の詳細な説明】 「産業上の利用分野」 この発明は、半導体装置等の電子部品を基板またはリー
ドフレーム上に有機物を用いて固着する電子装置のワイ
ヤボンディング後、これら全体を真空容器内に保持する
ことにより有機物中の気化成分を脱気せしめるとともに
、この気化有機成分の基板またはグイ上に付着した有機
物をプラズマアッシングにより除去することにより、そ
れらの上に本来密着させるべき保護膜または有機樹脂と
の密着性を向上させんとしたものである。
Detailed Description of the Invention "Industrial Application Field" This invention relates to the wire bonding of electronic devices, in which electronic components such as semiconductor devices are fixed onto a substrate or lead frame using an organic substance, and then the entire electronic component is bonded in a vacuum container. By holding the vaporized organic components in the organic material, the vaporized components in the organic matter are degassed, and by removing the organic matter attached to the substrate or the gooey of the vaporized organic component by plasma ashing, the protective film or organic matter that should originally adhere to them is removed. This is intended to improve adhesion with resin.

そして、グイとそれに密着する保護膜との密着性を向上
させることによりクラック、ふくれ(ダイの裏面側のモ
ールド剤が半田付の際、温度上昇のためグイ近傍の水の
気化により膨れてしまう現象をいう)の発生を防がんと
したものである。
By improving the adhesion between the goo and the protective film that adheres to it, cracks and blisters (a phenomenon in which the molding agent on the back side of the die swells due to the vaporization of water near the goo due to temperature rise during soldering) It is intended to prevent the occurrence of cancer.

「従来の技術」 従来、本発明人による特許願(半導体装置作製方法、昭
和58年特許願第106452号、昭和58年6月14
日出願)が知られている。
"Prior Art" Previously, the present inventor has filed a patent application (Semiconductor device manufacturing method, Patent Application No. 106452 of 1981, June 14, 1988)
(application filed in Japan) is known.

しかし従来は第5図にその概要を示すが、リードフレー
ム(35) 、 (35’)特にICチップがダイアタ
ッチされるダイ(35’)は銅、4270イ等の金属よ
りなり、この表面(裏面)には恨ペースト(24)、そ
のはみ出た部分(24”)が設けられている。
However, in the past, as shown in Fig. 5, the lead frames (35), (35') and especially the die (35') to which the IC chip is attached are made of metal such as copper or 4270I, and the surface ( On the back side) there is grudge paste (24) and the protruding part (24").

そして電子部品をダイアタッチ(24)させる際は10
0〜200°Cの熱処理と加圧処理により、ICチップ
をグイ(35°)上に固着させていた。
And when die attaching electronic parts (24), 10
The IC chip was fixed on the Gui (35°) by heat treatment at 0 to 200°C and pressure treatment.

しかし、ダイアタッチ用の銀ペースト等の有機物中の不
要有機ガス(24”)が脱気し、基板またはリードフレ
ーム上に付着してしまう。このため、この後、ただちに
有機樹脂のモールド(41)処理を行うと、このモール
ド剤と銅または4270イとの間にきわめてはがれやす
い吸着物および低級酸化物li! (32)が残存して
しまう。
However, the unnecessary organic gas (24") in the organic substance such as silver paste for die attach is degassed and adheres to the substrate or lead frame. Therefore, immediately after this, the organic resin mold (41) When the treatment is carried out, adsorbates and lower oxides li! (32), which are extremely easy to peel off, remain between the molding agent and the copper or 4270I.

「従来の欠点」 このため、第4図に示した如く、プラスチック・モール
ド・パッケージは、一般に信頼性を低下させる水等がリ
ードフレームのダイの裏面等に集まり、半田付(一般に
260°C33〜10秒の溶融半田中への浸漬を行う)
の際、急激に気化し、その結果モールド剤が膨張する応
力が働く。そのためグイ(35″)とモールド剤(41
”)との間の密着性が悪いと、この間の界面で熱歪によ
りクラック(33)(33’)およびボイド(42)の
発生を誘発する。
``Conventional drawbacks'' For this reason, as shown in Figure 4, plastic mold packages generally have water, etc. that reduce reliability, which collects on the back side of the die of the lead frame. (dip into molten solder for 10 seconds)
At this time, the molding agent rapidly vaporizes, resulting in stress that causes the molding agent to expand. Therefore, goui (35″) and molding agent (41″)
If the adhesion between them is poor, cracks (33) (33') and voids (42) will be generated at the interface between them due to thermal strain.

これまでは、絶縁性基板上にリードが形成された基板ま
たは金属リードフレームのダイ(35’) 上に電子部
品(以下チップともいう)を固着させていた。この固着
材用にエポキシ系の有機樹脂またはこれと銀とが混合し
た銀ペースト等の有機物を含有する固着材(24) 、
 (24”)を用いた。この固着材により電子部品を基
板またはフレーム上に固着させる際に、初期に溶融状態
であった有機物を化学反応または熱化学反応を伴わせて
固化する。これは安価かつ大量生産にはきわめて優れた
ものである。しかしこの有機物固着材(24) 、 (
24”)は大気中の室温の状態、ないし加熱(100〜
300 ’C)を行うと、この固着後の有機気化成分が
残存する。この残存物は徐々に気化し、基板またはダイ
の表面上に吸着するため、この後に形成する保護膜また
はモールド樹脂との密着性をも害してしまう。
Up to now, electronic components (hereinafter also referred to as chips) have been fixed on a die (35') of a metal lead frame or a substrate on which leads are formed on an insulating substrate. A fixing material (24) containing an organic substance such as an epoxy-based organic resin or a silver paste mixed with silver for this fixing material;
(24") was used. When fixing electronic components onto a board or frame using this adhesive, the organic matter that was initially in a molten state is solidified through a chemical reaction or thermochemical reaction. This is an inexpensive material. And it is extremely excellent for mass production.However, this organic matter fixing material (24), (
24") is at room temperature in the atmosphere or heated (100~
300'C), this fixed organic vaporized component remains. Since this residual material gradually vaporizes and adsorbs onto the surface of the substrate or die, it also impairs the adhesion with the protective film or molding resin that will be formed later.

「発明の構成」 本発明は、かかる従来のDIPまたはフラットバック等
のモールド封止された半導体集積回路または複数の電子
部品が基体上に固着されたハイブリッドIC等の電子装
置における信頼性の低下を防ぐためになされたものであ
る。銀ペースト等で固着した電子装置に対しては、より
真空にすることにより、脱気する有機物がこれら基板ま
たは金属のリードフレーム上に吸着する。しかし本発明
は、かかる吸着有機物をN20.0□または酸素のアル
ゴンとの混合気体等によりプラズマアッシング処理を行
うことにより除去し、さらに好ましくは、きわめて吸湿
しやすいモールド樹脂と金属との間に耐湿性の窒化珪素
等の無機材料の保護膜を形成させることを特徴としてい
る。
``Structure of the Invention'' The present invention is directed to reducing reliability in electronic devices such as conventional DIP or flat-back molded semiconductor integrated circuits or hybrid ICs in which a plurality of electronic components are fixed on a substrate. This was done to prevent it. For electronic devices fixed with silver paste or the like, by applying a higher vacuum, the degassed organic substances will be adsorbed onto these substrates or metal lead frames. However, in the present invention, such adsorbed organic substances are removed by plasma ashing treatment using N20.0□ or a mixed gas of oxygen and argon, and more preferably, moisture-proofing is performed between the mold resin and the metal, which easily absorb moisture. It is characterized by forming a protective film of an inorganic material such as silicon nitride.

リードフレームと保護膜との界面での炭素の濃度は2 
X 10zocm−’以下好ましくは7 XIO”cm
−3以下とすることにより、炭素有機物の除去と密着性
の向上を計ったものである。
The carbon concentration at the interface between the lead frame and the protective film is 2
X 10zocm-' or less, preferably 7 XIO"cm
-3 or less is intended to remove carbon organic matter and improve adhesion.

このため、電子装置をターボ分子ポンプで真空排気する
真空容器中に保持することにより、脱気するとともに、
排気処理中のロータリーポンプから逆流するオイルミス
トをも防ぎ、高倍転性を成就するものである。
For this reason, by holding the electronic device in a vacuum container that is evacuated with a turbo molecular pump, it is degassed and
This also prevents oil mist from flowing back from the rotary pump during exhaust processing, achieving high rotation performance.

さらに必要に応じて、この後同じ反応炉で同時に外部加
熱をすることなく、好ましくは室温(プラズマによる自
己発熱は若干ある)で、プラズマ気相法によりこの金属
表面を含めてこれら全ての表面を窒化珪素等の保護膜で
覆ってコーティングを施し、その後にプラスチック・モ
ールド処理による封止を行うことを特徴としている。
Furthermore, if necessary, all these surfaces, including this metal surface, are then treated in the same reactor without external heating at the same time, preferably at room temperature (there is some self-heating due to the plasma), using a plasma vapor phase method. It is characterized by being coated with a protective film such as silicon nitride, and then sealed by plastic molding.

第1図は本発明構造のプラスチックDIP(デュアルイ
ンライン型パッケイジ)またはフラットバックパッケイ
ジの縦断面図を示す。
FIG. 1 shows a longitudinal sectional view of a plastic DIP (dual in-line package) or flat back package constructed according to the present invention.

図面において、リードフレームのダイ(35’)に有機
物を含有する銀ペースト(24)等で密着させたチップ
(28)を有する。このチップアタッチの際に固着させ
るための有機物の不要物が(24″)として側周辺には
みだしている。チップ(28)と、このチップのアルミ
ニューム・パッド(38)とステム(35)との間に、
金線(39)のワイヤボンドがなされている。
In the drawing, a chip (28) is attached to a die (35') of a lead frame with a silver paste (24) containing an organic substance or the like. Unwanted organic matter to be fixed when attaching this chip protrudes around the side as (24"). Between the chip (28), the aluminum pad (38) of this chip, and the stem (35). Between,
A wire bond of gold wire (39) is made.

本発明は、このチップ(28)表面、パッド(38)表
面、ワイヤ(39)表面およびダイ(35’)の裏面に
対し、有機物(24) 、 (24’)中の不要気体成
分を脱気させ、それらが前記した表面に不本意にも吸着
してしまうが、これを酸化物気体を含有させた雰囲気で
プラズマアッシングを施すことにより酸化して炭酸ガス
と水とに変成して気化除去する。その後この表面に吸着
している残存する酸化物、例えば低級酸化物、炭酸ガス
、水等をアルゴン、窒素またはこれらに水素を添加した
気体でプラズマアッシングを行い脱気する。さらにこれ
ら清浄になって密着性が向上する表面上に窒化珪素等の
保護膜(27) 、 (27°)、(27°’)、(2
7”″)を形成する。
The present invention degasses unnecessary gas components in the organic substances (24) and (24') from the surface of the chip (28), the surface of the pad (38), the surface of the wire (39), and the back surface of the die (35'). However, by performing plasma ashing in an atmosphere containing oxide gas, they are oxidized and transformed into carbon dioxide gas and water, which are vaporized and removed. . Thereafter, remaining oxides adsorbed on this surface, such as lower oxides, carbon dioxide gas, water, etc., are degassed by plasma ashing with argon, nitrogen, or a gas obtained by adding hydrogen to these. Furthermore, protective films such as silicon nitride (27), (27°), (27°'), (2
7"").

第2図は、本発明の装置の概要を示す。FIG. 2 shows an overview of the device of the invention.

チップがフレームにボンディングされた構造の基板およ
びそれを複数個集合させた基体(2)(基板および基体
をまとめて基体とも以下では略記する)を複数配設させ
ている。プラズマ処理方法により不要の半固着した有機
物を酸化物気体を用いたプラズマアッシングにより除去
、さらに低級酸化物のアルゴン、窒素またはこれらと水
素とが添加された気体によるプラズマクリーニングによ
り除去する。同一反応炉または連結したマルチチャンバ
方式で、大気にこれらが触れて水等が吸着しないように
しつつ同一反応炉内で反応性気体を切り換えることによ
りジシランC3iJs)  と窒素(N2)とを用い、
プラズマCVD法による窒化珪素膜のコーティングを行
う。
A plurality of substrates having a structure in which a chip is bonded to a frame and a plurality of base bodies (2) in which a plurality of such substrates are assembled (hereinafter, the substrates and the base bodies are collectively referred to as the base body) are provided. By the plasma processing method, unnecessary semi-fixed organic substances are removed by plasma ashing using oxide gas, and further by plasma cleaning using lower oxides such as argon, nitrogen, or a gas to which these and hydrogen are added. Using disilane (C3iJs) and nitrogen (N2) in the same reactor or in a connected multi-chamber system, by switching the reactive gas in the same reactor while preventing them from coming into contact with the atmosphere and adsorbing water, etc.
A silicon nitride film is coated by plasma CVD.

第・2図において、反応系(6)、ドーピング系(5)
を有している。
In Figure 2, reaction system (6), doping system (5)
have.

反応系は、真空容器(以下反応室ともいう)(1)と予
備室(7)とを有し、ゲート弁(9)、(9’)とを有
している。反応室(1)は内側に供給側フード(13)
を有し、入口側(3)よりの反応性気体をフード(14
)のノズル(13)より下方向に吹き出し、排気せしめ
ている。
The reaction system includes a vacuum container (hereinafter also referred to as reaction chamber) (1), a preliminary chamber (7), and gate valves (9) and (9'). The reaction chamber (1) has a supply hood (13) inside.
, and the reactive gas from the inlet side (3) is passed through the hood (14
) is blown downward from the nozzle (13) and exhausted.

第2図における反応性気体は、フード(13)より枠構
造のホルダ(40)の内側およびフード(13“)によ
り囲まれた内側にてターボ分子ボング(20)で5×1
0−コ〜I ×10−’torr好ましくはl×10−
’〜lX10−8torrに5〜30分保持することに
よって、第1図における固着剤中の不要有機物ガスを真
空中に脱気し、かつ基板、フレーム等上への吸着を防い
だ。
In FIG. 2, the reactive gas is supplied to the turbo molecular bong (20) in a 5×1 manner from the hood (13) to the inside of the frame-structured holder (40) and the inside surrounded by the hood (13'').
0-co~I x 10-'torr preferably l x 10-
By holding the sample at a temperature of 1.times.10@-8 torr for 5 to 30 minutes, unnecessary organic gases in the fixing agent in FIG. 1 were degassed into vacuum, and adsorption onto the substrate, frame, etc. was prevented.

本発明のプラズマアッシング処理方法は酸素(0□)。The plasma ashing treatment method of the present invention uses oxygen (0□).

亜酸化窒素(NZO)を(19)より供給して用い、有
機物を炭酸ガスと水とに分解気体化して除去している。
Nitrous oxide (NZO) is supplied from (19) and used to decompose and gasify organic matter into carbon dioxide gas and water and remove it.

本発明のプラズマクリーニング処理方法は、アルゴン、
ネオン、ヘリウム、クリプトン等の不活性物気体を(1
5)より、または水素を(18)より、窒素またはアン
モニアを(16)より供給して用いてもよい。しかし質
量が大きくかつ比較的安価でプラズマ化しやすい気体で
あるアルゴンが好ましい。
The plasma cleaning treatment method of the present invention includes argon,
Inert gases such as neon, helium, krypton, etc. (1
5), hydrogen may be supplied from (18), and nitrogen or ammonia may be supplied from (16). However, argon is preferable because it has a large mass, is relatively inexpensive, and is a gas that easily turns into plasma.

この真空中に電子装置を配設して、有機物中の不要気体
成分の脱気、電子装置表面上での有機気体成分の不本意
にして再付着した不要有機物成分の除去用のプラズマア
ッシング処理およびその後の酸化物の除去用のプラズマ
クリーニング、次に無機材料の保護膜形成を電子装置を
外気に触れさせることなく第2図の如きプラズマ処理装
置を用いて行った。さらにこの上面にプラスチックモー
ルド(41)を行った。
Electronic equipment is placed in this vacuum, and plasma ashing processing is performed to degas unnecessary gaseous components in the organic matter, remove unnecessary organic components that have been inadvertently redeposited on the surface of the electronic equipment, and Thereafter, plasma cleaning for removing oxides and formation of a protective film of an inorganic material were performed using a plasma processing apparatus as shown in FIG. 2 without exposing the electronic device to the outside air. Further, a plastic mold (41) was formed on this upper surface.

この窒化珪素膜の如き保護膜は室温において、珪化物気
体のジシランを(17)より、さらにアンモニアまたは
窒素を(16)より供給してプラズマ反応炉(1)に導
入し、そこに電磁エネルギを供給するいわゆるプラズマ
気相法により形成せしめた。
This protective film such as a silicon nitride film is prepared by introducing disilane, a silicide gas, from (17) and further ammonia or nitrogen from (16) into the plasma reactor (1) at room temperature, and then applying electromagnetic energy thereto. It was formed by a so-called plasma vapor phase method.

かくの如くして、窒化珪素膜の如き劣化防止用保護膜を
300〜5000人、一般には約1000人の厚さに形
成した後、公知のインジェクション・モールド法により
、有機樹脂例えばエポキシ(例えば、410B)モール
ド法により注入・封止させた。さらにフレームをリード
部(37)にて曲げ、かつタイバーを切断する。さらに
リード部を酸洗いした後、リードにハンダメツキを行っ
た。
After forming a protective film for preventing deterioration such as a silicon nitride film to a thickness of 300 to 5,000 layers, generally about 1,000 layers, an organic resin such as epoxy (for example, 410B) Injected and sealed by molding method. Furthermore, the frame is bent at the lead portion (37) and the tie bar is cut. Furthermore, after pickling the lead portion, the lead was solder-plated.

この反応容器を用い、プラズマ反応をさせ、基板または
基体(2)上での不要有機物、半有機物、低級酸化物の
除去および保護膜形成を行った。プラズマアッシング処
理、プラズマクリーニング処理またはプラズマCVD反
応後は排出側フード(14”)のノズル(13’)より
排気口(4)を経てバルブ(21)。
Using this reaction vessel, a plasma reaction was carried out to remove unnecessary organic substances, semi-organic substances, and lower oxides and to form a protective film on the substrate or substrate (2). After plasma ashing treatment, plasma cleaning treatment or plasma CVD reaction, the valve (21) is passed from the nozzle (13') of the exhaust side hood (14'') through the exhaust port (4).

ターボ分子ポンプ(20)さらにロータリー型真空ポン
プまたはドライ真空ポンプ(23)に至る。
The turbomolecular pump (20) further leads to a rotary vacuum pump or dry vacuum pump (23).

それぞれの高周波電源(10−1) 、 (10−2)
即ち(10)よりの電磁エネルギは、マツチングボック
ス(251) 、 (25−2)即ち(25)をへて、
1〜500MHz、例えば13.56 MHzの周波数
を上下間の一対の同じ大きさの網状電極(11)、 (
11’)に加え、それぞれの電極(11)、(11°)
に供給される。電磁エネルギの位相は180 ’±30
°以内または0°±30°以内に位相調整器(26)に
より制御される。電源(10−1) 、 (10−2)
の他端は接地させている。また周辺の枠構造のホルダ(
40)は導体の場合は接地レベル(22)とし、また絶
縁体であってもよい。
Respective high frequency power supplies (10-1) and (10-2)
That is, the electromagnetic energy from (10) passes through the matching box (251), (25-2), that is, (25),
A pair of mesh electrodes (11) of the same size between the upper and lower sides, (
11'), as well as the respective electrodes (11), (11°)
supplied to The phase of electromagnetic energy is 180'±30
or within 0°±30° controlled by the phase adjuster (26). Power supply (10-1), (10-2)
The other end is grounded. There is also a holder with a surrounding frame structure (
40) is a ground level (22) if it is a conductor, or it may be an insulator.

反応性気体は、一対の電極(11)、 (12)により
供給された高周波エネルギにより励起させている。
The reactive gas is excited by high frequency energy supplied by a pair of electrodes (11) and (12).

また同一反応炉内における真空処理による脱気、プラズ
マ処理およびプラズマCVD法において、被形成体(2
)(以下基体(2)という)はサポータ(40′)上に
配設された枠構造のホルダ(40)内に一対の電極間の
電界の方向に平行に、さらに、いずれの電極(11)、
(12)からも離間させている。複数の基体(2)は互
いに一定の間隔(2〜13cm例えば6cm)または概
略一定の間隔を有して配設されている。この多数の基体
(2)は、グロー放電により作られるプラズマ中の陽光
社内に配設される。
In addition, in deaeration by vacuum treatment, plasma treatment, and plasma CVD methods in the same reactor, the object to be formed (2
) (hereinafter referred to as the base (2)) is placed in a frame-structured holder (40) disposed on a supporter (40') parallel to the direction of the electric field between the pair of electrodes, and furthermore, either electrode (11). ,
It is also spaced apart from (12). The plurality of base bodies (2) are arranged at a constant interval (2 to 13 cm, for example 6 cm) or approximately at a constant interval from each other. This large number of substrates (2) is placed inside the sunlight in the plasma created by glow discharge.

この基体の要部を第3図(C)に示す。The main part of this base body is shown in FIG. 3(C).

第3図(八)は、基体(2)においてステム(35)。Figure 3 (8) shows the stem (35) in the base (2).

ダイ(35“)を複数個一体化したリードフレーム上(
45)に、半導体装置(28)がボンディングされた電
子装置(29)を5〜25ケ、ユニット化した基体(4
5)を有する。
On a lead frame that integrates multiple dies (35") (
45), and a base (4) in which 5 to 25 electronic devices (29) to which semiconductor devices (28) are bonded are unitized.
5).

複数の半導体チップがボンディングされた1本のリード
フレーム(45)における1つのリードフレーム(基板
)を第3図(B)に示す。
FIG. 3B shows one lead frame (substrate) in one lead frame (45) to which a plurality of semiconductor chips are bonded.

図面ではリードを左側のみ簡単のため示す。このA−A
’での縦断面図を第3図(C)の(29)に示す。
In the drawing, only the left side of the lead is shown for simplicity. This A-A
A vertical cross-sectional view at ' is shown in (29) of FIG. 3(C).

第3図(C)において、リードフレーム(35) 、ダ
イ(35’)、半導体チップ(2B)、金属線(39)
よりなる基板(45)をさらに5〜300本集め、ジグ
(44)により一体化し、基体(2)として構成させて
いる。この基体(2)が第2図における基体(2)に対
応している。これをさらに5〜50枚(図面では7枚)
陽光柱内に第2図では配設している。
In FIG. 3(C), a lead frame (35), a die (35'), a semiconductor chip (2B), a metal wire (39)
Further, 5 to 300 substrates (45) made of the above are collected and integrated with a jig (44) to form the base body (2). This base body (2) corresponds to the base body (2) in FIG. Add 5 to 50 more sheets (7 sheets in the drawing)
In Figure 2, it is placed inside the positive column.

第2図に示すごとき本発明方法における有機物の脱気方
法は、室温の条件下での5X10−”〜1×10−8t
orrに保持することに従った。
The method of degassing organic matter in the method of the present invention as shown in FIG. 2 is as follows:
Followed to hold at orr.

本発明において、この高真空脱気の後、反応容器内圧力
を中真空の5X10−”〜5 X 10− ’ tor
r例えばI ×10−’〜I ×10−’torrにお
いて、酸素プラズマを発生させ、プラズマアッシングを
行った。さらにその後プラズマクリーニングを同一圧力
で反応性気体を加えて施し、保護膜としての窒化珪素膜
を形成するに際し、外部より加熱をしなくても充分に緻
密な絶縁膜を作ることができる。
In the present invention, after this high vacuum degassing, the internal pressure of the reaction vessel is reduced to a medium vacuum of 5X10-'' to 5X10-' tor.
For example, oxygen plasma was generated at I x 10-' to I x 10-' torr, and plasma ashing was performed. Further, after that, plasma cleaning is performed by adding a reactive gas at the same pressure, and when forming a silicon nitride film as a protective film, a sufficiently dense insulating film can be formed without external heating.

そのプロセス上の1例を以下に示す。An example of this process is shown below.

「実施例1」 第2図のプラズマ処理装置およびプラズマCVD装置に
おいて、ドーピング系(5)は珪化物気体であるジシラ
ン(SiJa)を(17)より、また窒化物気体である
アンモニアまたは窒素を(16)より、プラズマ処理用
の非生成物気体であるアルゴンを(15)より、水素を
(18)より、酸素またはN!0を(19)より供給し
ている。それらは流量計(8)、バルブ(7)により制
御されている。
"Example 1" In the plasma processing apparatus and plasma CVD apparatus shown in FIG. 2, the doping system (5) uses disilane (SiJa), which is a silicide gas, from (17), and ammonia or nitrogen, which is a nitride gas, from (17). From (16), argon, which is a non-product gas for plasma processing, is added from (15), hydrogen from (18), oxygen or N! 0 is supplied from (19). They are controlled by a flow meter (8) and a valve (7).

例えば、大量生産のため基板温度は外部加熱を特に積極
的に行わない室温(プラズマによる自己加熱を含む)と
した。
For example, for mass production, the substrate temperature was set to room temperature (including self-heating by plasma) without any active external heating.

まず反応空間(1)をI ×10−’〜I ×10−’
torrに5〜15分保持し、その後、5 ×10−8
torrにN、0を導入し、電磁エネルギを与え、プラ
ズマ化し基体(2)の表面の有機吸着物のプラズマアッ
シング処理を5〜15分間行った。即ちこれら酸化物気
体に対し、13.56MHzの周波数によりIK−の出
力を一対の電極(11)、 (11°)に電源(10)
、マツチングボックス(25)をへて供給してプラズマ
化した。するとこのダイの裏面に付着しているオイルミ
スト、不要有機物および水分、低級酸化物を除去し、新
たな金属面を露呈させることができ、成膜する被膜の密
着性を向上させることができた。
First, the reaction space (1) is I x 10-' ~ I x 10-'
torr for 5-15 minutes, then 5 x 10-8
N,0 was introduced into the torr, electromagnetic energy was applied, it turned into plasma, and the organic adsorbate on the surface of the substrate (2) was subjected to a plasma ashing process for 5 to 15 minutes. That is, for these oxide gases, the output of IK- at a frequency of 13.56 MHz is applied to a pair of electrodes (11), (11°) and a power source (10).
, and a matching box (25) to generate plasma. This removed the oil mist, unnecessary organic matter, moisture, and lower oxides adhering to the back side of the die, exposing a new metal surface and improving the adhesion of the film being formed. .

さらにこの後、好ましくはアルゴンに置換し、ひきつづ
きプラズマ処理を行った。このアルゴン中に水素を5〜
30体積%添加してもよい。そして吸着している酸化物
を除去した。
Furthermore, after this, the atmosphere was preferably replaced with argon, and then plasma treatment was performed. Hydrogen in this argon is 5~
It may be added in an amount of 30% by volume. Then, the adsorbed oxides were removed.

次にこのプラズマ処理がなされた被形成面上に保護膜を
同一反応炉で大気にふれさせることなく形成する。即ち
窒化珪素膜を形成する場合、反応性気体は例えば、5i
zHa/Nz=115とした。これら反応性気体に対し
、13.56MHzの周波数によりIKWの出力を一対
の電極(11) 、(11’)(11’)に供給した。
Next, a protective film is formed on the plasma-treated surface in the same reactor without exposing it to the atmosphere. That is, when forming a silicon nitride film, the reactive gas is, for example, 5i
zHa/Nz=115. For these reactive gases, IKW output was supplied to a pair of electrodes (11), (11') and (11') at a frequency of 13.56 MHz.

かくして平均200〜2000人(1000人±200
人)に約10分(平均速度3人/秒)の被膜形成を行っ
た。
Thus, on average 200 to 2000 people (1000 ± 200
Film formation was carried out for about 10 minutes (average speed of 3 people/second).

窒化珪素膜はその絶縁耐圧7 X 10”V/cm以上
を有し、比抵抗は2X10”ΩcIllであった。赤外
線吸収スペクトルでは864cm−’の5t−N結合の
吸収ピークを有し、屈折率は2.0であった。
The silicon nitride film had a dielectric strength voltage of 7×10”V/cm or more, and a specific resistance of 2×10”ΩcIll. The infrared absorption spectrum had an absorption peak of 5t-N bond at 864 cm-', and the refractive index was 2.0.

5χNaC1で溶解させた塩水中(95°C)に保有し
たところ、20時間を経ても何らの劣化も見られなかっ
た。このため、本発明の劣化防止用保護膜として用い得
ることを証明することができた。
When kept in saline solution (95°C) in which 5χNaCl was dissolved, no deterioration was observed even after 20 hours. Therefore, it was possible to prove that the film can be used as a protective film for preventing deterioration of the present invention.

かかる本発明方法で作られた電子装置に対し、85°C
/85χ(相対温度)で1000時間放置して、その後
、半田付けを260°Cで5秒行った。しかしこのモー
ルドには何らのクラックもまたふくれも発生しなかった
For electronic devices manufactured by the method of the present invention, 85°C
/85χ (relative temperature) for 1000 hours, and then soldering was performed at 260°C for 5 seconds. However, this mold did not develop any cracks or blisters.

さらに85°C/85!で300ケ放置しプラスチック
モールドに吸水させ、その後260°C13秒の加熱を
行う条件の信鎖性テストを行った。
Another 85°C/85! A reliability test was conducted under the following conditions: 300 pieces were left in the plastic mold to absorb water, and then heated at 260°C for 13 seconds.

その−例を以下の表に示す。Examples are shown in the table below.

■ プラズマアッシング処理(分) ■ プラズマクリーニング処理(15分)クランク 内
部クラック有の不良品/母数その結果、プラズマアッシ
ング処理、プラズマクリーニング処理および保護膜の形
成を行うと100ケ中不良品零となり、すべて良品(漱
1〜5)であった。またプラズマアッシング処理と保護
膜形成の工程でも3/100と不良品はきわめて少なか
った(Nα6〜10)。しかしプラズマアッシング処理
がなく、かつ保護膜がない通常の市販品と同じ品質の場
合は、20ケ中20ケが不良品(No、15)であった
。また保護膜があってもアッシング処理がないと一部に
不良品が発生してしまった(No、11〜12)。
■ Plasma ashing treatment (minutes) ■ Plasma cleaning treatment (15 minutes) Crank Defective products with internal cracks/parameter As a result, after plasma ashing treatment, plasma cleaning treatment, and protective film formation, there were 0 defective products out of 100. , all were good products (Sob 1 to 5). In addition, the number of defective products in the plasma ashing process and protective film formation process was 3/100, which was extremely low (Nα6 to 10). However, when the quality was the same as a normal commercially available product without plasma ashing treatment and without a protective film, 20 out of 20 products were defective (No. 15). Furthermore, even with the protective film, some defective products occurred without ashing treatment (Nos. 11 to 12).

また保護膜がなくてもプラズマアッシング処理およびク
リーニング処理が行われる場合は、1ケの不良のみであ
った( k13)。
Furthermore, when plasma ashing and cleaning were performed without a protective film, there was only one defect (k13).

第4図は本発明の実験結果の原因の裏付けをとるため、
SIMS(二次イオン質量分析機)で深さ方向の分布と
イオン強度との関係を測定評価したものである。
FIG. 4 shows the following steps to confirm the cause of the experimental results of the present invention.
The relationship between the distribution in the depth direction and the ion intensity was measured and evaluated using SIMS (secondary ion mass spectrometer).

第4図(A)はプラズマアッシング、プラズマクリーニ
ングおよび保護膜として窒化珪素膜を形成したもので、
表1におけるNα5に対応する。第4図(B)はプラズ
マアッシングもプラズマクリーニングも共に何ら行って
おらず、かつ窒化珪素膜を作って表1におけるNα12
に対応する。第4図(C)はプラズマアッシングはやっ
ているが、プラズマクリーニングを行っていない表1に
おけるNα10に対応する0図面において、領域(55
)は2000人と厚めの深さ分布をとりやすい窒化珪素
が形成されている領域を示す。また、4270イのリー
ドフレームの領域(57)、界面(56)を示す。この
深さ方向の分布は第1図における窒化珪素膜(27”)
の(59)方向の深さ方向に対応している。第4図にお
いて、その縦軸はイオン強度を示す対数目盛りである。
Figure 4(A) shows plasma ashing, plasma cleaning, and formation of a silicon nitride film as a protective film.
Corresponds to Nα5 in Table 1. FIG. 4(B) shows that neither plasma ashing nor plasma cleaning was performed, and a silicon nitride film was formed to reduce the Nα12 in Table 1.
corresponds to FIG. 4(C) shows an area (55
) indicates a region where silicon nitride is formed, which tends to have a thicker depth distribution. The area (57) and interface (56) of the 4270-I lead frame are also shown. This distribution in the depth direction is similar to that of the silicon nitride film (27”) in Figure 1.
This corresponds to the depth direction of the (59) direction. In FIG. 4, the vertical axis is a logarithmic scale indicating ion intensity.

また(50)は炭素濃度を示し、窒化珪素中の炭素濃度
(50−2)、界面の炭素濃度(50−1)、  リー
ドフレム中の炭素濃度(50−3)を示す。珪素の濃度
分布は曲線(51)で示され、窒素の濃度分布は曲線(
52)で示され、酸素の濃度は曲線(53)で示されて
いる。
Further, (50) indicates the carbon concentration, and indicates the carbon concentration in silicon nitride (50-2), the carbon concentration at the interface (50-1), and the carbon concentration in the lead frame (50-3). The silicon concentration distribution is shown by the curve (51), and the nitrogen concentration distribution is shown by the curve (51).
52), and the concentration of oxygen is shown by the curve (53).

膜中、界面、リードフレーム中に対応して(53−1)
Corresponding to the inside of the film, interface, and lead frame (53-1)
.

(53−2) 、 (53−3)として示されている。(53-2) and (53-3).

プラズマアッシングを行わないと第4図(B)に示す如
く、炭素(50)が界面(50−1)で多く、その濃度
もサンプルのバラツキはあるが、3〜20X10”cm
−3ときわめて高密度である。また結果として窒化珪素
中にもその炭素濃度は比較的多い(50−2)。
If plasma ashing is not performed, as shown in Figure 4 (B), carbon (50) is abundant at the interface (50-1), and its concentration varies from sample to sample, but it is 3 to 20 x 10" cm.
-3, which is extremely high density. Furthermore, as a result, the carbon concentration in silicon nitride is relatively high (50-2).

成膜されているものは窒化珪素であることが(7)。The deposited film is silicon nitride (7).

(52)よりわかる。This can be seen from (52).

またプラズマアッシングをやるがプラズマアッシングを
行わず被膜形成をすると、第4図(C)に示す如く、界
面(56)には酸素(53−2)が残存し、その濃度は
3〜l0XIO”cm−’と多い。さらにその結果、膜
中にも酸素は多量に混入してしまっている(53−1)
。このため成膜した膜は窒化珪素のつもりでも酸素が多
く入って、むしろオキシナイトライドであると推定され
る。
In addition, if plasma ashing is performed but a film is formed without plasma ashing, oxygen (53-2) remains at the interface (56) as shown in Figure 4 (C), and its concentration is 3 to 10XIO"cm. -'. Furthermore, as a result, a large amount of oxygen is mixed into the film (53-1)
. For this reason, the formed film contains a large amount of oxygen even though it is intended to be silicon nitride, and it is presumed that it is actually oxynitride.

この場合でも、炭素は界面(50−1)、膜中(50−
2)ともに減少し、プラズマアッシングの効果は十分で
ある。
Even in this case, carbon is present at the interface (50-1) and in the film (50-1).
2) both decrease, and the effect of plasma ashing is sufficient.

このピーク値(50−1)はサンプルによってばらつい
たが、2 XIO”cn+−’以下であり、−船釣には
1〜7X10”ケ/cts3と低い濃度であった。この
ことが有機物が界面に残存または実質的に残存していな
いことの間接的な証明になっている。
This peak value (50-1) varied depending on the sample, but was less than 2XIO"cn+-', and was a low concentration of 1 to 7X10"cn/cts3 for boat fishing. This is indirect proof that no organic matter remains or substantially does not remain at the interface.

また第4図(A)は本発明のプラズマアッシングおよび
プラズマクリーニングを行ったものである。
Moreover, FIG. 4(A) shows the result of plasma ashing and plasma cleaning according to the present invention.

すると炭素濃度も界面(50−1)、膜中(50−2)
において十分小さく、2 XIO”cm−’以下好まし
くは7XIO”cm−’以下であった。同様に酸素濃度
も2×1020ケ/c−3以下の濃度(53−2)であ
った。さらにプラズマクリーニングを行い、吸着存在し
ている酸素を除去したため、窒化珪素膜中(53−2)
においてはその濃度を十分小さくすることができた。
Then, the carbon concentration is also at the interface (50-1) and in the film (50-2).
It was sufficiently small, less than 2XIO"cm-', preferably less than 7XIO"cm-'. Similarly, the oxygen concentration was less than 2 x 1020 Ke/c-3 (53-2). Furthermore, plasma cleaning was performed to remove adsorbed oxygen, so that the silicon nitride film (53-2)
In this case, we were able to reduce the concentration sufficiently.

その結果、成膜されたものは窒化珪素であることがわか
り、ひいては他の信軌性、例えば耐ナトリウム性で良好
なデータを期待できた根拠となっている。
As a result, it was found that the deposited film was silicon nitride, which was the basis for expecting good data on other reliability properties, such as sodium resistance.

これらのSIMSのデータより、本発明の酸化物気体の
プラズマアッシング工程は、ダイアタッチ剤がエポキシ
等の有機物を用いる時きわめて有効であると判明できた
。その結果は表1からも明らかである。
From these SIMS data, it was found that the oxide gas plasma ashing process of the present invention is extremely effective when an organic material such as epoxy is used as the die attach agent. The results are clear from Table 1.

一般にアルミニューム・パッドの表面はモールド材と密
着性が悪い。しかし本発明の如くこのアルミパッド(第
1図(3B) )上に保護膜を形成すると、ここでの密
着性が向上し、加えて窒化珪素膜は水、塩素に対するブ
ロッキング効果(マスク効果)が大きい。このため、本
発明構造の電子装置(例えば半導体集積回路)において
は、PCT  (プレッシャー・クツカー・テスト) 
2atoa+、120°Cの条件下で20時間おいても
、まったく不良が観察されず、従来のICチップが50
〜100フイツトの不良率を有していたが、5〜10フ
イツトにまでその不良率を下げることが可能になった。
Generally, the surface of an aluminum pad has poor adhesion to the molding material. However, when a protective film is formed on this aluminum pad (Fig. 1 (3B)) as in the present invention, the adhesion here is improved, and in addition, the silicon nitride film has a blocking effect (mask effect) against water and chlorine. big. Therefore, in electronic devices (for example, semiconductor integrated circuits) having the structure of the present invention, PCT (Pressure Cutcher Test)
Even after 20 hours at 2atoa+ and 120°C, no defects were observed, and the conventional IC chip
The defective rate used to be ~100 feet, but it has now become possible to lower that defective rate to 5 to 10 feet.

なお本発明においては、高真空、下に保持すること、お
よびプラズマアッシング処理において、電気エネルギの
みならず、300nm以下の紫外光を同時に加えた光エ
ネルギを用い有機物除去用のフォトクリーニング法を併
用することは有効である。
In the present invention, the material is kept under a high vacuum, and in the plasma ashing process, not only electric energy but also light energy with ultraviolet light of 300 nm or less is used in combination with a photo cleaning method for removing organic substances. That is valid.

「効果」 本発明において、酸化物気体を用いたプラズマアッシン
グ処理およびそれに引き続くプラズマクリーニング処理
を室温で行ったため、ダイにチップをアタッチした時に
用いた有機樹脂を加熱して劣化させることがない。また
加熱に必要な電力、時間がいらず、生産性に優れている
。加えて、ダイの裏面に対しても、吸着有機物、低級酸
化物を除去しているため、窒化珪素膜またはモールド剤
である有機樹脂のリードフレームとの密着性を向上させ
ることができた。また保護膜を形成すると、長期間たっ
ても、有機樹脂中の水分、塩素とダイの金属との間で反
応を起こして低級酸化物ができ、信転性を低下させると
いう欠点がない。そして裏面からの水分の侵入を防ぐこ
とができる。またこの電子装置のPCBへの半導体によ
る装着の際、従来例に示す如く、モールド材が加熱によ
り膨れてしまうことを防ぐことができた。
"Effects" In the present invention, since the plasma ashing treatment using oxide gas and the subsequent plasma cleaning treatment are performed at room temperature, the organic resin used when attaching the chip to the die is not heated and deteriorated. It also requires no electricity or time for heating, and is highly productive. In addition, since adsorbed organic substances and lower oxides were removed from the back surface of the die, it was possible to improve the adhesion of the silicon nitride film or the organic resin used as the molding agent to the lead frame. Further, when a protective film is formed, there is no problem that even after a long period of time, water and chlorine in the organic resin react with the metal of the die to form lower oxides, which deteriorate reliability. This also prevents moisture from entering from the back side. Furthermore, when mounting this electronic device on a PCB using a semiconductor, it was possible to prevent the molding material from swelling due to heating, as shown in the conventional example.

本発明における保護膜は窒化珪素膜とした。しかしこれ
をDLC(ダイヤモンド・ライク・カーボン)膜、酸化
珪素膜、その他の絶縁膜の単層または多層膜であっても
よい。
The protective film in the present invention was a silicon nitride film. However, this may be a single layer or multilayer film of a DLC (diamond-like carbon) film, a silicon oxide film, or other insulating films.

さらに本発明において、電子部品チップは半導体素子と
して示したが、その他、絶縁基板上に金属導体が設けら
れ、これらに抵抗、コンデンサを固着させたハイブリッ
ドICであってもよく、ボンディングもワイヤボンディ
ングのみならずフリップチップボンディング、ハンダバ
ンプボンディングでもよい。
Further, in the present invention, the electronic component chip is shown as a semiconductor element, but it may also be a hybrid IC in which a metal conductor is provided on an insulating substrate and a resistor and a capacitor are fixed to these, and bonding can be performed only by wire bonding. Alternatively, flip chip bonding or solder bump bonding may be used.

本発明において、チップの大きさが太き(なって、ダイ
を用いることなしにモールドする場合がある。しかしそ
の場合も基体としての基板またはリードフレーム、チッ
プのすべてを覆って保護膜を設けることは有効である。
In the present invention, there are cases where the chip is large in size and is molded without using a die. However, even in that case, it is necessary to provide a protective film covering all of the substrate or lead frame as a base and the chip. is valid.

上述した説明においては、リードフレーム上に半導体チ
ップを載置した場合について述べているが、本発明は特
にデュアルインライン型のリードフレームに限るもので
はなく、フラットパック型のリードフレームおよびその
他のリードフレームまたはサーフェイスマウント型チッ
プ等の同様の機能を持つものであっても、同様の効果が
期待できるものである。
Although the above description describes the case where a semiconductor chip is mounted on a lead frame, the present invention is not limited to a dual-in-line type lead frame, but is applicable to a flat pack type lead frame and other lead frames. Alternatively, similar effects can be expected even if the chip has similar functions such as a surface mount chip.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の耐湿テストおよび半田付はテストをし
た後のプラスチック・パッケージ半導体装置の縦断面部
の要部を示す。 第2図は本発明方法を実施するためのプラズマ気相反応
装置の概要を示す。 第3図は第2図の装置のうちの基体部の拡大図を示す。 第4図はSIMS(二次イオン質量分析機)での測定評
価結果を示す。 第5図は従来例のプラスチックパッケージを耐湿テスト
および半田付はテストをした後の縦断面図の要部を示す
。 茗 ! 弔 ダ 図
FIG. 1 shows a main part of a plastic package semiconductor device in longitudinal section after the moisture resistance test and soldering test of the present invention. FIG. 2 shows an outline of a plasma gas phase reactor for carrying out the method of the present invention. FIG. 3 shows an enlarged view of the base portion of the device of FIG. FIG. 4 shows measurement evaluation results using SIMS (secondary ion mass spectrometer). FIG. 5 shows a main part of a conventional plastic package in a vertical sectional view after being subjected to a moisture resistance test and a soldering test. Meat! Funeral map

Claims (1)

【特許請求の範囲】 1、電子部品を基板上またはリードフレーム上に有機物
を含有する固着材により固着せしめる工程を有する電子
装置の作製方法において、前記電子装置を真空容器内に
保持し、真空排気せしめることにより、前記有機物中の
気体成分を脱気するとともに、前記基板またはリードフ
レーム上に吸着または付着した前記脱気した気体吸着成
分を除去する工程と、無機材料保護膜を形成する工程と
、有機樹脂封止をする工程とを有することを特徴とする
電子装置作製方法。 2、特許請求の範囲第1項において、基板またはリード
フレーム上の脱気した気体吸着成分を除去する工程とし
て、酸素または酸化物気体により、前記基板またはリー
ドフレーム表面をプラズマアッシング処理をする工程を
有することを特徴とする電子装置作製方法。 3、特許請求の範囲第1項において、基板またはリード
フレーム上に吸着した有機物を紫外光を照射することに
より除去する工程を有することを特徴とする電子装置作
製方法。 4、特許請求の範囲第1項において、真空容器内の圧力
は5×10^−^3〜1×10^−^8torrである
ことを特徴とする電子装置作製方法。 5、特許請求の範囲第1項において、真空容器は反応容
器内を排気し、基板またはリードフレーム上に吸着また
は付着した気体成分を除去するとともに、前記基板また
はリードフレーム上に形成される保護膜を外気に触れさ
せることなく同じ真空容器またはマルチチャンバ型真空
容器内での気相反応方法により形成することを特徴とす
る電子装置作製方法。
[Scope of Claims] 1. A method for manufacturing an electronic device comprising a step of fixing an electronic component onto a substrate or a lead frame using a fixing material containing an organic substance, wherein the electronic device is held in a vacuum container, and the electronic device is vacuum evacuated. a step of degassing gaseous components in the organic matter and removing the degassed gaseous adsorbed components adsorbed or attached to the substrate or lead frame; and a step of forming an inorganic material protective film. 1. A method for manufacturing an electronic device, comprising the step of encapsulating with an organic resin. 2. In claim 1, the step of removing the degassed gas-adsorbed components on the substrate or lead frame includes a step of subjecting the surface of the substrate or lead frame to plasma ashing using oxygen or oxide gas. A method for manufacturing an electronic device, comprising: 3. A method for manufacturing an electronic device according to claim 1, which comprises the step of removing organic matter adsorbed onto a substrate or lead frame by irradiating it with ultraviolet light. 4. A method for manufacturing an electronic device according to claim 1, characterized in that the pressure within the vacuum container is 5 x 10^-^3 to 1 x 10^-^8 torr. 5. In claim 1, the vacuum vessel evacuates the interior of the reaction vessel to remove gaseous components adsorbed or adhered to the substrate or lead frame, and also removes a protective film formed on the substrate or lead frame. A method for manufacturing an electronic device, characterized in that the electronic device is formed by a gas phase reaction method in the same vacuum container or a multi-chamber vacuum container without exposing it to outside air.
JP63256701A 1988-10-12 1988-10-12 Electronic device manufacturing method Expired - Fee Related JP2681167B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP63256701A JP2681167B2 (en) 1988-10-12 1988-10-12 Electronic device manufacturing method
EP89118909A EP0363936B1 (en) 1988-10-12 1989-10-11 Method of manufacturing electric devices
DE68926086T DE68926086T2 (en) 1988-10-12 1989-10-11 Method of making electrical assemblies
CN89108372A CN1023165C (en) 1988-10-12 1989-10-12 Method of manufacturing electric devices
KR1019890014618A KR930007519B1 (en) 1988-10-12 1989-10-12 Method of manufacturing electric device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63256701A JP2681167B2 (en) 1988-10-12 1988-10-12 Electronic device manufacturing method

Publications (2)

Publication Number Publication Date
JPH02102567A true JPH02102567A (en) 1990-04-16
JP2681167B2 JP2681167B2 (en) 1997-11-26

Family

ID=17296274

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63256701A Expired - Fee Related JP2681167B2 (en) 1988-10-12 1988-10-12 Electronic device manufacturing method

Country Status (1)

Country Link
JP (1) JP2681167B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995015579A1 (en) * 1993-11-30 1995-06-08 Giat Industries Method for the encapsulation of components or elecetronic units and devices encapsulated using said method
JP2009231680A (en) * 2008-03-25 2009-10-08 Panasonic Corp Surface treatment method and surface treatment device of substrate, and method of manufacturing semiconductor package
JP2012033626A (en) * 2010-07-29 2012-02-16 Nitto Denko Corp Film for flip-chip type semiconductor rear face, and use thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0244738A (en) * 1988-08-05 1990-02-14 Semiconductor Energy Lab Co Ltd Manufacture of electronic device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0244738A (en) * 1988-08-05 1990-02-14 Semiconductor Energy Lab Co Ltd Manufacture of electronic device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995015579A1 (en) * 1993-11-30 1995-06-08 Giat Industries Method for the encapsulation of components or elecetronic units and devices encapsulated using said method
FR2713396A1 (en) * 1993-11-30 1995-06-09 Giat Ind Sa A method of encapsulating electronic components or modules and electronic components or modules encapsulated by said method.
JP2009231680A (en) * 2008-03-25 2009-10-08 Panasonic Corp Surface treatment method and surface treatment device of substrate, and method of manufacturing semiconductor package
JP2012033626A (en) * 2010-07-29 2012-02-16 Nitto Denko Corp Film for flip-chip type semiconductor rear face, and use thereof
US10211083B2 (en) 2010-07-29 2019-02-19 Nitto Denko Corporation Film for flip chip type semiconductor back surface and its use

Also Published As

Publication number Publication date
JP2681167B2 (en) 1997-11-26

Similar Documents

Publication Publication Date Title
US5147822A (en) Plasma processing method for improving a package of a semiconductor device
JPH0244738A (en) Manufacture of electronic device
US6417028B2 (en) Method and apparatus for removing contaminants on electronic devices
US6191492B1 (en) Electronic device including a densified region
US5276351A (en) Electronic device and a manufacturing method for the same
JP2012169623A (en) Passivation layer for semiconductor device packaging
JPH02102567A (en) Manufacture of electronic device
US6756670B1 (en) Electronic device and its manufacturing method
JP3786465B2 (en) Semiconductor device and manufacturing method thereof
JPH02102564A (en) Electronic device and manufacture thereof
JPH0276249A (en) Electronic device and manufacture thereof
US5121187A (en) Electric device having a leadframe covered with an antioxidation film
JPH0260150A (en) Electronic device and manufacture thereof
JPH02181450A (en) Manufacture of electronic device
JPS59231840A (en) Semiconductor device and manufacture thereof
EP0363936B1 (en) Method of manufacturing electric devices
JPH02106952A (en) Electronic device
JPH05152378A (en) Tape carrier package
JPH0383365A (en) Electronic device
JPH0260154A (en) Lead frame and manufacture of electronic device incorporating the same
JPH0642495B2 (en) Electronic device and manufacturing method thereof
JPH02106954A (en) Electronic device
JP2683694B2 (en) Method of manufacturing electronic device
JPH01292849A (en) Manufacture of electronic device
JPH04206855A (en) Semiconductor device

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20070808

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080808

Year of fee payment: 11

LAPS Cancellation because of no payment of annual fees