JPH02101680A - Sector mark detector for optical disk device - Google Patents

Abstract

PURPOSE:To generate a false sector mark signal with accurate timing and to perform a processing appropriately by providing a measuring means for a sector mark, and a judging means to judge whether or not a detected sector mark is the one by erroneous detection. CONSTITUTION:A sector mark detection circuit 2 in a sector mark detector 1 issues a sector mark detecting signal (a) by a reproducing signal from an optical disk, and inputs it to a reset pulse generation circuit 4 and a latch signal generation circuit 11 in a false sector mark generation circuit 3. A false sector mark (h) generated from the circuit 3 is inputted to the circuit 4, and the circuit 4 generates a reset pulse (b) to a counter 5 preferentially to the signal (a), and starts up the counter 5 that has been reset by the signal (h) even when no signal (a) is detected. The counter 5 counts an impressed 1F clock, and when a count value arrives at a prescribed value, a synthetic sector mark signal (c) is outputted from a first decoder 6. In such a way, a second detector 7 inputs a timing signal (d) to the circuit 3, then, the signal (h) is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sector mark detection device for an optical disc device that detects the start points of a plurality of sectors formed on each track of an optical disc as a disc-shaped recording medium.

[Prior Art] Disc-shaped recording media are widely used in optical recording and reproducing devices.

In a recording/reproducing device (hereinafter referred to as an optical disk device) using the disk-shaped recording medium (hereinafter referred to as an optical disk), information data is recorded along concentric or spiral tracks of the optical disk. In this case, each track is divided into multiple sectors and used as data processing units.

That is, when recording or reproducing information on an optical disc, when performing random access or read/write control, a mark is placed to indicate the starting point of one recording, and this recording unit is called a sector. This mark is also called a sector mark.

The 112 sector mark is useful not only for the above-mentioned control but also for facilitating timing control during reading and writing of data and for making detection of periodic signals more reliable.

As described above, sector marks are effective for access control and signal detection during reading or writing, but the reliability of their detection must be sufficiently high. By the way, in optical disks, it is difficult to sufficiently reduce defects in the recording film, noise, etc., and it is necessary to create an apparatus that can tolerate errors of 10 -5 to 10 -6 bit error rate. Among the above errors, burst errors are more problematic than random errors.

The reliability of recorded data is improved by adding an error correction code. Furthermore, burst errors can be dispersed by using an interleaving method that records data in a distributed manner, and even fairly long burst errors can be dealt with.

However, this method cannot be applied to sector mark detection, and therefore cannot be put to practical use without some improvement in reliability.

For this reason, in the conventional example disclosed in Japanese Unexamined Patent Publication No. 61-5476, a method such as applying a gate is used to prevent erroneous detection of sector marks. However, if the rotational error is large, the gate width must be wide, and if we consider the case where marks cannot be detected continuously, the gate width must be even wider. Considering this, it is impossible to prevent erroneous detection near the sector mark (erroneous detection due to detection at 503, etc.).

For this reason, in the conventional example disclosed in Japanese Patent Application Laid-Open No. 60-201573, a periodic timer is used to indicate that sector marks should normally be detected, taking advantage of the fact that sector marks should be detected at equal intervals. A method has been adopted in which a pseudo sector mark signal is generated when no sector mark is detected at the end of the period and is used in place of the original sector mark signal.

[Problems to be Solved by the Invention] In the method disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 60-201573, after it is detected that no sector mark reading signal is generated, a pseudo sector mark signal starts to be generated. Therefore, the pseudo sector mark signal inevitably occurs at a later timing than when the sector mark read signal should normally occur.

If the above-mentioned timing deviates, there arises a disadvantage that the reliability of reading the original sector mark decreases.

In addition, as an example of related technology to the present invention, Japanese Patent Application No. 10597/1983
In No. 5, a method of measuring the sector mark interval using a crystal Q-oscillation clock, predicting the next sector mark position using this value, and generating a pseudo mark was shown.

However, even if this method can cope with the case where a sector mark is not detected, if a sector mark is detected incorrectly, the interpolation circuit may malfunction and an incorrect interpolation signal may be output.

The present invention has been made in view of the above-mentioned points, and is an optical disc that can generate a pseudo sector mark signal at an accurate timing without delay, and can cope with the case where a sector mark is detected incorrectly. An object of the present invention is to provide a sector mark detection device for a device.

[16 Means and Effects for Solving Problems] The present invention includes a measuring means for measuring the interval between sector mark signals detected from a sector mark area formed at the leading portion of an optical disc, and a sector mark signal based on the measurement output of this measuring means. pseudo sector mark signal generating means for generating a pseudo sector mark signal every time; means for determining whether the sector mark signal is erroneously detected; and when the sector mark signal is not detected, and when the sector mark signal is detected If the signal is erroneously detected, a timing signal is generated based on the pseudo sector mark signal, and if there is no erroneous detection in the sector where the sector mark signal is generated, a timing signal is generated based on this sector mark signal. By providing a synthetic sector mark signal generation means for generating a synthetic sector mark signal, when a sector mark is not detected, a high degree timing signal is generated by a pseudo sector mark signal.
Even if a sector mark is erroneously detected, a timing signal can be generated with high precision.

[Example] Hereinafter, the present invention will be specifically described with reference to the drawings.

1 to 9 relate to one embodiment of the present invention, FIG. 1 is a block diagram showing the configuration of a sector mark detection device of the first embodiment, and FIG. 2 is a block diagram of the reset pulse generation circuit in FIG. 1. 3 is a circuit diagram showing a specific configuration of the latch signal generation circuit in FIG. 1, and FIG. 4 is a circuit diagram showing a specific configuration of the load signal generation circuit in FIG. 1. Figure, 5th
1. FIG. 6 is a circuit diagram showing a specific configuration of the sector mark interval prediction circuit in FIG. 1, FIG. 6 is a timing chart for explaining the operation of each part of the first embodiment, and FIG. FIG. 8 is an explanatory diagram showing the counting operation area of the second and third counters. FIG. FIG. 9 is a timing chart for explaining the operation of FIG. 3.

As shown in FIG. 1, a sector mark detection device 1 includes a sector mark detection circuit 2 that generates a sector mark detection signal a based on a reproduced signal from an optical disk, and a pseudo sector mark signal that is generated by inputting this sector mark detection signal a. A pseudo sector mark signal generation circuit 3 that generates a sector mark detection signal a and a pseudo sector mark signal R are input,
A reset pulse generating circuit 4 outputs a reset pulse b in order to give priority to the sector mark detection signal a, a first counter 5 whose count value is reset by inputting the reset pulse b, and a first counter 5 connected to the output terminal of the counter 5. ,
When the count value reaches a set value, a first decoder 6 outputs a composite sector mark signal C, a second decoder 7 outputs a timing signal d, and an address mark detection circuit that generates an address mark detection signal l from the reproduced signal. It consists of 8.

The sector mark detection signal a output from the sector mark detection circuit 2 is sent to the reset pulse generation circuit 4 and the latch signal generation circuit 11 in the pseudo sector mark signal generation circuit 3.
is input. This reset pulse generation circuit 4 has a sixth
When the sector mark detection signal a is generated as shown in b in the figure, or when the sector mark detection signal @a is not generated, the first counter 5, which had been reset, is activated by the generation of the pseudo sector mark signal.

Thus, the first counter 5 counts the 1F clock applied to the clock input terminal. A first decoder 6 connected to the output terminal of this counter 5 has a relatively small count value <
decoder setting value), a composite sector mark signal C is output. This situation is shown in FIG. 6C. As a result, the timing of notifying the sector mark detection to the outside is slightly delayed, but there is always a certain delay (even when it cannot be detected)
can be supplied with

On the other hand, the second decoder 7 connected to the output terminal of the first counter 5 is set to a relatively large decoder setting value. That is, in FIG. 6, sector mark areas SM,
Identification area ID (in addition, there is an address mark area AM for synchronizing 10 in the ID), Gi 1? In each sector consisting of the block area GAP, the data area DATA, and the buffer area BUF, after the first counter 5 is cleared by the reset pulse b, it starts counting 1F clocks and then starts counting near the end of the data area or in the buffer area 7.
The count value of the counter 5 is set so as to reach the decoder setting value near the area.

Therefore, when this decoder setting value is reached, the second decoder 7 outputs the timing signal d shown in FIG. This pseudo sector mark generation circuit 3 starts its operation according to the timing signal d.The first latch 12 starts its operation according to the timing signal d.
As shown in e of FIG. 6, a latch output e of "H" is output, and this latch output e is applied to the reset terminals of the second counter 13 and the third counter 14, and the latch output e is applied to the reset terminals of the second counter 13 and the third counter 14, and is set to "L II" until then. Start the counting operation that had been reset.

No. 2 above. As shown in FIG. 6, the third counters 13 and 14 are for performing a counting operation from near the end of the data area to near the leading end of the ID section across the next sector mark area.

Both counters 13,14 count 1F clocks. Incidentally, as shown in FIG. 7, the first counter 5 is counted from the end of the sector mark area to the second... Third counter 13.1
This is for measuring the predetermined time (decoder setting value of the second decoder 7) until the start of the second decoder 7. Third
This is to cover the start time of counters 13 and 14.

The count value of the second counter 13 starting near the end of the data area is input to a sector mark interval prediction circuit 15 connected to its output terminal.

The sector mark interval prediction circuit 15 measures and latches the count value of the second counter 13 using the measurement signal f1 and the latch signal f2 output from the latch signal generation circuit 11. This wrap signal f2 is output at the timing when the sector mark detection signal a is detected, as shown by f2 in FIG.

Note that this measurement signal f1 is simply the sector mark detection signal a.
The latch signal f2 is output on the condition that the sector mark detection signal a and the address mark detection signal l are also output in the immediately preceding sector, not when the measurement signal f1 is detected. , further outputs an address mark detection signal 2, which is configured to be output only when two consecutive sector marks are adopted. This measurement signal f1 and latch signal f2
The latch signal generation circuit 11 that outputs the sector mark detection signal @a, the latch output e of the first latch 12, the previous sector mark adoption determination clock g1 of the load signal generation circuit 16, the load signal g2, and the address Mark detection signal 2 is input.

The latch output e of the first latch 12 is input to the load signal generation circuit 16, and the carry output of the second counter 13 is input as a reset signal. However,
This load signal generation circuit 16 outputs a load signal Q2 that loads the third counter 14 with the sector mark interval latched by the sector mark interval prediction circuit 15. This load signal g2 is generated for each sector near the end of the data area, as shown by g2 in FIG.

Note that a 2F clock is input to the load signal generation circuit 16.

The carry output of the second counter 13 resets the first latch 12 and the O-do signal generating circuit 16.

By the way, the third counter 14 is a down counter, and after receiving the value of one half of the sector mark interval prediction circuit 15 as a preset value by applying the load signal g2, it counts down. The third decoder 17 connected to the output terminal of the second decoder 14 predicts the same timing as the sector mark detection signal a and outputs a pseudo sector mark signal shown at h in FIG. This third decoder 17 also outputs the output i at the timing of the buffer area, and resets the reset pulse generation circuit 4.

Next, the configuration of the reset pulse generating circuit 4 will be explained using FIG. 2.

The sector mark detection signal a is applied to the data input end of the first D flip-flop (hereinafter referred to as D-FF) 21, taken in at the rising edge of the 2F clock, and output from the output EQ. This Q output is applied to the data input terminal of the second D-FF 22, and is inverted by the inverter 23.
The clock signal is input to the NAND circuit 24 from the output terminal n along with the Q output of the first D-FF 21.

The output of the NAND circuit 24 is the sector mark detection signal Q
The timing pulse corresponds to the rising edge of a, and is applied to the terminal of the third D-FF 26 through the OR circuit 25.

The above-mentioned reset terminal is connected to the output of the third detector 17 and the reset signal R generated when the device shutdown source is turned on.
3T is also applied via the OR circuit 27 and the OR circuit 25. Since the output i of the third decoder 17 is generated in the button 7 area immediately before the sector mark area, the D-FF
The 26th Q output is first reset in the buffer area to "L11" as shown in Figure 8, and the third D-,
After the output of the NAND circuit 24, which serves as a reset signal to the FF 26, returns to IIH11, it becomes "HII" at the rise of the 2F clock.

The output of the OR circuit 27 is the first. 211th-FF21
, 22 to reset the Q and G outputs.

Incidentally, in this embodiment, a pseudo sector mark signal is generated for each sector regardless of whether or not the sector mark detection signal a is generated. Note that this pseudo sector mark signal is controlled to be generated at the same position as the sector mark detection signal a. Therefore, if the sector mark detection signal a and the pseudo sector mark signal a occur at the same timing, the third D-F F 26 is set with either the pseudo sector mark signal or the sector mark detection signal a, and the first counter 5 may be started, but in order to perform the correct operation even if the timings of these two signals a and [1 are shifted, the configuration is such that a reset signal is generated to give priority to the sector mark detection signal a. There is. Therefore, the third decoder 1
7 pseudo sector mark signal 1), the Q output of the second D-FF 21, and the Q output of the third D-FF 26 are connected to the OR circuit 28.
, and is applied to the data input terminal of this third DFF 26.

For example, as shown in FIG. 8 (8), when the pseudo sector mark signal is delayed compared to the sector mark detection signal a, the Q output of the D-FF 26 is temporarily delayed due to the lid mark detection signal a. '', this ``blank'' signal is inputted again to the data input terminal of the DFF 26 via the OR circuit 28, and the Q output is maintained at the 1'' level, after which the pseudo sector mark signal 11 is output. Even if it becomes H°', there is no change in the Q output, and the sector mark detection signal j
3a is given priority and the first J counter 5 is activated.

Further, as shown in FIG. 8(B), when the pseudo sector mark signal is in advance, the Q output of the D-FF 26 is temporarily transferred to 'TOBI' due to the pseudo sector mark signal, and the force of the first counter 5 is・The Kunt operation starts, but the Q output is changed to 11 L again with the input of the sector mark detection signal j3a.
11, reset the count value of the first counter 5, and then restart the first counter 5.

In this way, the ret pulse generating circuit 4 gives priority to the sector mark detection signal a and generates the reset pulse b to the first counter 5.

Also, if the sector mark detection signal @a is not detected (for example, in Figure 6, 5ector N+3>, only a pseudo sector mark signal is generated, and at the timing of this signal, the third
D-FF 26 is set, and the counting operation of the first counter 5 is started. Even in this case, since the timing of generation of the pseudo sector mark signal is determined by measuring the timing at which the sector mark detection signal a is originally generated, the composite sector mark signal C is generated at an accurate time.

Next, the configuration of the latch signal generation circuit 11 shown in FIG. 3 will be described below with reference to the timing pulse shown in FIG. 9.

When the output e of the first latch 12 is at the "H11 level" (the reset of the second and third counters 13 and 14 is released,
When the sector mark detection circuit 2 outputs a pulse signal of "H11" which is the sector mark detection signal a, this signal is passed through the AND circuit 31 along with the above output e to the input terminal of the D-FF 32. applied, this D
-FF32 latches the D input "HII" and sets the Q output j to H11 (for example, a, e, at time t1 in FIG.
(see j). This D-FF 32 is provided to remember that a sector mark has been detected.

The signal of the output j is applied to the D input terminal of the next stage D-FF 33, and when the address mark detection signal 2 is applied to the clock terminal, the signal state of j is latched. Also, a load signal g2 is applied to the reset terminal, and this load signal Q
It is reset together with the DFF 32 at timing 2. In other words, this D-FF33 outputs II only when a sector mark is detected and an address mark is also detected (when that sector mark is decided to be adopted).
It becomes HII. (For example, it is shown at time t2 in FIG. 9.) The output of the D-FF 33 is applied to the D input terminal of the D-FF 34 in the next stage, and is generated prior to the load signal 02. When the judgment clock g1 is applied to the clock input terminal, the state of is latched at the output, and an output 1 is output from the Q output terminal.

(See time t3 in FIG. 9) Immediately after this, the D-FF 32.33 is reset by the load signal g2 (see, for example, time t4 in FIG. 9).
The role of this D-FF 34 is to latch the rejection.

By passing the output 1 of the D-FF 34 and the output of the first AND circuit 31 through the second AND circuit 35, a sector mark interval measurement clock "1" is generated (see time t5 in FIG. 9), and the next stage D - Applied to the clock input terminal of the FF36, latching the D input 'l-1'.

That is, with the D-FF 34 set, a sector mark is detected and the output of the first AND circuit 31 becomes H1.
1, the sector mark interval measurement clock f1 is output through the second AND circuit 35, and the state in which this clock f1 is output is latched by the D-FF 36 in the next stage, and the output m is output from the Q output terminal. put out. It goes without saying that the D-FF 32 is also set at this timing.

The output m of the above D-FF36 is the address mark detection signal 2
It is input to the third AND circuit 39 along with the Q output port of the D-FF 38 which latches the "H" of the D input.

Therefore, when the D-FF 36 is set, the address mark detection signal Z is output, sets the D-FF F1a, and when the Q output port is output, the sector mark interval latch signal f2 is output through the AND circuit 39. Output (
(See time t6 in FIG. 9).

In other words, the value measured earlier is latched with this latch signal f2.

Incidentally, the D-FF 38 is also reset by the load signal g2 together with the D-FF 32 and 33.

In addition, the load signal g is also applied to the reset terminal of the D-FF36.
2 is applied, so even if the measurement clock "1" is output, if no address mark is detected immediately, the Q output port of D-FF38 becomes I L II, so the sector mark interval latch signal f2 will not be output. For example, time t7 in FIG.
in the case of).

In this embodiment, three address marks are provided, and when at least one of them is detected, an address mark detection signal Z is output.

FIG. 4 shows the structure of the first latch and load signal generation circuit 16.

The first lap 12 is composed of a D-FF 12a, which latches the HI+ level voltage applied to the data input terminal with the output d of the second decoder 7 applied to the clock input terminal.
Latch output e to D -F F 41 data manual G1f
It is applied to tD. Further, this latch output e is passed through an AND circuit 42 together with the mutual outputs of the D-FF 41 to generate a lid mark adoption determination clock g1.

The Q output of this D-FF 41 is applied to the data input 'IQD of the next stage D-FF 43, and together with the Q output of the D-FF 43, a load signal g2 is generated through the NAND circuit 44.

Also, the carry pulse of the second counter 13 is the D-FF45.
It is applied to the data input end of , and is outputted from the output Oat Q to the OR circuit 46 by one output per 2F. This OR circuit 46 has a reset signal QR3T generated when the power supply A is turned on.
is also input, and the output of this OR circuit 46 is D-FFI 2
a, 41. It is applied to the reset terminal of 43.

The above D-FF41, 43. The configuration of the NAND circuit 44 is the third
The configuration of the latch signal generation circuit 11 shown in the figure is almost the same.

Therefore, using the latch output e of the first latch 12 as an input,
Occurs in each sector near the end of the data area [J-
outputs a code signal Q2.

By applying the load signal g2 to the load terminal of the third counter 14, the sector mark interval prediction circuit 15
The pulse generating circuit loads data that depends on the sector mark interval latched to , starts counting near the end of the data area, and resets the pseudo sector mark signal at the position of the next sector mark detection signal a. It is set to output to 4.

Next, the configuration of the sector mark interval prediction circuit 15 is shown in FIG.

The sector mark interval measurement clock f1 output from the latch signal generation circuit 11 is applied to the clock input terminals of the first-stage Gino 1 to register 51, and the latch signal generation circuit 11
The latch signal f2 output from the shift registers 51a and 51b in the second and subsequent stages.

. . , 51m, only valid sector mark interval data is applied to the measurement data latch shift 1 registers 51a, 51b.

..., taken into 51m, past n pieces (51a, ...
51m is sequentially multiplied by 25 up to n pieces).

The data accumulated in the shift registers 51a, . Also, the data value (rounded off, etc.) is 1/n, that is, the average value.If the number n of shift registers is selected as the factorial of 2, the circuit that makes it 1/[) is the lower pit. It can be substituted by truncating .

The average value obtained in this way is input to the predicted value register 54, and the latch signal f2 is delayed by the delay 55. Supplied as data.

The sector mark interval prediction circuit 15 allows the sector mark interval to be accurately measured.

In this embodiment, the sector mark detection circuit 2 detects the sector mark pattern recorded in the sector mark area and outputs the sector mark detection signal a, and the pseudo sector mark generation circuit 3 outputs the sector mark detection signal a. A pseudo sector mark signal is generated at the timing when a is predicted to be detected, and these sector mark detections (based on the M number a and the pseudo sector mark signal, are combined to give priority to the sector mark detection signal a, and generate a lid mark). Since the signal C is generated, by using this synthetic sector marking @C, it is possible to perform highly reliable control of random access, etc., and control of write/read. When the power is turned on, a default value is stored in the sector mark interval prediction circuit 15, and the first two pseudo sector mark signals are outputted with this value.

In the above embodiment, the sector mark detection signal j3a and the pseudo sector mark signal R are used to generate the composite sector mark signal C by giving priority to the lid mark detection signal a, but as shown in the third embodiment described later, If there is a high possibility of false detection, there is a method that internally uses pseudo sector marks.

FIG. 10 shows the configuration of a sector mark interval prediction circuit 60 in a second embodiment of the present invention. This circuit 60 can be used as the sector mark interval prediction circuit 15 in FIG.

The count data representing the sector mark interval output from the second counter 13 is stored in the measurement data wrap register 61.
and is latched by the sector mark interval measurement clock f1 output from the latch signal generation circuit 11. This latched data is input to a subtractor 62, and the latched data value is subtracted by a predicted value register 63 using the latch signal f2 as a clock. This reduced data value is input to the divider 64 and is converted into a data value reduced to 1/x. Note that when the value is set to 1/x, the fraction is rounded off or rounded off. The output of this interrupter 64 is the output of the adder 6
5 and is added to the data value latched by the prediction value register 63, and this added data is given as a prediction (data to the register 63. Therefore, the sector mark interval latch clock f2 is applied. Then, the output data value of the Q adder 65 is stored in the predicted value register 63 as a new predicted value.

This sector mark interval prediction circuit 60 can operate very stably by adjusting (setting) the division number χ (or 1/X when used as a multiplier) of the divider 64 to an appropriate value. Become.

Note that if the notation X is chosen to be a factorial of 2, the operation is performed by truncating the lower bits. It is best to select X to the extent of positive and negative fluctuations.

According to the second embodiment, the circuit scale can be made smaller than that of the sector mark interval prediction circuit 15 used in the first embodiment, and the same effect can be achieved.

Next, a third embodiment of the present invention will be described.

FIG. 11 shows a pseudo sector mark employing circuit 71 in a third embodiment of the present invention.

This pseudo sector mark adoption circuit 71 is a circuit for internally re-adopting a pseudo sector mark when it is determined that the sector mark detection signal a h is less than an erroneous lid mark, as shown in FIG. In the first embodiment, the counter 5 is inserted between the first counter 5 and the second data 7.

In FIG. 11, the output of the first counter 5 is input to a wrap 74 via a two's complement circuit 72 and a selector 73 (consisting of AND circuits 73a, 73b and an OR circuit 73G).

On the other hand, the sector mark detection signal a and the latch output e are input to an AND circuit 75, and this output is input to an AND circuit 73b forming the selector 73.
The output of the two's complement circuit 72 is output to the latch 74 when the output of the two's complement circuit 72 is at H''.

Further, the output of this AND circuit 75 is input to the A circuit 76 along with the pseudo sector mark signal, and the output of this OR circuit 76 is inputted to the A circuit 76.
The output is applied to the input terminal of the latch 74 via the delay circuit 77.

Therefore, when the first counter 5 starts counting in response to the pseudo sector mark signal and a sector mark is detected by the sector mark detection signal a, the output of the AND circuit 75 becomes 73 is the first
The count of the non-counter 5 (directly) is outputted to the latch 74 as its two's complement value.
The output of 5 is applied as a clock to the latch 74 via the A circuit 76 and the delay circuit 77, and as a result, a value obtained by converting the count value corresponding to the interval between the pseudo sector mark and the sector mark detected as a two's complement number is obtained. , is stored in latch 74.

The output of the 10,000th counter 5 is input to an adder 79 together with the output passed through a latch 74 and an AND circuit 78, and after being added, is input to a second decoder 7.

The output d of the second decoder 7 is applied to the reset terminal of the D-FF 80, and when the output d is ii L ++, the D-FF 80 is put into a reset state.

This D-FF 80 is the D-FF of the latch signal generation circuit 11.
Output k of F33 (see Figure 3) (II H if a sector mark is detected and an address mark is also detected)
It becomes 11. ) is applied as a clock, and this clock latches 'l-1' of the D input.
The inverted output signal of the FF 80 becomes a gate signal of an AND circuit 78 to which the output of the latch 74 is input.

Therefore, the value stored in the latch 74 is the output k
Only when the output is not output, the AND circuit 78 is opened and the output is input to the adder 79, where it is added to the output of the first counter 5. On the other hand, if a sector mark is detected but no address mark is detected, only the counter value of the first counter 5 is stored in the adder 79, and in this case, the second decoder 7
The input to the first counter is the count (direction itself) of the first counter.

Note that the AND circuits 73a, 73b, and the AND circuit 78 of the selector 73 are described together for the number of bits of the latch 74.

The operation of this pseudo sector mark adoption circuit 71 will be explained below with reference to FIG.

As shown in FIGS. 12(A) and 12(B), the first counter 5 starts due to the pseudo sector mark, and if the sector mark is detected, the process starts from the generation of the pseudo sector mark to the detection of the sector mark. A two's complement number of the count value corresponding to the time interval C is stored in the latch 74. This storage is performed by applying the output of the AND circuit 75 to the clock input terminal through the OR circuit 76 and the delay circuit 77. Also, the first counter 5 restarts when the sector mark is reached.

On the other hand, the input to the second decoder 7 is the count value of the first counter 5 stored in the latch 74 ('1 is added to the value of ab shown in FIG. 12 (8)). .Here, a does not indicate the original transfer position.

If the address mark continues as it is without being detected, the detected sector mark will be treated as an error and a pseudo sector mark will be adopted again, and when a-b becomes the value of the second decoder 7, the output d will be output. Dimensions.

On the other hand, when the address mark is detected, the output k becomes D-
It is clocked and applied to FF80, and the inverted output port is L I
+, so the output of the AND circuit 78 becomes φ'', so the input to the second de-der 7 becomes the count value of the first counter 5 itself, which is not shown in FIG. 12(B). The second decoder 7 outputs an output d at the original transfer position a using the address mark.

Unlike in Figure 12 (8) (B) above, if a sector mark is detected first and then a fake sector mark is detected, the process from detection of the sector mark to generation of the pseudo sector mark is A value corresponding to the interval is stored in latch 74. This value is indicated by C in FIGS. 12(C) and 12(D).

At this time, the input to the second decoder 7 becomes 1' a + c as shown in FIG. 12(C).

If no address mark is detected, a pseudo sector mark is adopted, and when a+C becomes the value of the second decoder 7, an output d is produced.

On the other hand, when an address mark is detected, the AND circuit 75
The output of φ becomes φ, and the value of the first counter 5, which has started from 1 due to the detection of the address mark, becomes the second data: 1-.
The signal is input as is to the decoder 7, and when it reaches the value of the second decoder 7, it outputs the output d.

Although the first embodiment described above judges whether or not the detected sector mark is a false detection, and does not perform any particular processing in the case of false detection, this third embodiment employs a pseudo sector mark. , it is possible to perform a sector mark detection operation (generation of a composite sector mark signal) with fewer errors. Therefore, highly reliable recording/reproduction control operations can be performed.

For example, even if the optical disc has many defects or normal signals cannot be obtained during seek, stable interpolation can always be performed, and each scale gate signal and control signal can be stably output. It becomes possible to continue.

"Effects of the Invention" As described above, according to the present invention, since the sector mark interval prediction means is provided and the means for determining whether or not the detected sector mark is a false detection, the determining means is provided. Appropriate processing can be performed using the output.

[Brief explanation of drawings]

1 to 9 relate to one embodiment of the present invention, FIG. 1 is a block diagram showing the configuration of a sector mark detection device of the first embodiment, and FIG. 2 is a block diagram of the reset pulse generation circuit in FIG. 1. 3 is a circuit diagram showing a specific configuration of the latch signal generation circuit in FIG. 1, and FIG. 4 is a circuit diagram showing a specific configuration of the load signal generation circuit in FIG. 1. Figure, 5th
1 is a circuit diagram showing a specific configuration of the sector mark interval prediction circuit in FIG. 1, FIG. 6 is a timing diagram for explaining the operation of each part of the first embodiment, and FIG. Fig. 8 is an explanatory diagram showing the counting operation area of the second and third counters, and Fig. 8 is a timing chart showing the timing at which a reset pulse is generated when a pseudo sector mark signal is generated at a timing different from that of a sector mark detection signal. FIG. 9 is a timing chart for explaining the operation of FIG. 3, and FIG.
Figure 11 is a block diagram showing the configuration of the square mark interval prediction circuit according to the second embodiment of the present invention, and Fig. 11 shows the configuration of the pseudo sector mark adoption circuit according to the third embodiment of the present invention. The block diagram and FIG. 12 are explanatory diagrams of the operation of the third embodiment. 1... Sector mark detection device 2... Sector mark detection circuit 3... Pseudo sector mark signal generation circuit 4... Ret pulse generation circuit 5... First counter 6, 7... Decoder 8.
... Address mark detection circuit 11 ... Latch signal generation circuit 13 ... Second counter 14 ... Third counter 1
5...Sector Mark Interval Prediction Circuit Agent Patent Attorney Ito License 7 Figure 8

Claims (1)

[Claims] 1. Means for measuring the interval of sector mark signals detected from the sector mark area recorded at the beginning of each sector on an optical disk; A sector mark detection device for an optical disc device, comprising: means for generating a pseudo sector mark signal; and means for determining whether or not the sector mark signal is erroneously detected. 2. Means for measuring the interval of sector mark signals detected from the sector mark area recorded at the beginning of each sector on an optical disc, means for averaging the measurement output of this measuring means, and means for averaging. 1. A sector mark detection device for an optical disc device, comprising: means for generating a pseudo sector mark signal for each sector based on the output of the sector mark detection device. 3. Means for measuring the interval between sector mark signals detected from the sector mark area recorded at the beginning of each sector on an optical disk, and generating a pseudo sector mark signal for each sector based on the measurement output of this measuring means. means for determining whether or not the sector mark signal is a false detection; and a means for determining whether or not the sector mark signal is a false detection; A sector mark detection device for an optical disc device, comprising: processing means for prioritizing a sector mark signal.