JPH02100165A - Method for making access to dual port memory - Google Patents

Abstract

PURPOSE:To perform the contention control of memory access only by a software processing by establishing its own flag area at a flag area when no flag is established, and obtaining an access right to a memory area. CONSTITUTION:A processor which desires to obtain the access right of a dual port memory 1 out of two processors 2a and 2c reads out the flag area of the dual port memory 1. And the processor, after confirming whether or not the flag to request the access right is established from another processor, obtains the access right by establishing its own flag when no flag is confirmed. Furthermore, the establishment of the flag by another processor can be performed by releasing its own flag after completing access. In such a way, it is possible to perform the contention control of the dual port memory 1 between the two processors 2a and 2c via the flag area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dual port memory access method when two processors perform data communication via a dual port memory.

(Prior Art) Fig. 4 is a diagram showing a conventional hardware configuration that performs data communication via a dual port memory using a processor with a HOLD function. In Fig. 5, (1) is a dual port memory, ( 2a).

(2b) is a processor with a HOLD function connected to this dual port memory (1), (3a) is a HOLD
A data bus (3b) is an HO bus that passes data between a functional processor (2a) and a dual port memory (1)
A data bus (4a) that passes data between the processor with LD type function (2b) and the dual port memory (1)
is an address bus that outputs an address from the processor (2a) with HOLD function to the dual port memory (1), (
4b) is an address bus that outputs the address from the processor with HOLD function (2b) to the dual port memory (1), and (5a) is the processor with HOLD function (2a).
) is the write signal branch line that sends the write signal from the processor (2b) to the dual port memory (1), (5b) is the write a line that sends the write signal from the processor (2b) with the HOLD function to the dual port memory (1), ( 6a) is a lead wire that outputs the read signal from the processor (2a) with HOLD function to the dual port memory (1), (6b) is the HOLD
The lead wire (7a) is H for sending the read signal from the functional processor (2b) to the dual port memory (1).
The chip select signal line (7b) outputs the chip select signal from the processor with OLD function (2a) to the dual port memory (1),
2b) is the chip select signal line that outputs the chip select signal to the dual port memory (1), (8a) is the dual port memory (1) and each processor (2a), (
2b) accesses the same address and a busy signal line (8b) informs the processor (2a) that a collision has occurred;
) is dual-port memory (1) for each processor (2a
) and (2b) are busy signal lines that notify the processor (2b) that the same address has been accessed and a collision has occurred.

Next, the operation will be explained. In order to write data from the processor (2a) with the HOLDlil function to an address in the dual port memory (1), the processor (2a) first uses the address bus (4a) to write the address to which the data is to be written. While sending the signal to the dual port memory (1), the chip select signal line (7
According to a), the chip select signal is sent to the dual port memory (1) to confirm the address, and then the processor (2a) uses the data bus (3a) to send the write data to the dual port memory (1), and the write Signal line(
5a), data can be written to any address of the dual port memory (1) by issuing a write signal.

In addition, the dual port memory (1) is connected from the processor (2a).
), the processor (
2a) is the dual port memory (1) that stores the data to be read using the address bus (4a).
The address signal of the upper address is connected to the dual port memory (
1) and sends a chip select signal to the chip select signal line (7a) to the dual port memory (1),
After determining the address, the processor (2a) issues a read signal to the read signal line (6a), so that the dual port memory (1) transfers the data stored at the address specified by the address signal to the data bus (3a). The processor (2a) reads this data.

Similarly to the processor (2a) above, when writing data from the processor (2b) to the dual port memory (1), the processor (2b) sends an address signal of the address to which data is to be written via the address bus (4b), and Connect the select signal to the chip select signal line (7
b), and then send the data you want to write to the data bus (3).
Data can be written to any address of the dual port memory (1) by outputting a write signal to the write signal line (5b). In addition, when reading data stored in an arbitrary address of the dual port memory (1) from the processor (2b), an address signal is sent to the address bus (4b), and a chip select signal is sent to the chip select signal line (7b). Data stored at any address in the dual port memory (1) can be read by outputting the data to the dual port memory (1), determining the address, and issuing a read signal to the read signal line (6b).

Now, processors with HOLD function (2a), (2
If you try to write different data to the same address at the same time from b), the data cannot be guaranteed, so use dual port memory (1) on the side to which a low priority processor is connected.
gives a busy signal. Here, if processor (2b) is a low-priority processor, then processor (2b) is
If you try to write data from a), (2b),
The dual port memory (1) outputs a busy signal to the busy signal line (8b), and when this signal is input to the HOLD input of the processor (2b), the processor (2b) interrupts the write operation. ), no data conflicts occur. Also, if one processor is writing data to a certain address in the dual port memory (1) and the other processor tries to read or write data to the same address, a busy signal is sent and this is sent to the HOLD input. By keeping the processor connected, the processor that started running later will suspend its operation, so data conflicts will not occur in the dual port memory (1), but if a processor that does not have a HOLD function is connected to the dual port memory (1) In this case, even if the dual port memory (1) outputs a busy signal, the processor operation cannot be stopped.
Write data cannot be guaranteed.

[Problem to be solved by the invention]

Data communication between processors via conventional dual-port memory operates as described above, so when a contention for dual-port memory data occurs between both processors,
A processor that has a HOLD function can output a busy signal to the other processor and interrupt its operation, but for a processor that does not have a HOLD function, the busy signal is not valid and it is possible to read dual port memory,
Write data cannot be guaranteed. Therefore,)(
When accessing dual-port memory with a processor that does not have the OLD function, it is necessary to add additional hardware to ensure that both processors do not access the same address, which limits the processor used. There was a problem that the

This invention was made in order to solve the above-mentioned problems.
It is an object of the present invention to provide a method for accessing a dual port memory that allows communication via the dual port memory even when using a processor that does not have a D type function.

[Means to solve the problem]

A dual port memory access method according to the present invention allows two processors to mutually access the dual port memory and perform data communication between the processors via a buffer area, wherein each processor A flag area is provided in which each processor sets a flag for requesting memory area access rights when competing for memory area access rights between processors.
Each processor mutually monitors the establishment of the other party's flag, and when the flag is not established, establishes its own flag in the flag area,
This allows access rights to the memory area to be obtained.

[Effect]

According to this invention, a processor that wants to obtain access rights to the dual port memory of two processors reads the flag area in the dual port memory, and
Checks whether a flag for requesting access rights has been established from another processor, and if the flag is not confirmed, establishes its own flag to obtain access rights, and after the access is completed, clears the self flag. By allowing flags of other processors to be established, dual port memory contention control is performed between both processors through the flag area.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a diagram showing the hardware configuration of a dual port memory access method according to an embodiment of the present invention corresponding to FIG. It is assumed that the memory is accessed according to the memory map shown below. Also (2c), (2
d) is a processor without a HOLD function. Second
The memory map i' (a) in Figure (a) is the occupancy flag for controlling access rights to the DPM management area, and the memory map i' (a) in Figure 2 (
As shown in b), an M bit (9m) corresponding to the processor (2c) and an S bit (9s) corresponding to the processor (2d) are defined.

(lla) to (lln) are processors (2c),
(2d) This is a buffer area used for data transfer.

(lO) is a buffer management area for managing the status of buffer areas (ila) to (lln).

Next, the operation will be explained based on the flowchart shown in FIGS. 3(a) to 3(b). When the processors (2c) and (2d) without the HOLD function each access the buffer of the dual port memory, the processors (2c) and (2d) each access the buffer of the dual port memory as shown in Fig. 3 (
a) Access the buffer according to the flowchart shown in . First, the processing of the processor (2c) will be described. Processor (2C) has dual port memory (1)
When writing or reading data to or from the buffers (lla) to (lln), get (establish) the occupancy flag (9) in order to know which buffers can be used.
Step 5al), the details of which are shown in FIG. 3(b). When getting the occupancy flag (9), first a counter is used to measure whether or not the occupancy flag can be established within a certain period. Read the occupancy flag (9) (step 5b2), determine the S bit (9s) (step 5b3), and if the S bit (9S) is 0, M
Set bit (9g+) to 1 (step 5b4), read the occupancy flag (9) again (step 5b5),
Determine whether M bit (9+a) is 1 (step 5
b6), which means that when the processor (2d) sets the occupied flag in the S bit (9s) in a byte configuration, the M bit (9s)
0M bits (9
If +a) is 1, confirm that the S bit (9S) is 0 (step 5b7).

If the S bit (9S) is 0, the occupancy flag (9) can be obtained. If first occupied flag (9)
Read and judge the S bit (9s) Step 5b3
), if not 0, add 1 to the counter.Step 5
b9), compared with the preset value, step 5bl
o) If it is larger, the count is over and the process ends with an error.

If the value of the counter is determined and is smaller than or equal to the set value (step 5blo), then the ``re-occupancy flag (9
) (step 5b2), determine whether the S bit (9S) is 0 (step 5b3),
) is O, set M bit (9m) to 1 Step 5
b4), Steps sb5 to 5b6) to determine whether the M bit (9m) is set to 1 in the occupancy flag.
m) is 00, add 1 to the counter (step 5b9
), the counter is determined (step 5b1O), and if the count is not over, the process of setting the M bit (9m) to 1 is performed again (steps sb2 to 5b6). M bit (9+
++) can be set to 1 (step 5b9)
, determine whether the S bit (9S) is 0 or not in step 5b.
7), if it is not 0, there is a possibility that the processor (2d) also accessed the occupancy flag (9) at the same time, so set the M bit (9m) to 0, step 5b8), and re-enter the M bit (9m).
Perform processing to set the bit to 1 (steps sb9 to 5bl
O1sb2 to 5b7), the occupancy flag (9) is set to g
After reading the DPM management area (10) and checking which buffer can be used (step 5a2),
Now, when the buffer (11a) is found to be usable, the occupancy flag (9) is put (released).
Then, the processor (2d) makes the DPM management area (10) accessible (step 5a3). The 11 processor (2c) puts the occupancy flag as shown in FIG.
).

First, the processor (2c) sets the counter to O (step 5cl) and reads the occupancy flag (9) (step 5c).
2), determine the S bit (step 5c3); if it is 1, add 1 to the counter (step 5c7); if the counter does not count over (step 5c8),
The occupancy flag (9) is read again (step 5c2), and if the counter exceeds the count, the process ends with an error. Read the occupancy flag (9) (step 5c2),
If it is O, set the M bit (9m) of the occupancy flag (9) to 0 (step 5c4)e and re-occupy the flag (9).
) (step 5c5) and the M bit (911) is 0.
If it is not 0, repeat the process of setting the M bit (9IQ) of occupancy flag (9) to 0 (steps sc7, sc8, sc2 to 5c).
6).

If M bit (9m) is O (step 5c6)
This means that the occupancy flag is put (step 5a3)
, the processor (2c) inputs and outputs data to the buffer (11,a) (step 5a4). Processor (2C)
After inputting/outputting data to/from the buffer (lla), gets the occupancy flag again L/ (Step 5ad
), writes information indicating completion of access to the buffer (11a) in the DPM management area (lG) (step 5ad) and puts the % occupancy flag (9) (step 5a7).

Next, the processing of the processor (2d) will be described. When the processor (2d) writes data to or reads data from the buffers (lla) to (lln) of the dual port memory (1), the processor (2d) knows which buffers can be used.
Get the occupancy flag (9) (step 5at).

The details are shown in FIG. 3(d). Set the occupancy flag (9) to g
ET, first clear the counter in step 5d.
i), Read the occupancy flag (9) (step 5d2),
Determine the M bit (9m) (step 5d3), and if the M bit (9m) is 0, set the S bit (9S) to 1 (step 5d4), and set the occupancy flag (9) again.
(Step 5d5) and determine whether the S bit (9S) is 1 (Step 5d6).
If is 1, confirm that the M bit (9m) is 0 (step 5d7). If the M bit (9a+) is O, it means that the occupancy flag (9) has been obtained. If you first read the occupancy flag (9) and read the M bit (
If it is not 0, add 1 to the counter (step 5d9), and compare it with a preset value (step 5dlO); if it is larger, the count is over and the process ends with an error.

If the value of the counter is determined (step 5dlO), and it is smaller than or equal to the set value, the occupancy flag (9) is read again (step 5d2), and it is determined whether the M bit (9m) is O (step 5d3). M bit (9+g) is 0, set S bit (9S) to 1 Step 5d4
), determine whether the S bit (9S) is set to 1 in the occupancy flag (steps sd5 to 5d6), S bit (9S)
If is 0, add 1 to the counter (step 5d9),
Determine the counter (step 5dlo), and if the count is not over, perform processing to set the S bit (9S) to 1 again (steps sd2 to 5d8), S bit (9s)
If it can be set to 1 (step 5d6), determine whether the M bit (9m) is 0 or not (step sd7).
, O, there is a possibility that the processor (2C) also accessed the occupancy flag (9) at the same time.
The bit (9S) is set to 0 (step 5d8), and the S bit is set to 1 again (steps sd9 to 5dlO).
1sd2~5d7), ge the occupancy flag (9)
After t L/, read the DPM management area (10) and check which buffer is usable (step 5ad) eAnd if it turns out that buffer y (lla) is now available, put the occupancy flag (9) L /% Processor (2C) makes DPM management area (IO) accessible (step 5a3), Processor (2d)
The process of putting the occupancy flag will be explained using FIG. 3(e).

First, the processor (2d) sets the counter to 0 (step 5el) and reads the divination flag (9) (step 5e).
2), determine the M bit (step 5e3), and if it is 1, add 1 to the counter (step 5e7), and if the counter does not exceed the count (step 5e
8) reads the occupancy flag (9) again (step 5e
2). If the counter exceeds the count, the process ends with an error. Read the occupancy flag (9) (step 5
e2) Determine M bit (9m) (Step 5e3
) If O, S bit (9S) of occupancy flag (9)
Set to 0 (Step 5e4), and read the occupancy flag (9) again (Step 5es).
) is 0 (step 5e6) If not, set the S bit (9S) of the occupancy flag (9) to 0 again.
(Steps se7, sea, s
e2 to 5e6), if the S bit (9S) is 0 (step 5e6), it means that the occupancy flag has been put (step 5a3), and the processor (2d) inputs and outputs data to the buffer f (llb). (Step 5
a4), the processor (2d) is a buffer (llb)
When you finish inputting and outputting data to , get the occupancy flag again.
L/ (step 5a5), DPM management area (10
) is written to indicate the completion of access to the buffer (lla) (step 5ad), and the occupancy flag (9) is put (step 5a7).

In the above embodiment, the occupancy flag is set to the same address on the dual port memory, but it may be set to a different address.
Exactly the same access method is possible without using the function.

Further, the processor in the above embodiment may be a combination of a processor and a peripheral circuit, or may have functions equivalent to a processor, and the dual port memory may be one that can detect memory conflicts and does not have the function of issuing a busy signal. good.

(Effects of the Invention) As described above, according to the present invention, a flag area is provided in the dual port memory in which two processors can alternately establish their own flags, and both processors can establish their own flags by the other processor. The configuration is configured so that it can acquire dual-port memory access rights by setting a self-flag while confirming that no This has the effect of providing a high-performance dual-port memory access method.

[Brief explanation of the drawing]

FIG. 1 is a hardware configuration diagram of a dual port memory access method according to an embodiment of the present invention, and FIG. 2(a)
(b) is a memory map of the dual port memory used in the present invention, FIG. 3 (a) to (e) are flowcharts showing how the processor accesses the dual port memory in this embodiment, and FIG. FIG. 2 is a hardware configuration diagram using a dual port memory access method. In the figure, (1) is dual port memory, (2a)
(2b) is a processor with HOLD function, (2C)
(2d) is a processor without HOLD function, (3a)
(3b) is a data bus, (4a) (4b) is an address bus, (9) is an occupancy flag, (10) is a DPM management area, and (lla) to (lln) are buffer areas.

Claims (1)

[Claims] In a dual port memory access method in which two processors mutually access the dual port memory and data communication is performed between the processors via a buffer area, access rights to the memory area are granted between each processor to the dual port memory. A flag area is provided in which each processor sets a flag for requesting access rights to a memory area when competing, each processor mutually monitors the establishment of the other party's flag, and establishes its own flag in the flag area when the flag is not established. A dual port memory access method characterized by obtaining access rights to a memory area.